From 234547bf5ea7f64c93bdf49c7992b5cbdd87b73f Mon Sep 17 00:00:00 2001
From: mark <mark@NetBSD.org>
Date: Tue, 2 Apr 1996 21:45:25 +0000
Subject: [PATCH] Add CPU ID's for the DEC StrongARM-110 processor. Update
 control register bit definitions as the SA-110 has separate instruction and
 data caches.

---
 sys/arch/arm32/include/cpu.h | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/sys/arch/arm32/include/cpu.h b/sys/arch/arm32/include/cpu.h
index cae5a79ccb43..3d79f4d74172 100644
--- a/sys/arch/arm32/include/cpu.h
+++ b/sys/arch/arm32/include/cpu.h
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.5 1996/03/13 21:18:06 mark Exp $ */
+/* $NetBSD: cpu.h,v 1.6 1996/04/02 21:45:25 mark Exp $ */
 
 /*
  * Copyright (c) 1994-1996 Mark Brinicombe.
@@ -97,6 +97,7 @@
 
 #define CPU_ID_DESIGNER_MASK	0xff000000
 #define CPU_ID_ARM_LTD		0x41000000
+#define CPU_ID_DEC		0x44000000
 #define CPU_ID_MAKER_MASK	0x00ff0000
 #define CPU_ID_GPS		0x00560000
 #define CPU_ID_VLSI		0x00000000
@@ -104,11 +105,12 @@
 #define ID_ARM610		0x00000610
 #define ID_ARM700		0x00007000
 #define ID_ARM710		0x00007100
+#define ID_SARM110		0x0000a100
 #define CPU_ID_REVISION_MASK	0x0000000f
 
-#define CPU_CONTROL_MMU_ENABLE  0x0001
-#define CPU_CONTROL_AFLT_ENABLE 0x0002
-#define CPU_CONTROL_IDC_ENABLE  0x0004
+#define CPU_CONTROL_MMU_ENABLE	0x0001
+#define CPU_CONTROL_AFLT_ENABLE	0x0002
+#define CPU_CONTROL_DC_ENABLE	0x0004
 #define CPU_CONTROL_WBUF_ENABLE 0x0008
 #define CPU_CONTROL_32BP_ENABLE 0x0010
 #define CPU_CONTROL_32BD_ENABLE 0x0020
@@ -117,6 +119,15 @@
 #define CPU_CONTROL_SYST_ENABLE 0x0100
 #define CPU_CONTROL_ROM_ENABLE	0x0200
 #define CPU_CONTROL_CPCLK	0x0400
+#define CPU_CONTROL_IC_ENABLE   0x1000
+
+/* StrongARM has separate instruction and data caches */
+
+#ifdef CPU_SA
+#define CPU_CONTROL_IDC_ENABLE	(CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE)
+#else
+#define CPU_CONTROL_IDC_ENABLE	CPU_CONTROL_DC_ENABLE
+#endif
 
 #define FAULT_TYPE_MASK 0x0f
 #define FAULT_USER      0x10