Patch a few of the holes in the machine-dependent part of this driver.
Sync the m.i. part with the Atari.
This commit is contained in:
briggs
parent
1fd44da3df
commit
229c36d3dd
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@ -1,4 +1,4 @@
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/* $NetBSD: mac68k5380.c,v 1.16 1996/01/11 15:25:53 briggs Exp $ */
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/* $NetBSD: mac68k5380.c,v 1.17 1996/01/24 06:02:06 briggs Exp $ */
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/*
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* Copyright (c) 1995 Allen Briggs
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@ -66,7 +66,7 @@
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#undef DBG_PIO /* Show the polled-I/O process */
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#undef DBG_INF /* Show information transfer process */
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#define DBG_NOSTATIC /* No static functions, all in DDB trace*/
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#undef DBG_PID /* Keep track of driver */
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#define DBG_PID 20 /* Keep track of driver */
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#undef REAL_DMA /* Use DMA if sensible */
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#define fair_to_keep_dma() 1
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#define claimed_dma() 1
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@ -175,9 +175,9 @@ int pdma_5380_dir = 0;
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u_char *pending_5380_data;
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u_long pending_5380_count;
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#define DEBUG 1 /* Maybe we try with this off eventually. */
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#define NCR5380_PDMA_DEBUG 1 /* Maybe we try with this off eventually. */
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#if DEBUG
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#if NCR5380_PDMA_DEBUG
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int pdma_5380_sends = 0;
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int pdma_5380_bytes = 0;
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@ -189,12 +189,13 @@ pdma_stat()
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{
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printf("PDMA SCSI: %d xfers completed for %d bytes.\n",
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pdma_5380_sends, pdma_5380_bytes);
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printf("pdma_5380_dir = %d.\n",
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printf("pdma_5380_dir = %d\t",
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pdma_5380_dir);
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printf("datap = 0x%x, remainder = %d.\n",
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pending_5380_data, pending_5380_count);
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printf("state = %s\n", pdma_5380_state);
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printf("last state = %s\n", pdma_5380_prev_state);
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printf("state: %s\t", pdma_5380_state);
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printf("last state: %s\n", pdma_5380_prev_state);
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scsi_show();
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}
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#endif
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@ -208,7 +209,7 @@ pdma_cleanup(void)
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pdma_5380_dir = 0;
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#if DEBUG
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#if NCR5380_PDMA_DEBUG
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DBG_SET("in pdma_cleanup().")
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pdma_5380_sends++;
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pdma_5380_bytes+=(reqp->xdata_len - pending_5380_count);
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@ -243,11 +244,11 @@ pdma_cleanup(void)
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/*
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* Back for more punishment.
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*/
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#if DEBUG
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#if NCR5380_PDMA_DEBUG
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pdma_5380_state = "pdma_cleanup() -- going back to run_main().";
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#endif
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run_main(cur_softc);
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#if DEBUG
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#if NCR5380_PDMA_DEBUG
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pdma_5380_state = "pdma_cleanup() -- back from run_main().";
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#endif
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}
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@ -262,7 +263,7 @@ pdma_ready()
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extern u_char ncr5380_no_parchk;
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if (pdma_5380_dir) {
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#if DEBUG
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#if NCR5380_PDMA_DEBUG
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DBG_SET("got irq interrupt in xfer.")
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#endif
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/*
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@ -271,6 +272,9 @@ extern u_char ncr5380_no_parchk;
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*/
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dmstat = GET_5380_REG(NCR5380_DMSTAT);
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if (!(dmstat & SC_IRQ_SET)) {
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#if NCR5380_PDMA_DEBUG
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DBG_SET("irq not set.")
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#endif
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return 0;
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}
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/*
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@ -284,12 +288,18 @@ extern u_char ncr5380_no_parchk;
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if ( ((dmstat & (0xff & ~SC_ATN_STAT)) == SC_IRQ_SET)
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&& ((idstat & (SC_S_BSY|SC_S_REQ))
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== (SC_S_BSY | SC_S_REQ)) ) {
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#if NCR5380_PDMA_DEBUG
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DBG_SET("BSY|REQ.")
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#endif
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pdma_cleanup();
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return 1;
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} else if (PH_IN(reqp->phase) && (dmstat & SC_PAR_ERR)) {
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if (!(ncr5380_no_parchk & (1 << reqp->targ_id)))
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/* XXX: Should be parity error ???? */
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reqp->xs->error = XS_DRIVER_STUFFUP;
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#if NCR5380_PDMA_DEBUG
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DBG_SET("PARITY.")
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#endif
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/* XXX: is this the right reaction? */
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pdma_cleanup();
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return 1;
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@ -362,10 +372,24 @@ extern int *nofault, mac68k_buserr_addr;
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* If we're not ready to xfer data, just return.
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*/
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if ( !(GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ)
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|| !pdma_5380_dir)
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|| !pdma_5380_dir) {
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return;
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}
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#if DEBUG
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/*
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* I don't think this should be necessary, but it is
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* for writes--at least to some devices. They don't
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* let go of PH_DATAOUT until we do pdma_cleanup().
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*/
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if (pending_5380_count == 0) {
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#if NCR5380_PDMA_DEBUG
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DBG_SET("forcing pdma_cleanup().")
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#endif
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pdma_cleanup();
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return;
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}
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#if NCR5380_PDMA_DEBUG
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DBG_SET("got drq interrupt.")
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#endif
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@ -378,7 +402,7 @@ extern int *nofault, mac68k_buserr_addr;
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if (setjmp((label_t *) nofault)) {
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nofault = (int *) 0;
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#if DEBUG
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#if NCR5380_PDMA_DEBUG
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DBG_SET("buserr in xfer.")
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#endif
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count = ( (u_long) mac68k_buserr_addr
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@ -394,7 +418,7 @@ extern int *nofault, mac68k_buserr_addr;
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pending_5380_data += count;
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pending_5380_count -= count;
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#if DEBUG
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#if NCR5380_PDMA_DEBUG
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DBG_SET("handled bus error in xfer.")
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#endif
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mac68k_buserr_addr = 0;
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@ -404,11 +428,18 @@ extern int *nofault, mac68k_buserr_addr;
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if (pdma_5380_dir == 2) { /* Data In */
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int resid;
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#if NCR5380_PDMA_DEBUG
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DBG_SET("Data in.")
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#endif
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/*
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* Get the dest address aligned.
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*/
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resid = count = 4 - (((int) pending_5380_data) & 0x3);
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if (count < 4) {
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resid = count = min(pending_5380_count,
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4 - (((int) pending_5380_data) & 0x3));
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if (count && (count < 4)) {
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#if NCR5380_PDMA_DEBUG
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DBG_SET("Data in (aligning dest).")
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#endif
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data = (u_int8_t *) pending_5380_data;
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drq = (u_int8_t *) ncr_5380_with_drq;
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while (count) {
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@ -426,6 +457,9 @@ extern int *nofault, mac68k_buserr_addr;
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while (pending_5380_count) {
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int dcount;
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#if NCR5380_PDMA_DEBUG
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DBG_SET("Data in (starting read).")
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#endif
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dcount = count = min(pending_5380_count, MIN_PHYS);
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long_drq = (volatile u_int32_t *) ncr_5380_with_drq;
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long_data = (u_int32_t *) pending_5380_data;
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@ -437,7 +471,7 @@ extern int *nofault, mac68k_buserr_addr;
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pending_5380_data += (dcount - count);
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pending_5380_count -= (dcount - count);
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#if DEBUG
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#if NCR5380_PDMA_DEBUG
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DBG_SET("drq low")
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#endif
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return;
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@ -464,6 +498,9 @@ extern int *nofault, mac68k_buserr_addr;
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R4; count -= 4;
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}
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#undef R4
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#if NCR5380_PDMA_DEBUG
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DBG_SET("Data in (finishing up).")
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#endif
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data = (u_int8_t *) long_data;
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drq = (u_int8_t *) long_drq;
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while (count) {
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@ -477,11 +514,18 @@ extern int *nofault, mac68k_buserr_addr;
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} else {
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int resid;
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#if NCR5380_PDMA_DEBUG
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DBG_SET("Data out.")
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#endif
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/*
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* Get the source address aligned.
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*/
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resid = count = 4 - (((int) pending_5380_data) & 0x3);
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if (count < 4) {
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resid = count = min(pending_5380_count,
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4 - (((int) pending_5380_data) & 0x3));
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if (count && (count < 4)) {
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#if NCR5380_PDMA_DEBUG
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DBG_SET("Data out (aligning dest).")
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#endif
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data = (u_int8_t *) pending_5380_data;
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drq = (u_int8_t *) ncr_5380_with_drq;
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while (count) {
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@ -499,6 +543,9 @@ extern int *nofault, mac68k_buserr_addr;
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while (pending_5380_count) {
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int dcount;
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#if NCR5380_PDMA_DEBUG
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DBG_SET("Data out (starting write).")
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#endif
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dcount = count = min(pending_5380_count, MIN_PHYS);
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long_drq = (volatile u_int32_t *) ncr_5380_with_drq;
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long_data = (u_int32_t *) pending_5380_data;
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@ -513,6 +560,9 @@ extern int *nofault, mac68k_buserr_addr;
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W4; count -= 4;
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}
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#undef W4
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#if NCR5380_PDMA_DEBUG
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DBG_SET("Data out (cleaning up).")
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#endif
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data = (u_int8_t *) long_data;
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drq = (u_int8_t *) long_drq;
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while (count) {
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@ -531,28 +581,10 @@ extern int *nofault, mac68k_buserr_addr;
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*/
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nofault = (int *) 0;
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#if DEBUG
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DBG_SET("done in xfer--waiting.")
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#endif
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/*
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* Is this necessary?
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*/
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while (!( (GET_5380_REG(NCR5380_DMSTAT) & SC_ACK_STAT)
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|| (GET_5380_REG(NCR5380_IDSTAT) & SC_S_REQ) ));
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/*
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* Update pointers for pdma_cleanup().
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*/
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pending_5380_data += pending_5380_count;
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pending_5380_count = 0;
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#if DEBUG
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#if NCR5380_PDMA_DEBUG
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DBG_SET("done in xfer.")
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#endif
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pdma_cleanup();
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return;
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#endif /* if USE_PDMA */
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}
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@ -574,7 +606,7 @@ transfer_pdma(phasep, data, count)
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panic("ncrscsi: transfer_pdma called when operation already "
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"pending.\n");
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}
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#if DEBUG
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#if NCR5380_PDMA_DEBUG
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DBG_SET("in transfer_pdma.")
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#endif
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@ -582,7 +614,7 @@ transfer_pdma(phasep, data, count)
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* Don't bother with PDMA if we can't sleep or for small transfers.
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*/
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if (reqp->dr_flag & DRIVER_NOINT) {
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#if DEBUG
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#if NCR5380_PDMA_DEBUG
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DBG_SET("pdma, actually using transfer_pio.")
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#endif
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transfer_pio(phasep, data, count, 0);
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@ -625,20 +657,14 @@ transfer_pdma(phasep, data, count)
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*/
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reqp->dr_flag |= DRIVER_IN_DMA;
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/*
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* Set DMA mode and assert data bus.
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*/
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SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) | SC_M_DMA);
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SET_5380_REG(NCR5380_ICOM, GET_5380_REG(NCR5380_ICOM) | SC_ADTB);
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/*
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* Load transfer values for DRQ interrupt handlers.
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*/
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pending_5380_data = data;
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pending_5380_count = len;
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#if DEBUG
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DBG_SET("wait for interrupt.")
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#if NCR5380_PDMA_DEBUG
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DBG_SET("setting up for interrupt.")
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#endif
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/*
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@ -650,14 +676,22 @@ transfer_pdma(phasep, data, count)
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panic("Unexpected phase in transfer_pdma.\n");
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case PH_DATAOUT:
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pdma_5380_dir = 1;
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SET_5380_REG(NCR5380_ICOM, GET_5380_REG(NCR5380_ICOM)|SC_ADTB);
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SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE)|SC_M_DMA);
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SET_5380_REG(NCR5380_DMSTAT, 0);
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break;
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case PH_DATAIN:
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pdma_5380_dir = 2;
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SET_5380_REG(NCR5380_ICOM, 0);
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SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE)|SC_M_DMA);
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SET_5380_REG(NCR5380_IRCV, 0);
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break;
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}
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#if NCR5380_PDMA_DEBUG
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DBG_SET("wait for interrupt.")
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#endif
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/*
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* Now that we're set up, enable interrupts and drop processor
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* priority back down.
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@ -1,4 +1,4 @@
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/* $NetBSD: ncr5380.c,v 1.17 1996/01/06 15:56:12 briggs Exp $ */
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/* $NetBSD: ncr5380.c,v 1.18 1996/01/24 06:02:11 briggs Exp $ */
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/*
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* Copyright (c) 1995 Leo Weppelman.
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