- Adapt to the MI wdc driver changes which added the notion of
"shadow registers": http://mail-index.netbsd.org/source-changes/2004/05/25/0048.html - While here, also fix accesses to CTL regsters to use the correct address. Now the cobalt bootloader works again. XXX Maybe we should make this SA wdc driver MI...
This commit is contained in:
tsutsui
parent
175e99933e
commit
221c318874
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@ -1,4 +1,4 @@
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/* $NetBSD: pciide.c,v 1.3 2004/01/03 01:50:53 thorpej Exp $ */
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/* $NetBSD: pciide.c,v 1.4 2004/09/01 15:54:39 tsutsui Exp $ */
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/*-
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* Copyright (c) 2003 The NetBSD Foundation, Inc.
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@ -40,13 +40,15 @@
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#include "boot.h"
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#include "wdvar.h"
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#define COBALT_IO_SPACE_BASE 0x10000000 /* XXX VT82C586 ISA I/O space */
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int
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pciide_init(chp, unit)
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struct wdc_channel *chp;
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u_int *unit;
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{
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u_long bpa, addr;
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int compatchan = 0;
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u_int32_t cmdreg, ctlreg;
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int i, compatchan = 0;
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/*
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* two channels per chip, two drives per channel
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@ -61,12 +63,21 @@ pciide_init(chp, unit)
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/*
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* XXX map?
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*/
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bpa = PCIIDE_COMPAT_CMD_BASE(compatchan);
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addr = MIPS_PHYS_TO_KSEG1(bpa);
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if (bpa < 0x10000000)
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addr += 0x10000000;
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cmdreg = MIPS_PHYS_TO_KSEG1(COBALT_IO_SPACE_BASE +
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PCIIDE_COMPAT_CMD_BASE(compatchan));
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ctlreg = MIPS_PHYS_TO_KSEG1(COBALT_IO_SPACE_BASE +
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PCIIDE_COMPAT_CTL_BASE(compatchan));
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/* set up cmd regsiters */
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chp->c_cmdbase = (u_int8_t *)cmdreg;
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chp->c_data = (u_int16_t *)(cmdreg + wd_data);
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for (i = 0; i < WDC_NPORTS; i++)
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chp->c_cmdreg[i] = chp->c_cmdbase + i;
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/* set up shadow registers */
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chp->c_cmdreg[wd_status] = chp->c_cmdreg[wd_command];
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chp->c_cmdreg[wd_features] = chp->c_cmdreg[wd_precomp];
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/* set up ctl registers */
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chp->c_ctlbase = (u_int8_t *)ctlreg;
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chp->c_base = (u_int8_t*)addr;
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chp->c_data = (u_int16_t*)(addr + wd_data);
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return (0);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: wdc.c,v 1.5 2004/01/03 01:50:53 thorpej Exp $ */
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/* $NetBSD: wdc.c,v 1.6 2004/09/01 15:54:39 tsutsui Exp $ */
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/*-
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* Copyright (c) 2003 The NetBSD Foundation, Inc.
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@ -67,12 +67,12 @@ __wdcwait_reset(chp, drv_mask)
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/* wait for BSY to deassert */
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for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) {
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chp->c_base[wd_sdh] = WDSD_IBM; /* master */
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WDC_WRITE_REG(chp, wd_sdh, WDSD_IBM); /* master */
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delay(10);
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st0 = chp->c_base[wd_status];
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chp->c_base[wd_sdh] = WDSD_IBM | 0x10; /* slave */
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st0 = WDC_READ_REG(chp, wd_status);
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WDC_WRITE_REG(chp, wd_sdh, WDSD_IBM | 0x10); /* slave */
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delay(10);
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st1 = chp->c_base[wd_status];
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st1 = WDC_READ_REG(chp, wd_status);
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if ((drv_mask & 0x01) == 0) {
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/* no master */
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@ -129,12 +129,12 @@ wdcprobe(chp)
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/*
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* Sanity check to see if the wdc channel responds at all.
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*/
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chp->c_base[wd_sdh] = WDSD_IBM;
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WDC_WRITE_REG(chp, wd_sdh, WDSD_IBM);
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delay(10);
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st0 = chp->c_base[wd_status];
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chp->c_base[wd_sdh] = WDSD_IBM | 0x10;
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st0 = WDC_READ_REG(chp, wd_status);
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WDC_WRITE_REG(chp, wd_sdh, WDSD_IBM | 0x10);
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delay(10);
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st1 = chp->c_base[wd_status];
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st1 = WDC_READ_REG(chp, wd_status);
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if (st0 == 0xff || st0 == WDSD_IBM)
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ret_value &= ~0x01;
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@ -144,14 +144,14 @@ wdcprobe(chp)
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return (ENXIO);
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/* assert SRST, wait for reset to complete */
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chp->c_base[wd_sdh] = WDSD_IBM;
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WDC_WRITE_REG(chp, wd_sdh, WDSD_IBM);
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delay(10);
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chp->c_base[wd_aux_ctlr] = WDCTL_RST | WDCTL_IDS;
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WDC_WRITE_CTLREG(chp, wd_aux_ctlr, WDCTL_RST | WDCTL_IDS);
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delay(1000);
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chp->c_base[wd_aux_ctlr] = WDCTL_IDS;
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WDC_WRITE_CTLREG(chp, wd_aux_ctlr, WDCTL_IDS);
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delay(1000);
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(void) chp->c_base[wd_error];
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chp->c_base[wd_aux_ctlr] = WDCTL_4BIT;
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(void) WDC_READ_REG(chp, wd_error);
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WDC_WRITE_CTLREG(chp, wd_aux_ctlr, WDCTL_4BIT);
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delay(10);
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ret_value = __wdcwait_reset(chp, ret_value);
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@ -199,7 +199,7 @@ wdc_wait_for_ready(chp)
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{
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u_int timeout;
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for (timeout = WDC_TIMEOUT; timeout > 0; --timeout) {
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if ((chp->c_base[wd_status] & (WDCS_BSY | WDCS_DRDY))
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if ((WDC_READ_REG(chp, wd_status) & (WDCS_BSY | WDCS_DRDY))
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== WDCS_DRDY)
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return (0);
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}
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@ -222,7 +222,7 @@ wdc_read_block(sc, wd_c)
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return (0);
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for (i = wd_c->bcount; i > 0; i -= sizeof(u_int16_t))
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*ptr++ = *chp->c_data;
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*ptr++ = WDC_READ_DATA(chp);
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return (0);
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}
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@ -245,20 +245,21 @@ wdccommand(sc, wd_c)
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wd_c->r_precomp));
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#endif
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chp->c_base[wd_precomp] = wd_c->r_precomp;
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chp->c_base[wd_seccnt] = wd_c->r_count;
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chp->c_base[wd_sector] = wd_c->r_sector;
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chp->c_base[wd_cyl_lo] = wd_c->r_cyl;
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chp->c_base[wd_cyl_hi] = wd_c->r_cyl >> 8;
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chp->c_base[wd_sdh] = WDSD_IBM | (wd_c->drive << 4) | wd_c->r_head;
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chp->c_base[wd_command] = wd_c->r_command;
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WDC_WRITE_REG(chp, wd_precomp, wd_c->r_precomp);
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WDC_WRITE_REG(chp, wd_seccnt, wd_c->r_count);
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WDC_WRITE_REG(chp, wd_sector, wd_c->r_sector);
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WDC_WRITE_REG(chp, wd_cyl_lo, wd_c->r_cyl);
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WDC_WRITE_REG(chp, wd_cyl_hi, wd_c->r_cyl >> 8);
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WDC_WRITE_REG(chp, wd_sdh,
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WDSD_IBM | (wd_c->drive << 4) | wd_c->r_head);
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WDC_WRITE_REG(chp, wd_command, wd_c->r_command);
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if (wdc_wait_for_ready(chp) != 0)
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return (ENXIO);
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if (chp->c_base[wd_status] & WDCS_ERR) {
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if (WDC_READ_REG(chp, wd_status) & WDCS_ERR) {
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printf("wd%d: error %x\n", chp->compatchan,
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chp->c_base[wd_error]);
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WDC_READ_REG(chp, wd_error));
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return (ENXIO);
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}
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@ -277,31 +278,31 @@ wdccommandext(wd, wd_c)
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struct wdc_channel *chp = &wd->sc_channel;
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/* Select drive, head, and addressing mode. */
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chp->c_base[wd_sdh] = (wd_c->drive << 4) | WDSD_LBA;
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WDC_WRITE_REG(chp, wd_sdh, (wd_c->drive << 4) | WDSD_LBA);
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/* previous */
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chp->c_base[wd_features] = 0;
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chp->c_base[wd_seccnt] = wd_c->r_count >> 8;
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chp->c_base[wd_lba_hi] = wd_c->r_blkno >> 40;
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chp->c_base[wd_lba_mi] = wd_c->r_blkno >> 32;
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chp->c_base[wd_lba_lo] = wd_c->r_blkno >> 24;
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WDC_WRITE_REG(chp, wd_features, 0);
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WDC_WRITE_REG(chp, wd_seccnt, wd_c->r_count >> 8);
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WDC_WRITE_REG(chp, wd_lba_hi, wd_c->r_blkno >> 40);
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WDC_WRITE_REG(chp, wd_lba_mi, wd_c->r_blkno >> 32);
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WDC_WRITE_REG(chp, wd_lba_lo, wd_c->r_blkno >> 24);
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/* current */
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chp->c_base[wd_features] = 0;
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chp->c_base[wd_seccnt] = wd_c->r_count;
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chp->c_base[wd_lba_hi] = wd_c->r_blkno >> 16;
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chp->c_base[wd_lba_mi] = wd_c->r_blkno >> 8;
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chp->c_base[wd_lba_lo] = wd_c->r_blkno;
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WDC_WRITE_REG(chp, wd_features, 0);
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WDC_WRITE_REG(chp, wd_seccnt, wd_c->r_count);
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WDC_WRITE_REG(chp, wd_lba_hi, wd_c->r_blkno >> 16);
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WDC_WRITE_REG(chp, wd_lba_mi, wd_c->r_blkno >> 8);
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WDC_WRITE_REG(chp, wd_lba_lo, wd_c->r_blkno);
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/* Send command. */
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chp->c_base[wd_command] = wd_c->r_command;
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WDC_WRITE_REG(chp, wd_command, wd_c->r_command);
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if (wdc_wait_for_ready(chp) != 0)
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return (ENXIO);
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if (chp->c_base[wd_status] & WDCS_ERR) {
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if (WDC_READ_REG(chp, wd_status) & WDCS_ERR) {
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printf("wd%d: error %x\n", chp->compatchan,
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chp->c_base[wd_error]);
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WDC_READ_REG(chp, wd_error));
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return (ENXIO);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: wdvar.h,v 1.4 2004/01/03 01:50:53 thorpej Exp $ */
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/* $NetBSD: wdvar.h,v 1.5 2004/09/01 15:54:39 tsutsui Exp $ */
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/*-
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* Copyright (c) 2003 The NetBSD Foundation, Inc.
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@ -45,14 +45,24 @@
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#define WDC_TIMEOUT 2000000
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#define PCIIDE_CHANNEL_NDEV 2
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#define NUNITS (PCIIDE_CHANNEL_NDEV * PCIIDE_NUM_CHANNELS)
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#define WDC_NPORTS 8 /* XXX */
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#define WDC_NSHADOWREG 2 /* XXX */
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struct wdc_channel {
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volatile u_int8_t *c_base;
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volatile u_int8_t *c_cmdbase;
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volatile u_int8_t *c_ctlbase;
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volatile u_int8_t *c_cmdreg[WDC_NPORTS + WDC_NSHADOWREG];
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volatile u_int16_t *c_data;
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u_int8_t compatchan;
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};
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#define WDC_READ_REG(chp, reg) *(chp)->c_cmdreg[(reg)]
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#define WDC_WRITE_REG(chp, reg, val) *(chp)->c_cmdreg[(reg)] = (val)
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#define WDC_READ_CTLREG(chp, reg) (chp)->c_ctlbase[(reg)]
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#define WDC_WRITE_CTLREG(chp, reg, val) (chp)->c_ctlbase[(reg)] = (val)
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#define WDC_READ_DATA(chp) *(chp)->c_data
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struct wd_softc {
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#define WDF_LBA 0x0001
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#define WDF_LBA48 0x0002
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