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On Milan, also explicitly disable MBIRQ1 on PIIX. 

Milan's ROM bootloader v1.2 and v1.4 incorrectly set MBIRQ0 connected
to the secondary IDE to IRQ14 (not 15) and unused MBIRQ1 to IRQ15,
so both IDE channels don't work properly.
This commit is contained in:
tsutsui 2018-02-09 15:24:35 +00:00
parent 9e6ef971c3
commit 21d771a72b
1 changed files with 10 additions and 5 deletions
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15
sys/arch/atari/pci/pci_machdep.c
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@ -1,4 +1,4 @@
/* $NetBSD: pci_machdep.c,v 1.55 2018/01/31 15:36:29 tsutsui Exp $ */
/* $NetBSD: pci_machdep.c,v 1.56 2018/02/09 15:24:35 tsutsui Exp $ */
/*
* Copyright (c) 1996 Leo Weppelman. All rights reserved.
@ -32,7 +32,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.55 2018/01/31 15:36:29 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.56 2018/02/09 15:24:35 tsutsui Exp $");
#include "opt_mbtype.h"
@ -454,10 +454,15 @@ enable_pci_devices(void)
#define PIIX_PCIB_MBIRQ0 0x70
if ((PCI_VENDOR(id) == PCI_VENDOR_INTEL) &&
(PCI_PRODUCT(id) == PCI_PRODUCT_INTEL_82371FB_ISA)) {
/* Set Interrupt Routing for MBIRQ0 to IRQ15 */
/*
* Set Interrupt Routing for MBIRQ0 to IRQ15.
* Note Milan's ROM bootloader v1.2 and v1.4 incorrectly
* set MBIRQ0 to IRQ14 (not 15) and unused MBIRQ1 to IRQ 15,
* so explicitly disable MBIRQ1.
*/
csr = pci_conf_read(pc, tag, PIIX_PCIB_MBIRQ0);
csr &= ~0x00000ff;
csr |= 0x000000f; /* IRQ15 */
csr &= ~0x000ffff;
csr |= 0x000800f; /* MBIRQ1: disable, MBIRQ0: IRQ15 */
pci_conf_write(pc, tag, PIIX_PCIB_MBIRQ0, csr);
#ifdef DEBUG_PCI_MACHDEP
printf("\npcib0: enable and route MBIRQ0 to irq 15\n");