Import from i386 because it contains a nice explanation of our MMU.
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matthias
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c70676bb18
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@ -1,11 +1,9 @@
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/* $NetBSD: pte.h,v 1.2 1996/02/01 22:32:02 mycroft Exp $ */
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/* $NetBSD: pte.h,v 1.3 1998/03/18 21:52:02 matthias Exp $ */
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/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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/*
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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* Copyright (c) 1997 Charles D. Cranor and Washington University.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -16,55 +14,143 @@
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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* must display the following acknowledgment:
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* This product includes software developed by Charles D. Cranor and
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* Washington University.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)pte.h 5.5 (Berkeley) 5/9/91
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* NS532 page table entry and page table directory
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* (derived from 386 page table entry by W.Jolitz, 8/89)
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* pte.h rewritten by chuck based on the jolitz version, plus random
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* info on the pentium and other processors found on the net. The
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* goal of this rewrite is to provide enough documentation on the MMU
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* hardware that the reader will be able to understand it without having
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* to refer to a hardware manual.
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*
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* There are two major kinds of pte's: those which have ever existed (and are
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* thus either now in core or on the swap device), and those which have
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* never existed, but which will be filled on demand at first reference.
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* There is a structure describing each. There is also an ancillary
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* structure used in page clustering.
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* Modified for the ns32532 by Matthias Pfaller.
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*/
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#ifndef _NS532_PTE_H_
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#define _NS532_PTE_H_
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#define PDSHIFT 22 /* LOG2(NBPDR) */
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#define NBPD (1 << PDSHIFT) /* bytes/page dir */
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#define PDOFSET (NBPD-1) /* byte offset into page dir */
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#define NPTEPD (NBPD / NBPG)
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/*
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* ns32532 MMU hardware structure:
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*
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* The ns32532 MMU is a two-level MMU which maps 4GB of virtual memory.
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* The pagesize is 4K (4096 [0x1000] bytes).
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*
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* The first level table is called a "page directory" and it contains
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* 1024 page directory entries (PDEs). Each PDE is 4 bytes (an int),
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* so a PD fits in a single 4K page. This page is the page directory
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* page (PDP). Each PDE in a PDP maps 4MB of space (1024 * 4MB = 4GB).
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* A PDE contains the physical address of the second level
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* table: The page table.
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*
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* A page table consists of 1024 page table entries (PTEs). Each PTE is
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* 4 bytes (an int), so a page table also fits in a single 4K page. A 4K
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* page being used as a page table is called a page table page (PTP).
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* Each PTE in a PTP maps one 4K page (1024 * 4K = 4MB). A PTE contains
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* the physical address of the page it maps and some flag bits (described
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* below).
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*
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* The processor has a special register, "ptb0", which points to the
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* the PDP which is currently controlling the mappings of the virtual
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* address space.
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*
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* The following picture shows the translation process for a 4K page:
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*
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* ptb0 register [PA of PDP]
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* |
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* |
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* | bits <31-22> of VA bits <21-12> of VA bits <11-0>
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* | index the PDP (0 - 1023) index the PTP are the page offset
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* | | | |
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* | v | |
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* +--->+----------+ | |
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* | PD Page | PA of v |
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* | |---PTP-------->+------------+ |
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* | 1024 PDE | | page table |--PTE--+ |
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* | entries | | (aka PTP) | | |
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* +----------+ | 1024 PTE | | |
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* | entries | | |
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* +------------+ | |
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* | |
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* bits <31-12> bits <11-0>
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* p h y s i c a l a d d r
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*
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* The ns32532 caches PTEs in a TLB. It is important to flush out old
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* TLB mappings when making a change to a mappings. Writing to the
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* ptb0 register will flush the entire TLB. The ns32532 also has an
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* instruction that will invalidate the mapping of a single page (which
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* is useful if you are changing a single page's mappings because it
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* preserves all the cached TLB entries).
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*
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* As shows, bits 31-12 of the PTE contain PA of the page being mapped.
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* the rest of the PTE is defined as follows:
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* bit# name use
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* 11 n/a available for OS use, hardware ignores it
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* 10 n/a available for OS use, hardware ignores it
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* 9 n/a available for OS use, hardware ignores it
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* 8 M modified page
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* 7 R referenced page
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* 6 CI cache inhibited page
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* 5 n/a reserved
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* 4 n/a reserved
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* 3 n/a reserved
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* 2 U/S user/supervisor bit (0=supervisor only, 1=both u&s)
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* 1 R/W read/write bit (0=read only, 1=read-write)
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* 0 V valid page
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*
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* notes:
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* - Useraccessible pages (U/S == 1) are *always* writable in kernel mode.
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* copyout and friends use the ns32532's dual address space instructions
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* for this reason.
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*/
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#if !defined(_LOCORE)
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/*
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* here we define the data types for PDEs and PTEs
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*/
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typedef u_int32_t pd_entry_t; /* PDE */
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typedef u_int32_t pt_entry_t; /* PTE */
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#ifndef _LOCORE
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typedef int pd_entry_t; /* page directory entry */
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typedef int pt_entry_t; /* Mach page table entry */
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#endif
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/*
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* now we define various for playing with virtual addresses
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*/
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#define PDSHIFT 22 /* offset of PD index in VA */
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#define NBPD (1 << PDSHIFT) /* # bytes mapped by PD (4MB) */
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#define PDOFSET (NBPD-1) /* mask for non-PD part of VA */
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#if 0 /* not used? */
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#define NPTEPD (NBPD / NBPG) /* # of PTEs in a PD */
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#else
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#define PTES_PER_PTP (NBPD / NBPG) /* # of PTEs in a PTP */
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#endif
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#define PD_MASK 0xffc00000 /* page directory address bits */
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#define PT_MASK 0x003ff000 /* page table address bits */
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/*
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* here we define the bits of the PDE/PTE, as described above:
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*
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* XXXCDC: need to rename these (PG_u == ugly).
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*/
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#define PG_V 0x00000001 /* present */
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#define PG_RO 0x00000000 /* read-only by user and kernel */
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#define PG_RW 0x00000002 /* read-write by user */
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@ -73,25 +159,16 @@ typedef int pt_entry_t; /* Mach page table entry */
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#define PG_N 0x00000040 /* non-cacheable */
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#define PG_U 0x00000080 /* has been used */
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#define PG_M 0x00000100 /* has been modified */
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#define PG_W 0x00000200 /* page is wired */
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#define PG_AVAIL1 0x00000200 /* ignored by hardware */
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#define PG_AVAIL2 0x00000400 /* ignored by hardware */
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#define PG_AVAIL3 0x00000800 /* ignored by hardware */
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#define PG_FRAME 0xfffff000 /* page frame mask */
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#define PG_FZERO 0
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#define PG_FTEXT 1
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#define PG_FMAX (PG_FTEXT)
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/*
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* various short-hand protection codes
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*/
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#define PG_NOACC 0
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#define PG_KR 0x00000000
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#define PG_KW 0x00000002
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#define PG_URKR 0x00000004
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#define PG_URKW 0x00000004
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#define PG_UW 0x00000006
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#ifndef _LOCORE
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#ifdef _KERNEL
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/* utilities defined in pmap.c */
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extern pt_entry_t *Sysmap;
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#endif
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#endif
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#define PG_KR 0x00000000 /* kernel read-only */
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#define PG_KW 0x00000002 /* kernel read-write */
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#endif /* _NS532_PTE_H_ */
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