Define all members in TX/RX DMA descriptors as u_int32_t and use proper shift
and mask ops since smc83c170 chips access them in 32bit width with proper byteswap mechanism, so that all #if BYTE_ORDER in descriptors can be removed. While here, do some slight optimizations in epic_start() and epic_intr().
This commit is contained in:
tsutsui
parent
addcf5d254
commit
1fafd3e354
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@ -1,4 +1,4 @@
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/* $NetBSD: smc83c170.c,v 1.54 2003/11/02 11:07:46 wiz Exp $ */
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/* $NetBSD: smc83c170.c,v 1.55 2003/11/08 16:08:13 tsutsui Exp $ */
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/*-
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* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
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@ -43,7 +43,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.54 2003/11/02 11:07:46 wiz Exp $");
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__KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.55 2003/11/08 16:08:13 tsutsui Exp $");
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#include "bpfilter.h"
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@ -371,6 +371,7 @@ epic_start(ifp)
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struct epic_fraglist *fr;
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bus_dmamap_t dmamap;
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int error, firsttx, nexttx, opending, seg;
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u_int len;
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/*
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* Remember the previous txpending and the first transmit
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@ -453,10 +454,11 @@ epic_start(ifp)
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fr->ef_frags[seg].ef_length =
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dmamap->dm_segs[seg].ds_len;
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}
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if (m0->m_pkthdr.len < ETHER_PAD_LEN) {
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len = m0->m_pkthdr.len;
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if (len < ETHER_PAD_LEN) {
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fr->ef_frags[seg].ef_addr = sc->sc_nulldma;
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fr->ef_frags[seg].ef_length =
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ETHER_PAD_LEN - m0->m_pkthdr.len;
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fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len;
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len = ETHER_PAD_LEN;
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seg++;
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}
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fr->ef_nfrags = seg;
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@ -476,7 +478,6 @@ epic_start(ifp)
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* Fill in the transmit descriptor.
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*/
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txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST;
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txd->et_txlength = max(m0->m_pkthdr.len, ETHER_PAD_LEN);
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/*
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* If this is the first descriptor we're enqueueing,
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@ -484,9 +485,10 @@ epic_start(ifp)
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* a race condition. We'll do it below.
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*/
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if (nexttx == firsttx)
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txd->et_txstatus = 0;
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txd->et_txstatus = TXSTAT_TXLENGTH(len);
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else
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txd->et_txstatus = ET_TXSTAT_OWNER;
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txd->et_txstatus =
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TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER;
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EPIC_CDTXSYNC(sc, nexttx,
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BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
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@ -529,7 +531,7 @@ epic_start(ifp)
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* The entire packet chain is set up. Give the
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* first descriptor to the EPIC now.
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*/
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EPIC_CDTX(sc, firsttx)->et_txstatus = ET_TXSTAT_OWNER;
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EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER;
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EPIC_CDTXSYNC(sc, firsttx,
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BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
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@ -612,7 +614,7 @@ epic_intr(arg)
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struct epic_txdesc *txd;
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struct epic_descsoft *ds;
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struct mbuf *m;
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u_int32_t intstat;
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u_int32_t intstat, rxstatus, txstatus;
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int i, claimed = 0;
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u_int len;
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@ -643,7 +645,8 @@ epic_intr(arg)
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EPIC_CDRXSYNC(sc, i,
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BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
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if (rxd->er_rxstatus & ER_RXSTAT_OWNER) {
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rxstatus = rxd->er_rxstatus;
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if (rxstatus & ER_RXSTAT_OWNER) {
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/*
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* We have processed all of the
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* receive buffers.
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@ -657,11 +660,11 @@ epic_intr(arg)
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* The buffer will be reused the next time the
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* descriptor comes up in the ring.
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*/
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if ((rxd->er_rxstatus & ER_RXSTAT_PKTINTACT) == 0) {
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if (rxd->er_rxstatus & ER_RXSTAT_CRCERROR)
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if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) {
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if (rxstatus & ER_RXSTAT_CRCERROR)
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printf("%s: CRC error\n",
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sc->sc_dev.dv_xname);
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if (rxd->er_rxstatus & ER_RXSTAT_ALIGNERROR)
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if (rxstatus & ER_RXSTAT_ALIGNERROR)
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printf("%s: alignment error\n",
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sc->sc_dev.dv_xname);
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ifp->if_ierrors++;
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@ -675,7 +678,7 @@ epic_intr(arg)
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/*
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* The EPIC includes the CRC with every packet.
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*/
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len = rxd->er_rxlength;
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len = RXSTAT_RXLENGTH(rxstatus);
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if (len < sizeof(struct ether_header)) {
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/*
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@ -775,7 +778,8 @@ epic_intr(arg)
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EPIC_CDTXSYNC(sc, i,
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BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
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if (txd->et_txstatus & ET_TXSTAT_OWNER)
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txstatus = txd->et_txstatus;
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if (txstatus & ET_TXSTAT_OWNER)
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break;
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EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE);
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@ -790,13 +794,13 @@ epic_intr(arg)
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/*
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* Check for errors and collisions.
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*/
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if ((txd->et_txstatus & ET_TXSTAT_PACKETTX) == 0)
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if ((txstatus & ET_TXSTAT_PACKETTX) == 0)
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ifp->if_oerrors++;
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else
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ifp->if_opackets++;
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ifp->if_collisions +=
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TXSTAT_COLLISIONS(txd->et_txstatus);
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if (txd->et_txstatus & ET_TXSTAT_CARSENSELOST)
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TXSTAT_COLLISIONS(txstatus);
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if (txstatus & ET_TXSTAT_CARSENSELOST)
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printf("%s: lost carrier\n",
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sc->sc_dev.dv_xname);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: smc83c170reg.h,v 1.8 2003/11/02 11:07:46 wiz Exp $ */
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/* $NetBSD: smc83c170reg.h,v 1.9 2003/11/08 16:08:13 tsutsui Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -49,25 +49,16 @@
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* EPIC transmit descriptor. Must be 4-byte aligned.
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*/
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struct epic_txdesc {
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#if BYTE_ORDER == BIG_ENDIAN
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u_int16_t et_txlength; /* transmit length */
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u_int16_t et_txstatus; /* transmit status; see below */
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#else
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u_int16_t et_txstatus; /* transmit status; see below */
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u_int16_t et_txlength; /* transmit length */
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#endif
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u_int32_t et_txstatus; /* transmit status; see below */
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u_int32_t et_bufaddr; /* buffer address */
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#if BYTE_ORDER == BIG_ENDIAN
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u_int16_t et_control; /* control word; see below */
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u_int16_t et_buflength; /* buffer length */
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#else
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u_int16_t et_buflength; /* buffer length */
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u_int16_t et_control; /* control word; see below */
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#endif
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u_int32_t et_control; /* control word; see below */
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u_int32_t et_nextdesc; /* next descriptor pointer */
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};
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/* et_txstatus */
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#define TXSTAT_TXLENGTH_SHIFT 16 /* TX length in higher 16bits */
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#define TXSTAT_TXLENGTH(x) ((x) << TXSTAT_TXLENGTH_SHIFT)
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#define ET_TXSTAT_OWNER 0x8000 /* NIC owns descriptor */
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#define ET_TXSTAT_COLLMASK 0x1f00 /* collisions */
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#define ET_TXSTAT_DEFERRING 0x0080 /* deferring due to jabber */
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@ -82,35 +73,29 @@ struct epic_txdesc {
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#define TXSTAT_COLLISIONS(x) (((x) & ET_TXSTAT_COLLMASK) >> 8)
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/* et_control */
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#define ET_TXCTL_LASTDESC 0x0010 /* last descriptor in frame */
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#define ET_TXCTL_NOCRC 0x0008 /* disable CRC generation */
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#define ET_TXCTL_IAF 0x0004 /* interrupt after frame */
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#define ET_TXCTL_LFFORM 0x0002 /* alternate fraglist format */
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#define ET_TXCTL_FRAGLIST 0x0001 /* descriptor points to fraglist */
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#define TXCTL_BUFLENGTH_MASK 0x0000ffff /* buf length in lower 16bits */
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#define TXCTL_BUFLENGTH(x) ((x) & TXCTL_BUFLENGTH_MASK)
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#define ET_TXCTL_LASTDESC 0x00100000 /* last descriptor in frame */
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#define ET_TXCTL_NOCRC 0x00080000 /* disable CRC generation */
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#define ET_TXCTL_IAF 0x00040000 /* interrupt after frame */
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#define ET_TXCTL_LFFORM 0x00020000 /* alternate fraglist format */
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#define ET_TXCTL_FRAGLIST 0x00010000 /* descriptor points to fraglist */
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/*
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* EPIC receive descriptor. Must be 4-byte aligned.
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*/
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struct epic_rxdesc {
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#if BYTE_ORDER == BIG_ENDIAN
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u_int16_t er_rxlength; /* receive frame length */
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u_int16_t er_rxstatus; /* receive status; see below */
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#else
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u_int16_t er_rxstatus; /* receive status; see below */
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u_int16_t er_rxlength; /* receive frame length */
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#endif
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u_int32_t er_rxstatus; /* receive status; see below */
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u_int32_t er_bufaddr; /* buffer address */
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#if BYTE_ORDER == BIG_ENDIAN
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u_int16_t er_control; /* control word; see below */
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u_int16_t er_buflength; /* buffer length */
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#else
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u_int16_t er_buflength; /* buffer length */
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u_int16_t er_control; /* control word; see below */
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#endif
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u_int32_t er_control; /* control word; see below */
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u_int32_t er_nextdesc; /* next descriptor pointer */
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};
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/* er_rxstatus */
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#define RXSTAT_RXLENGTH_SHIFT 16 /* TX length in higher 16bits */
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#define RXSTAT_RXLENGTH(x) ((x) >> RXSTAT_RXLENGTH_SHIFT)
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#define ER_RXSTAT_OWNER 0x8000 /* NIC owns descriptor */
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#define ER_RXSTAT_HDRCOPIED 0x4000 /* rx status posted after hdr copy */
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#define ER_RXSTAT_FRAGLISTERR 0x2000 /* ran out of frags to copy frame */
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@ -124,9 +109,12 @@ struct epic_rxdesc {
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#define ER_RXSTAT_PKTINTACT 0x0001 /* packet received without error */
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/* er_control */
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#define ER_RXCTL_HEADER 0x0004 /* descriptor is for hdr copy */
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#define ER_RXCTL_LFFORM 0x0002 /* alternate fraglist format */
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#define ER_RXCTL_FRAGLIST 0x0001 /* descriptor points to fraglist */
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#define RXCTL_BUFLENGTH_MASK 0x0000ffff /* buf length in lower 16bits */
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#define RXCTL_BUFLENGTH(x) ((x) & RXCTL_BUFLENGTH_MASK)
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#define ER_RXCTL_HEADER 0x00040000 /* descriptor is for hdr copy */
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#define ER_RXCTL_LFFORM 0x00020000 /* alternate fraglist format */
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#define ER_RXCTL_FRAGLIST 0x00010000 /* descriptor points to fraglist */
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/*
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* This is not really part of the register description, but we need
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@ -1,4 +1,4 @@
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/* $NetBSD: smc83c170var.h,v 1.7 2003/01/13 17:00:18 bouyer Exp $ */
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/* $NetBSD: smc83c170var.h,v 1.8 2003/11/08 16:08:13 tsutsui Exp $ */
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/*-
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* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
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@ -176,12 +176,11 @@ do { \
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*/ \
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__m->m_data = __m->m_ext.ext_buf + 2; \
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__rxd->er_bufaddr = __ds->ds_dmamap->dm_segs[0].ds_addr + 2; \
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__rxd->er_buflength = __m->m_ext.ext_size - 2; \
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__rxd->er_control = 0; \
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__rxd->er_control = RXCTL_BUFLENGTH(__m->m_ext.ext_size - 2); \
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__rxd->er_rxstatus = ER_RXSTAT_OWNER; \
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__rxd->er_nextdesc = EPIC_CDRXADDR((sc), EPIC_NEXTRX((x))); \
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EPIC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
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} while (0)
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} while (/* CONSTCOND */ 0)
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#ifdef _KERNEL
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void epic_attach __P((struct epic_softc *));
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