Make PCI interrupts -> GPP mapping configured via config file.
Add bus_spaces for all possile obios. Add gt_halt to make sure the discovery is not doing dma as soon as possible. Read the SDRAM register to figure out how much physical RAM is available.
This commit is contained in:
matt
parent
bd800e6684
commit
1ebbd9b463
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@ -1,4 +1,4 @@
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# $NetBSD: EV64260,v 1.3 2003/03/17 23:23:47 matt Exp $
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# $NetBSD: EV64260,v 1.4 2003/03/24 17:07:15 matt Exp $
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#
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# MVP -- Motorola's Multiprocessing Verification Platform
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#
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@ -13,14 +13,23 @@ maxusers 32
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#options UVMHIST
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#options UVMHIST_PRINT
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# Discovery options
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# PowerPC options
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options ALTIVEC
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#options CLOCKBASE=100000000 # EVB64260
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options CLOCKBASE=133000000 # EVB64260A
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# Marvell options
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options GT_MPP_INTERRUPTS=0x2c600000
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options GT_MPP_WATCHDOG=0x03000000
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#options MPSC_CONSOLE
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#options MPSC_CONSOLE=0
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options GT_MPSC_DEFAULT_BAUD_RATE=9600
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options GT_BASE=0xF8000000
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options CLOCKBASE=100000000
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#options GT_BASE=0x14000000 # PMON low
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options GT_BASE=0xF8000000 # PPCBoot
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options GT_MPSC_FREQUENCY="(cpu_timebase*4)"
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options GT_MPSC_CLOCK_SOURCE="BRG_BCR_CLKS_TCLK"
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options PCI0_GPPINTS=0xffffff1b,PCI1_GPPINTS=0xffffff1d
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options PCI0_SKIPMASK="(~0xc0)",PCI1_SKIPMASK="(~0xc0)"
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options OBIO0_STRIDE=0,OBIO1_STRIDE=2,OBIO2_STRIDE=2,OBIO3_STRIDE=2
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# Options for necessary to use MD
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#options MEMORY_DISK_HOOKS
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@ -121,7 +130,7 @@ options PCIVERBOSE # verbose PCI device autoconfig messages
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options MIIVERBOSE # verbose PHY autoconfig messages
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#options PCI_CONFIG_DUMP # verbosely dump PCI config space
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#options SCSIVERBOSE # human readable SCSI error messages
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#options PCI_NETBSD_CONFIGURE # Do not rely on BIOS/whatever to configure PCI devices
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options PCI_NETBSD_CONFIGURE # Do not rely on BIOS/whatever to configure PCI devices
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#options PCI_CONFIGURE_VERBOSE # Show PCI config information
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# wscons options
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@ -149,9 +158,13 @@ gtpci1 at gt0 unit 1 # 64-bit, 66MHz
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pci* at gtpci?
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# 16550s off CS2
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obio0 at gt0 unit 0 # Chip Select 0
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obio1 at gt0 unit 1 # Chip Select 1
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obio2 at gt0 unit 2 # Chip Select 2
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com0 at obio2 offset 0x0020 size 8 irq 85
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com1 at obio2 offset 0x0000 size 8 irq 86
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obio3 at gt0 unit 3 # Chip Select 3
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obio4 at gt0 unit 4 # Boot Chip Select
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# UARTs
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gtmpsc0 at gt0 unit 0 # Serial #0
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@ -161,7 +174,6 @@ gtmpsc1 at gt0 unit 1 # Serial #1
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gfe0 at gt0 unit 0 flags 1 # Ethernet #0 (RMMI)
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gfe1 at gt0 unit 1 flags 1 # Ethernet #1 (RMMI)
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gfe2 at gt0 unit 2 flags 1 # Ethernet #2 (RMMI)
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acphy* at mii? phy ?
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# PCI devices
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ppb* at pci? dev ? function ? # PCI-PCI bridges
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@ -193,15 +205,18 @@ pci* at ppb? bus ?
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#ucom* at uvscom? portno ?
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fxp* at pci? dev ? function ? # Intel EtherExpress PRO 10+/100B
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sip* at pci? dev ? function ? # SiS 900/DP83815 Ethernet
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rtk* at pci? dev ? function ? # Realtek 8129/8139
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ep* at pci? dev ? function ?
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wm* at pci? dev ? function ?
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fxp* at pci? dev ? function ? # Intel EtherExpress PRO 10+/100B
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tlp* at pci? dev ? function ? # Digital 'Tulip' cards
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wm* at pci? dev ? function ? # Intel GigE cards
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acphy* at mii? phy ?
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inphy* at mii? phy ?
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makphy* at mii? phy ?
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nsphy* at mii? phy ?
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sqphy* at mii? phy ?
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ukphy* at mii? phy ?
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siop* at pci? dev ? function ?
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esiop* at pci? dev ? function ?
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isp* at pci? dev ? function ?
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scsibus* at scsi?
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sd* at scsibus? target ? lun ?
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@ -210,8 +225,8 @@ cd* at scsibus? target ? lun ?
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#auvia* at pci? dev ? function ? # VIA VT82C686A integrated AC'97 Audio
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#audio* at auvia?
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#pciide* at pci? dev ? function ? flags 0x0000
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#wd* at pciide? channel ? drive ? flags 0x0000
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pciide* at pci? dev ? function ? flags 0x0000
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wd* at pciide? channel ? drive ? flags 0x0000
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#pseudo-device vnd 4 # disk-like interface to files
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#pseudo-device ccd 4 # concatenated/striped disk devices
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@ -219,7 +234,7 @@ cd* at scsibus? target ? lun ?
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#options RAID_AUTOCONFIG # auto-configuration of RAID components
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pseudo-device md 1 # memory disk device
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pseudo-device loop # network loopback
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#pseudo-device bpfilter 8 # packet filter
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pseudo-device bpfilter 8 # packet filter
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#pseudo-device ipfilter # IP filter (firewall) and NAT
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#pseudo-device ppp 2 # Point-to-Point Protocol
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#pseudo-device sl 2 # Serial Line IP
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@ -1,8 +1,9 @@
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# $NetBSD: files.ev64260,v 1.2 2003/03/16 07:07:17 matt Exp $
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# $NetBSD: files.ev64260,v 1.3 2003/03/24 17:07:16 matt Exp $
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#
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# Marvell (Galileo) "EV64260" evaluation board's specific configuration info
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#
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#file dev/cninit.c
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defparam opt_ev64260.h OBIO0_STRIDE OBIO1_STRIDE OBIO2_STRIDE OBIO3_STRIDE
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defparam opt_ev64260.h PCI0_GPPINTS PCI1_GPPINTS PCI0_SKIPMASK PCI1_SKIPMASK
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file arch/evbppc/ev64260/autoconf.c
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#file arch/evbppc/ev64260/bus_space.c
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@ -57,6 +58,10 @@ attach cpu at mainbus
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attach com at obio with com_obio
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file arch/evbppc/ev64260/com_obio.c com_obio
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# wdc port
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attach wdc at obio with wdc_obio
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file arch/evbppc/ev64260/wdc_obio.c wdc_obio
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#
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# PCI-only drivers
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# XXX MUST BE INCLUDED BEFORE files.isa, as long as files.isa attaches
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@ -1,4 +1,4 @@
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/* $NetBSD: com_obio.c,v 1.1 2003/03/16 07:07:19 matt Exp $ */
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/* $NetBSD: com_obio.c,v 1.2 2003/03/24 17:07:17 matt Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -138,9 +138,6 @@ com_obio_attach(struct device *parent, struct device *self, void *aux)
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struct com_softc *sc = &osc->osc_com;
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struct obio_attach_args *oa = aux;
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/*
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* We're living on an obio that looks like an sbus slot.
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*/
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sc->sc_iot = oa->oa_memt;
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sc->sc_iobase = oa->oa_offset;
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sc->sc_frequency = COM_FREQ*2;
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@ -1,4 +1,4 @@
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/* $NetBSD: ev64260_locore.S,v 1.3 2003/03/18 14:56:21 matt Exp $ */
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/* $NetBSD: ev64260_locore.S,v 1.4 2003/03/24 17:07:17 matt Exp $ */
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/* $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $ */
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/*
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@ -68,6 +68,12 @@ GLOBAL(endsym)
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GLOBAL(proc0paddr)
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.long 0 /* proc0 p_addr */
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GLOBAL(intrnames)
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GLOBAL(eintrnames)
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GLOBAL(intrcnt)
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GLOBAL(eintrcnt)
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.long 0 /* vmstat needs these. XXX */
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/*
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* File-scope for locore.S
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*/
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@ -79,6 +85,7 @@ dink_stack:
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.long 0 /* fake uarea during idle after exit */
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#endif
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/*
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* This symbol is here for the benefit of kvm_mkdb, and is supposed to
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* mark the start of kernel text.
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@ -132,6 +139,12 @@ __start:
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sync ; isync
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#if 1
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mfpvr 0
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srwi 0,0,16
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cmplwi 0,MPC7410
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bne 16f
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#if 0
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/* flush and disable L2 */
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mfspr 8,SPR_L2CR
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lis 0,(L2CR_L2E|L2CR_L2WT)@h /* disable the L2 mode */
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@ -147,7 +160,8 @@ __start:
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andc 8,8,0
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mtspr SPR_HID0,8
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sync
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#if 1
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#endif
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#if 0
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/*
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* Flush the L1 cache
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*/
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@ -158,6 +172,17 @@ __start:
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sync
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#endif
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#if 1
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/* disable data and instruction caches */
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mfspr 8,SPR_HID0
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li 0,HID0_DLOCK@l
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andc 8,8,0
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sync
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mtspr SPR_HID0,8
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sync
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isync
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#endif
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7:
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#if 0
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/* disable data and instruction caches */
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mfspr 8,SPR_HID0
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li 0,(HID0_ICE|HID0_DCE)@l
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sync
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isync
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#endif
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#if 1
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7:
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#if 0
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/* Enable and flush data and instruction caches */
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# ori 8,8,(HID0_ICFI|HID0_ICE|HID0_DCFI|HID0_DCE)
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ori 8,8,(HID0_ICFI|HID0_ICE)
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ori 8,8,(HID0_ICFI|HID0_ICE|HID0_DCFI|HID0_DCE)
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# ori 8,8,(HID0_ICFI|HID0_ICE)
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mtspr SPR_HID0,8
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isync
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7: sync
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8: sync
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mfspr 8,SPR_HID0
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andi. 0,8,(HID0_ICFI|HID0_DCFI)
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bne 7b
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bne 8b
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#endif
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#if 1
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#if 0
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mfspr 8,SPR_L2CR
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oris 8,8,L2CR_L2E@h
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sync
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mtspr SPR_L2CR,8
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sync
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#endif
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16:
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#endif
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/* compute end of kernel memory */
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@ -1,4 +1,4 @@
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/* $NetBSD: gt_mainbus.c,v 1.6 2003/03/18 19:35:01 matt Exp $ */
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/* $NetBSD: gt_mainbus.c,v 1.7 2003/03/24 17:07:17 matt Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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@ -35,6 +35,7 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_ev64260.h"
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/device.h>
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@ -77,6 +78,19 @@ struct powerpc_bus_dma_tag gt_bus_dma_tag = {
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_bus_dmamem_mmap,
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};
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const int gtpci_skipmask[2] = {
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#ifdef PCI0_SKIPMASK
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PCI0_SKIPMASK,
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#else
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0,
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#endif
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#ifdef PCI1_SKIPMASK
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PCI1_SKIPMASK,
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#else
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0,
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#endif
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};
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static int gt_match(struct device *, struct cfdata *, void *);
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static void gt_attach(struct device *, struct device *, void *);
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@ -145,6 +159,10 @@ gtpci_bus_configure(struct gtpci_chipset *gtpc)
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{
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#ifdef PCI_NETBSD_CONFIGURE
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struct extent *ioext, *memext;
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#if 0
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extern int pci_conf_debug;
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pci_conf_debug = 1;
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#endif
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switch (gtpc->gtpc_busno) {
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case 0:
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@ -178,23 +196,30 @@ gtpci_md_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin,
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{
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#ifdef PCI_NETBSD_CONFIGURE
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struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
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if (gtpc->gtpc_busno == 0)
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*iline = IRQ_GPP_BASE + 27;
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else
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*iline = IRQ_GPP_BASE + 29;
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int line = (gtpc->gtpc_busno == 0 ? PCI0_GPPINTS : PCI1_GPPINTS);
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*iline = (line >> (8 * ((pin + swiz - 1) & 3))) & 0xff;
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if (*iline != 0xff)
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*iline += IRQ_GPP_BASE;
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#endif /* PCI_NETBSD_CONFIGURE */
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}
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void
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gtpci_md_bus_devorder(pci_chipset_tag_t pc, int busno, char devs[])
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{
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int i;
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struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
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int dev;
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/*
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* Don't bother probing the GT itself.
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*/
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for (i = (busno == 0); i < 32; i++)
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*devs++ = i;
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for (dev = 0; dev < 32; dev++) {
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if (PCI_CFG_GET_BUSNO(gtpc->gtpc_self) == busno &&
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(PCI_CFG_GET_DEVNO(gtpc->gtpc_self) == dev ||
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(gtpci_skipmask[gtpc->gtpc_busno] & (1 << dev))))
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continue;
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*devs++ = dev;
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}
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*devs = -1;
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}
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@ -205,7 +230,7 @@ gtpci_md_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func,
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if (bus == 0 && dev == 0) /* don't configure GT */
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return 0;
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return PCI_CONF_ALL /* PCI_CONF_MAP_MEM|PCI_CONF_ENABLE_MEM */;
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return PCI_CONF_ALL;
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}
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int
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@ -214,7 +239,7 @@ gtpci_md_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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int pin = pa->pa_intrpin;
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int line = pa->pa_intrline;
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|
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if (pin > 4) {
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if (pin > 4 || line >= NIRQ) {
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printf("pci_intr_map: bad interrupt pin %d\n", pin);
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*ihp = -1;
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return 1;
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|
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.7 2003/03/18 19:33:50 matt Exp $ */
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/* $NetBSD: machdep.c,v 1.8 2003/03/24 17:07:18 matt Exp $ */
|
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|
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/*
|
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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|
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@ -32,6 +32,7 @@
|
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*/
|
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|
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#include "opt_marvell.h"
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#include "opt_ev64260.h"
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#include "opt_compat_netbsd.h"
|
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#include "opt_ddb.h"
|
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#include "opt_inet.h"
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|
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@ -101,6 +102,7 @@ void isa_intr_init(void);
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|
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#include <dev/marvell/gtreg.h>
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#include <dev/marvell/gtvar.h>
|
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#include <dev/marvell/gtethreg.h>
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#include "gtmpsc.h"
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#if (NGTMPSC > 0)
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|
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@ -119,15 +121,17 @@ struct mem_region physmemr[PMONMEMREGIONS], availmemr[PMONMEMREGIONS];
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char *bootpath;
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paddr_t avail_end; /* XXX temporary */
|
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|
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void initppc(u_int, u_int, u_int, void *); /* Called from locore */
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void strayintr(int);
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int lcsplx(int);
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void gt_bus_space_init(void);
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void gt_find_memory(bus_space_tag_t, bus_space_handle_t, paddr_t);
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void gt_halt(bus_space_tag_t, bus_space_handle_t);
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void return_to_dink(int);
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void calc_delayconst(void);
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void kcomcnputs(dev_t, const char *);
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struct powerpc_bus_space gt_pci0_mem_bs_tag = {
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_BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE,
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0x00000000, 0x00000000, 0x00000000,
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@ -144,8 +148,24 @@ struct powerpc_bus_space gt_pci1_io_bs_tag = {
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_BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE,
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0x00000000, 0x00000000, 0x00000000,
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};
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struct powerpc_bus_space gt_obio0_bs_tag = {
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_BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO0_STRIDE,
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0x00000000, 0x00000000, 0x00000000,
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};
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struct powerpc_bus_space gt_obio1_bs_tag = {
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_BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO1_STRIDE,
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0x00000000, 0x00000000, 0x00000000,
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};
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struct powerpc_bus_space gt_obio2_bs_tag = {
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_BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|2,
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_BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO2_STRIDE,
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||||
0x00000000, 0x00000000, 0x00000000,
|
||||
};
|
||||
struct powerpc_bus_space gt_obio3_bs_tag = {
|
||||
_BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO3_STRIDE,
|
||||
0x00000000, 0x00000000, 0x00000000,
|
||||
};
|
||||
struct powerpc_bus_space gt_bootcs_bs_tag = {
|
||||
_BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE,
|
||||
0x00000000, 0x00000000, 0x00000000,
|
||||
};
|
||||
struct powerpc_bus_space gt_mem_bs_tag = {
|
||||
|
|
@ -155,56 +175,50 @@ struct powerpc_bus_space gt_mem_bs_tag = {
|
|||
|
||||
bus_space_handle_t gt_memh;
|
||||
|
||||
bus_space_tag_t obio_bs_tags[5] = {
|
||||
NULL, NULL, >_obio2_bs_tag, NULL, NULL
|
||||
struct powerpc_bus_space *obio_bs_tags[5] = {
|
||||
>_obio0_bs_tag, >_obio1_bs_tag, >_obio2_bs_tag,
|
||||
>_obio1_bs_tag, >_bootcs_bs_tag
|
||||
};
|
||||
|
||||
static char ex_storage[6][EXTENT_FIXED_STORAGE_SIZE(8)]
|
||||
static char ex_storage[10][EXTENT_FIXED_STORAGE_SIZE(8)]
|
||||
__attribute__((aligned(8)));
|
||||
|
||||
#if 0
|
||||
cons_decl(gtmpsc);
|
||||
|
||||
struct consdev constab[] = {
|
||||
cons_init_halt(gtmpsc),
|
||||
{ 0 }
|
||||
const struct gt_decode_info {
|
||||
bus_addr_t low_decode;
|
||||
bus_addr_t high_decode;
|
||||
} decode_regs[] = {
|
||||
{ GT_SCS0_Low_Decode, GT_SCS0_High_Decode },
|
||||
{ GT_SCS1_Low_Decode, GT_SCS1_High_Decode },
|
||||
{ GT_SCS2_Low_Decode, GT_SCS2_High_Decode },
|
||||
{ GT_SCS3_Low_Decode, GT_SCS3_High_Decode },
|
||||
{ GT_CS0_Low_Decode, GT_CS0_High_Decode },
|
||||
{ GT_CS1_Low_Decode, GT_CS1_High_Decode },
|
||||
{ GT_CS2_Low_Decode, GT_CS2_High_Decode },
|
||||
{ GT_CS3_Low_Decode, GT_CS3_High_Decode },
|
||||
{ GT_BootCS_Low_Decode, GT_BootCS_High_Decode },
|
||||
};
|
||||
#endif
|
||||
|
||||
void
|
||||
initppc(startkernel, endkernel, args, btinfo)
|
||||
u_int startkernel, endkernel, args;
|
||||
void *btinfo;
|
||||
{
|
||||
#ifdef DDB
|
||||
extern void *startsym, *endsym;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Hardcode 32MB for now--we should probe for this or get it
|
||||
* from a boot loader, but for now, we are booting via an
|
||||
* S-record loader.
|
||||
*/
|
||||
{ /* XXX AKB */
|
||||
u_int32_t physmemsize;
|
||||
|
||||
physmemsize = 92 * 1024 * 1024;
|
||||
physmemr[0].start = 0;
|
||||
physmemr[0].size = physmemsize;
|
||||
physmemr[1].size = 0;
|
||||
availmemr[0].start = (endkernel + PGOFSET) & ~PGOFSET;
|
||||
availmemr[0].size = physmemsize - availmemr[0].start;
|
||||
availmemr[1].size = 0;
|
||||
}
|
||||
avail_end = physmemr[0].start + physmemr[0].size; /* XXX temporary */
|
||||
|
||||
oea_batinit(0xf0000000, BAT_BL_256M);
|
||||
oea_init((void (*)(void))ext_intr);
|
||||
|
||||
gt_bus_space_init();
|
||||
|
||||
calc_delayconst(); /* Set CPU clock */
|
||||
|
||||
DELAY(100000);
|
||||
|
||||
gt_bus_space_init();
|
||||
gt_find_memory(>_mem_bs_tag, gt_memh, roundup(endkernel, NBPG));
|
||||
gt_halt(>_mem_bs_tag, gt_memh);
|
||||
|
||||
/*
|
||||
* Now that we known how much memory, reinit the bats.
|
||||
*/
|
||||
oea_batinit(0xf0000000, BAT_BL_256M);
|
||||
|
||||
consinit();
|
||||
|
||||
#if (NISA > 0)
|
||||
|
|
@ -222,7 +236,11 @@ initppc(startkernel, endkernel, args, btinfo)
|
|||
pmap_bootstrap(startkernel, endkernel);
|
||||
|
||||
#ifdef DDB
|
||||
ddb_init((int)((u_int)endsym - (u_int)startsym), startsym, endsym);
|
||||
{
|
||||
extern void *startsym, *endsym;
|
||||
ddb_init((int)((u_int)endsym - (u_int)startsym),
|
||||
startsym, endsym);
|
||||
}
|
||||
#endif
|
||||
#ifdef IPKDB
|
||||
/*
|
||||
|
|
@ -235,18 +253,71 @@ initppc(startkernel, endkernel, args, btinfo)
|
|||
}
|
||||
|
||||
void
|
||||
mem_regions(mem, avail)
|
||||
struct mem_region **mem, **avail;
|
||||
mem_regions(struct mem_region **mem, struct mem_region **avail)
|
||||
{
|
||||
*mem = physmemr;
|
||||
*avail = availmemr;
|
||||
}
|
||||
|
||||
static __inline void
|
||||
gt_record_memory(int j, paddr_t start, paddr_t end, paddr_t endkernel)
|
||||
{
|
||||
physmemr[j].start = start;
|
||||
physmemr[j].size = end - start;
|
||||
if (start < endkernel)
|
||||
start = endkernel;
|
||||
availmemr[j].start = start;
|
||||
availmemr[j].size = end - start;
|
||||
}
|
||||
|
||||
void
|
||||
gt_find_memory(bus_space_tag_t memt, bus_space_handle_t memh,
|
||||
paddr_t endkernel)
|
||||
{
|
||||
paddr_t start, end;
|
||||
int i, j = 0, first = 1;
|
||||
|
||||
/*
|
||||
* Round kernel end to a page boundary.
|
||||
*/
|
||||
for (i = 0; i < 4; i++) {
|
||||
paddr_t nstart, nend;
|
||||
nstart = GT_LowAddr_GET(bus_space_read_4(>_mem_bs_tag,
|
||||
gt_memh, decode_regs[i].low_decode));
|
||||
nend = GT_HighAddr_GET(bus_space_read_4(>_mem_bs_tag,
|
||||
gt_memh, decode_regs[i].high_decode)) + 1;
|
||||
if (nstart >= nend)
|
||||
continue;
|
||||
if (first) {
|
||||
/*
|
||||
* First entry? Just remember it.
|
||||
*/
|
||||
start = nstart;
|
||||
end = nend;
|
||||
first = 0;
|
||||
} else if (nstart == end) {
|
||||
/*
|
||||
* Contiguous? Just update the end.
|
||||
*/
|
||||
end = nend;
|
||||
} else {
|
||||
/*
|
||||
* Disjoint? record it.
|
||||
*/
|
||||
gt_record_memory(j, start, end, endkernel);
|
||||
start = nstart;
|
||||
end = nend;
|
||||
j++;
|
||||
}
|
||||
}
|
||||
gt_record_memory(j, start, end, endkernel);
|
||||
}
|
||||
|
||||
/*
|
||||
* Machine dependent startup code.
|
||||
*/
|
||||
void
|
||||
cpu_startup()
|
||||
cpu_startup(void)
|
||||
{
|
||||
register_t msr;
|
||||
|
||||
|
|
@ -271,11 +342,11 @@ cpu_startup()
|
|||
* Initialize system console.
|
||||
*/
|
||||
void
|
||||
consinit()
|
||||
consinit(void)
|
||||
{
|
||||
#ifdef MPSC_CONSOLE
|
||||
/* PMON using MPSC0 @ 9600 */
|
||||
gtmpsccnattach(>_mem_bs_tag, gt_memh, 0, 9600,
|
||||
gtmpsccnattach(>_mem_bs_tag, gt_memh, MPSC_CONSOLE, 9600,
|
||||
(TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8);
|
||||
#else
|
||||
/* PPCBOOT using COM1 @ 57600 */
|
||||
|
|
@ -290,9 +361,7 @@ consinit()
|
|||
* mi keyboard controller driver
|
||||
*/
|
||||
int
|
||||
pckbc_machdep_cnattach(kbctag, kbcslot)
|
||||
pckbc_tag_t kbctag;
|
||||
pckbc_slot_t kbcslot;
|
||||
pckbc_machdep_cnattach(pckbc_tag_t kbctag, pckbc_slot_t kbcslot)
|
||||
{
|
||||
#if (NPC > 0)
|
||||
return (pcconskbd_cnattach(kbctag, kbcslot));
|
||||
|
|
@ -315,9 +384,7 @@ strayintr(int irq)
|
|||
* Halt or reboot the machine after syncing/dumping according to howto.
|
||||
*/
|
||||
void
|
||||
cpu_reboot(howto, what)
|
||||
int howto;
|
||||
char *what;
|
||||
cpu_reboot(int howto, char *what)
|
||||
{
|
||||
static int syncing;
|
||||
static char str[256];
|
||||
|
|
@ -369,12 +436,39 @@ cpu_reboot(howto, what)
|
|||
}
|
||||
|
||||
int
|
||||
lcsplx(ipl)
|
||||
int ipl;
|
||||
lcsplx(int ipl)
|
||||
{
|
||||
return spllower(ipl);
|
||||
}
|
||||
|
||||
void
|
||||
gt_halt(bus_space_tag_t gt_memt, bus_space_handle_t gt_memh)
|
||||
{
|
||||
int i;
|
||||
u_int32_t data;
|
||||
|
||||
bus_space_write_4(gt_memt, gt_memh,
|
||||
SDMA_U_SDCM(0), SDMA_SDCM_AR|SDMA_SDCM_AT);
|
||||
bus_space_write_4(gt_memt, gt_memh,
|
||||
SDMA_U_SDCM(1), SDMA_SDCM_AR|SDMA_SDCM_AT);
|
||||
/*
|
||||
* Shut down the Ethernets
|
||||
*/
|
||||
for (i = 0; i < 3; i++) {
|
||||
bus_space_write_4(gt_memt, gt_memh,
|
||||
ETH_ESDCMR(2), ETH_ESDCMR_AR|ETH_ESDCMR_AT);
|
||||
for (;;) {
|
||||
data = bus_space_read_4(gt_memt, gt_memh,
|
||||
ETH_ESDCMR(i));
|
||||
if (((ETH_ESDCMR_AR|ETH_ESDCMR_AT) & data) == 0)
|
||||
break;
|
||||
}
|
||||
data = bus_space_read_4(gt_memt, gt_memh, ETH_EPCR(i));
|
||||
data &= ~ETH_EPCR_EN;
|
||||
bus_space_write_4(gt_memt, gt_memh, ETH_EPCR(i), data);
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
gtget_macaddr(struct gt_softc *gt, int macno, char *enaddr)
|
||||
{
|
||||
|
|
@ -392,23 +486,34 @@ void
|
|||
gt_bus_space_init(void)
|
||||
{
|
||||
bus_space_tag_t gt_memt = >_mem_bs_tag;
|
||||
const struct gt_decode_info *di;
|
||||
uint32_t datal, datah;
|
||||
int error;
|
||||
int bs = 0;
|
||||
int j;
|
||||
|
||||
error = bus_space_init(>_mem_bs_tag, "gtmem",
|
||||
ex_storage[0], sizeof(ex_storage[0]));
|
||||
ex_storage[bs], sizeof(ex_storage[bs]));
|
||||
|
||||
error = bus_space_map(gt_memt, 0, 0x10000, 0, >_memh);
|
||||
|
||||
error = bus_space_map(gt_memt, 0, 4096, 0, >_memh);
|
||||
for (j = 0, di = &decode_regs[4]; j < 5; j++, di++) {
|
||||
struct powerpc_bus_space *memt = obio_bs_tags[j];
|
||||
datal = bus_space_read_4(gt_memt, gt_memh, di->low_decode);
|
||||
datah = bus_space_read_4(gt_memt, gt_memh, di->high_decode);
|
||||
|
||||
datal = bus_space_read_4(gt_memt, gt_memh, GT_CS2_Low_Decode);
|
||||
datah = bus_space_read_4(gt_memt, gt_memh, GT_CS2_High_Decode);
|
||||
gt_obio2_bs_tag.pbs_offset = GT_LowAddr_GET(datal);
|
||||
gt_obio2_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 -
|
||||
gt_obio2_bs_tag.pbs_offset;
|
||||
if (GT_LowAddr_GET(datal) >= GT_HighAddr_GET(datal)) {
|
||||
obio_bs_tags[j] = NULL;
|
||||
continue;
|
||||
}
|
||||
memt->pbs_offset = GT_LowAddr_GET(datal);
|
||||
memt->pbs_limit = GT_HighAddr_GET(datah) + 1 -
|
||||
memt->pbs_offset;
|
||||
|
||||
error = bus_space_init(>_obio2_bs_tag, "obio2",
|
||||
ex_storage[1], sizeof(ex_storage[1]));
|
||||
error = bus_space_init(memt, "obio2",
|
||||
ex_storage[bs], sizeof(ex_storage[bs]));
|
||||
bs++;
|
||||
}
|
||||
|
||||
datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_Low_Decode);
|
||||
datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_High_Decode);
|
||||
|
|
@ -416,12 +521,14 @@ gt_bus_space_init(void)
|
|||
gt_pci0_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1;
|
||||
|
||||
error = bus_space_init(>_pci0_mem_bs_tag, "pci0-mem",
|
||||
ex_storage[2], sizeof(ex_storage[2]));
|
||||
ex_storage[bs], sizeof(ex_storage[bs]));
|
||||
bs++;
|
||||
|
||||
/*
|
||||
* Make sure PCI0 Memory is BAT mapped.
|
||||
*/
|
||||
oea_iobat_add(gt_pci0_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M);
|
||||
if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal))
|
||||
oea_iobat_add(gt_pci0_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M);
|
||||
|
||||
/*
|
||||
* Make sure that I/O space start at 0.
|
||||
|
|
@ -435,7 +542,8 @@ gt_bus_space_init(void)
|
|||
gt_pci0_io_bs_tag.pbs_offset;
|
||||
|
||||
error = bus_space_init(>_pci0_io_bs_tag, "pci0-ioport",
|
||||
ex_storage[3], sizeof(ex_storage[3]));
|
||||
ex_storage[bs], sizeof(ex_storage[bs]));
|
||||
bs++;
|
||||
|
||||
#if 0
|
||||
error = extent_alloc_region(gt_pci0_io_bs_tag.pbs_extent,
|
||||
|
|
@ -451,12 +559,14 @@ gt_bus_space_init(void)
|
|||
gt_pci1_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1;
|
||||
|
||||
error = bus_space_init(>_pci1_mem_bs_tag, "pci1-mem",
|
||||
ex_storage[4], sizeof(ex_storage[4]));
|
||||
ex_storage[bs], sizeof(ex_storage[bs]));
|
||||
bs++;
|
||||
|
||||
/*
|
||||
* Make sure PCI1 Memory is BAT mapped.
|
||||
*/
|
||||
oea_iobat_add(gt_pci1_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M);
|
||||
if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal))
|
||||
oea_iobat_add(gt_pci1_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M);
|
||||
|
||||
/*
|
||||
* Make sure that I/O space start at 0.
|
||||
|
|
@ -470,7 +580,8 @@ gt_bus_space_init(void)
|
|||
gt_pci1_io_bs_tag.pbs_offset;
|
||||
|
||||
error = bus_space_init(>_pci1_io_bs_tag, "pci1-ioport",
|
||||
ex_storage[5], sizeof(ex_storage[5]));
|
||||
ex_storage[bs], sizeof(ex_storage[bs]));
|
||||
bs++;
|
||||
|
||||
#if 0
|
||||
error = extent_alloc_region(gt_pci1_io_bs_tag.pbs_extent,
|
||||
|
|
|
|||
Loading…
Reference in New Issue