Clean up deleted files.

This commit is contained in:
mycroft 1995-01-29 02:58:32 +00:00
parent f11e7e33fe
commit 1e719386a7
7 changed files with 0 additions and 723 deletions

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/* $NetBSD: cd1400.h,v 1.2 1994/10/27 04:18:37 cgd Exp $ */
/*
* cyclades cyclom-y serial driver
* Andrew Herbert <andrew@werple.apana.org.au>, 17 August 1993
*
* Copyright (c) 1993 Andrew Herbert.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name Andrew Herbert may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL I BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define CD1400_NO_OF_CHANNELS 4 /* four serial channels per chip */
#define CD1400_FIFOSIZE 12 /* 12 chars */
/* register definitions */
#define CD1400_CCR 2*0x05 /* channel control */
#define CD1400_CMD_RESET 0x81 /* full reset */
#define CD1400_SRER 2*0x06 /* service request enable */
#define CD1400_GFRCR 2*0x40 /* global firmware revision code */
#define CD1400_LIVR 2*0x18 /* local intr vector */
#define CD1400_MIVR 2*0x41 /* modem intr vector */
#define CD1400_TIVR 2*0x42 /* transmit intr vector */
#define CD1400_RIVR 2*0x43 /* receive intr vector */
#define CD1400_RIVR_EXCEPTION (1<<2) /* receive exception bit */
#define CD1400_RICR 2*0x44 /* receive intr channel */
#define CD1400_TICR 2*0x45 /* transmit intr channel */
#define CD1400_MICR 2*0x46 /* modem intr channel */
#define CD1400_RDCR 2*0x0e /* rx data count */
#define CD1400_EOSRR 2*0x60 /* end of service request */
#define CD1400_RDSR 2*0x62 /* rx data/status */
#define CD1400_RDSR_OVERRUN (1<<0) /* rx overrun error */
#define CD1400_RDSR_FRAMING (1<<1) /* rx framing error */
#define CD1400_RDSR_PARITY (1<<2) /* rx parity error */
#define CD1400_RDSR_BREAK (1<<3) /* rx break */
#define CD1400_RDSR_SPECIAL (7<<4) /* rx special char */
#define CD1400_RDSR_SPECIAL_SHIFT 4 /* rx special char shift */
#define CD1400_RDSR_TIMEOUT (1<<7) /* rx timeout */
#define CD1400_TDR 2*0x63 /* tx data */
#define CD1400_MISR 2*0x4c /* modem intr status */
#define CD1400_MISR_DSRd (1<<7) /* DSR delta */
#define CD1400_MISR_CTSd (1<<6) /* CTS delta */
#define CD1400_MISR_RId (1<<5) /* RI delta */
#define CD1400_MISR_CDd (1<<4) /* CD delta */
#define CD1400_MSVR 2*0x6d /* modem signals */
#define CD1400_MSVR_DSR (1<<7) /* !DSR line */
#define CD1400_MSVR_CTS (1<<6) /* !CTS line */
#define CD1400_MSVR_RI (1<<5) /* !RI line */
#define CD1400_MSVR_CD (1<<4) /* !CD line */
#define CD1400_MSVR_DTR (1<<1) /* DTR line */
#define CD1400_DTR 2*0x6d /* dtr control */
#define CD1400_DTR_CLEAR 0
#define CD1400_DTR_SET (1<<1)
#define CD1400_PPR 2*0x7e
#define CD1400_CLOCK_25_1MS 0x31
#define CD1400_CAR 2*0x68 /* channel access */
#define CD1400_RIR 2*0x6B /* receive interrupt status */
#define CD1400_TIR 2*0x6A /* transmit interrupt status */
#define CD1400_MIR 2*0x69 /* modem interrupt status */
#define CD1400_RBPR 2*0x78 /* receive baud rate period */
#define CD1400_RCOR 2*0x7C /* receive clock option */
#define CD1400_TBPR 2*0x72 /* transmit baud rate period */
#define CD1400_TCOR 2*0x76 /* transmit clock option */
#define CD1400_COR1 2*0x08 /* channel option 1 */
#define CD1400_COR2 2*0x09 /* channel option 2 */
#define CD1400_COR3 2*0x0A /* channel option 3 */
#define CD1400_COR4 2*0x1E /* channel option 4 */
#define CD1400_COR5 2*0x1F /* channel option 5 */
#define CD1400_SCHR1 2*0x1A /* special character 1 */
#define CD1400_SCHR2 2*0x1B /* special character 2 */
#define CD1400_SCHR3 2*0x1C /* special character 3 */
#define CD1400_SCHR4 2*0x1D /* special character 4 */
#define CD1400_MCOR1 2*0x15 /* modem change 1 */
#define CD1400_MCOR2 2*0x16 /* modem change 2 */
#define CD1400_RTPR 2*0x21 /* receive timeout period */
#define CD1400_SVRR 2*0x67 /* service request */
#define CD1400_SVRR_RX (1<<0)
#define CD1400_SVRR_TX (1<<1)
#define CD1400_SVRR_MDM (1<<2)
/* hardware SVCACK addresses, for use in interrupt handlers */
#define CD1400_SVCACKR 0x100
#define CD1400_SVCACKT 0x200
#define CD1400_SVCACKM 0x300

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/* $NetBSD: ds8390.h,v 1.3 1994/10/27 04:18:38 cgd Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)ds8390.h 7.1 (Berkeley) 5/9/91
*/
/*
* Nominal Semidestructor DS8390 Ethernet Chip
* Register and bit definitions
*/
/*
* Page register offset values
*/
#define ds_cmd 0x00 /* Command register: */
#define DSCM_STOP 0x01 /* Stop controller */
#define DSCM_START 0x02 /* Start controller */
#define DSCM_TRANS 0x04 /* Transmit packet */
#define DSCM_RREAD 0x08 /* Remote read */
#define DSCM_RWRITE 0x10 /* Remote write */
#define DSCM_NODMA 0x20 /* No Remote DMA present */
#define DSCM_PG0 0x00 /* Select Page 0 */
#define DSCM_PG1 0x40 /* Select Page 1 */
#define DSCM_PG2 0x80 /* Select Page 2? */
#define ds0_pstart 0x01 /* Page Start register */
#define ds0_pstop 0x02 /* Page Stop register */
#define ds0_bnry 0x03 /* Boundary Pointer */
#define ds0_tsr 0x04 /* Transmit Status (read-only) */
#define DSTS_PTX 0x01 /* Successful packet transmit */
#define DSTS_COLL 0x04 /* Packet transmit w/ collision*/
#define DSTS_COLL16 0x04 /* Packet had >16 collisions & fail */
#define DSTS_UND 0x20 /* FIFO Underrun on transmission*/
#define ds0_tpsr ds0_tsr /* Transmit Page (write-only) */
#define ds0_tbcr0 0x05 /* Transmit Byte count, low WO */
#define ds0_tbcr1 0x06 /* Transmit Byte count, high WO */
#define ds0_isr 0x07 /* Interrupt status register */
#define DSIS_RX 0x01 /* Successful packet reception */
#define DSIS_TX 0x02 /* Successful packet transmission */
#define DSIS_RXE 0x04 /* Packet reception w/error */
#define DSIS_TXE 0x08 /* Packet transmission w/error*/
#define DSIS_ROVRN 0x10 /* Receiver overrun in the ring*/
#define DSIS_CTRS 0x20 /* Diagnostic counters need attn */
#define DSIS_RDC 0x40 /* Remote DMA Complete */
#define DSIS_RESET 0x80 /* Reset Complete */
#define ds0_rsar0 0x08 /* Remote start address low WO */
#define ds0_rsar1 0x09 /* Remote start address high WO */
#define ds0_rbcr0 0x0A /* Remote byte count low WO */
#define ds0_rbcr1 0x0B /* Remote byte count high WO */
#define ds0_rsr 0x0C /* Receive status RO */
#define DSRS_RPC 0x01 /* Received Packet Complete */
#define ds0_rcr ds0_rsr /* Receive configuration WO */
#define DSRC_SEP 0x01 /* Save error packets */
#define DSRC_AR 0x02 /* Accept Runt packets */
#define DSRC_AB 0x04 /* Accept Broadcast packets */
#define DSRC_AM 0x08 /* Accept Multicast packets */
#define DSRC_PRO 0x10 /* Promiscuous physical */
#define DSRC_MON 0x20 /* Monitor mode */
#define ds0_tcr 0x0D /* Transmit configuration WO */
#define DSTC_CRC 0x01 /* Inhibit CRC */
#define DSTC_LB0 0x02 /* Encoded Loopback Control */
#define DSTC_LB1 0x04 /* Encoded Loopback Control */
#define DSTC_ATD 0x08 /* Auto Transmit Disable */
#define DSTC_OFST 0x10 /* Collision Offset Enable */
#define ds0_rcvalctr ds0_tcr /* Receive alignment err ctr RO */
#define ds0_dcr 0x0E /* Data configuration WO */
#define DSDC_WTS 0x01 /* Word Transfer Select */
#define DSDC_BOS 0x02 /* Byte Order Select */
#define DSDC_LAS 0x04 /* Long Address Select */
#define DSDC_BMS 0x08 /* Burst Mode Select */
#define DSDC_AR 0x10 /* Autoinitialize Remote */
#define DSDC_FT0 0x20 /* Fifo Threshold Select */
#define DSDC_FT1 0x40 /* Fifo Threshold Select */
#define ds0_rcvcrcctr ds0_dcr /* Receive CRC error counter RO */
#define ds0_imr 0x0F /* Interrupt mask register WO */
#define DSIM_PRXE 0x01 /* Packet received enable */
#define DSIM_PTXE 0x02 /* Packet transmitted enable */
#define DSIM_RXEE 0x04 /* Receive error enable */
#define DSIM_TXEE 0x08 /* Transmit error enable */
#define DSIM_OVWE 0x10 /* Overwrite warning enable */
#define DSIM_CNTE 0x20 /* Counter overflow enable */
#define DSIM_RDCE 0x40 /* Dma complete enable */
#define ds0_rcvfrmctr ds0_imr /* Receive Frame error cntr RO */
#define ds1_par0 ds0_pstart /* Physical address register 0 */
/* Physical address registers 1-4 */
#define ds1_par5 ds0_tbcr1 /* Physical address register 5 */
#define ds1_curr ds0_isr /* Current page (receive unit) */
#define ds1_mar0 ds0_rsar0 /* Multicast address register 0 */
/* Multicast address registers 1-6 */
#define ds1_mar7 ds0_imr /* Multicast address register 7 */
#define ds1_curr ds0_isr /* Current page (receive unit) */
#define DS_PGSIZE 256 /* Size of RAM pages in bytes */
/*
* Packet receive header, 1 per each buffer page used in receive packet
*/
struct prhdr {
u_char pr_status; /* is this a good packet, same as ds0_rsr */
u_char pr_nxtpg; /* next page of packet or next packet */
u_char pr_sz0;
u_char pr_sz1;
};

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/* $NetBSD: i8042.h,v 1.5 1994/10/27 04:18:39 cgd Exp $ */
#define KBSTATP 0x64 /* kbd controller status port (I) */
#define KBS_DIB 0x01 /* kbd data in buffer */
#define KBS_IBF 0x02 /* kbd input buffer low */
#define KBS_WARM 0x04 /* kbd input buffer low */
#define KBS_OCMD 0x08 /* kbd output buffer has command */
#define KBS_NOSEC 0x10 /* kbd security lock not engaged */
#define KBS_TERR 0x20 /* kbd transmission error */
#define KBS_RERR 0x40 /* kbd receive error */
#define KBS_PERR 0x80 /* kbd parity error */
#define KBCMDP 0x64 /* kbd controller port (O) */
#define KBDATAP 0x60 /* kbd data port (I) */
#define KBOUTP 0x60 /* kbd data port (O) */
#define K_RDCMDBYTE 0x20
#define K_LDCMDBYTE 0x60
#define KC8_TRANS 0x40 /* convert to old scan codes */
#define KC8_MDISABLE 0x20 /* disable mouse */
#define KC8_KDISABLE 0x10 /* disable keyboard */
#define KC8_IGNSEC 0x08 /* ignore security lock */
#define KC8_CPU 0x04 /* exit from protected mode reset */
#define KC8_MENABLE 0x02 /* enable mouse interrupt */
#define KC8_KENABLE 0x01 /* enable keyboard interrupt */
#define CMDBYTE (KC8_TRANS|KC8_CPU|KC8_MENABLE|KC8_KENABLE)

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/* $NetBSD: i8237.h,v 1.4 1994/10/27 04:18:39 cgd Exp $ */
/*
* Intel 8237 DMA Controller
*/
#define DMA37MD_SINGLE 0x40 /* single pass mode */
#define DMA37MD_CASCADE 0xc0 /* cascade mode */
#define DMA37MD_WRITE 0x04 /* read the device, write memory operation */
#define DMA37MD_READ 0x08 /* write the device, read memory operation */
#define DMA37SM_CLEAR 0x00 /* clear mask bit */
#define DMA37SM_SET 0x04 /* set mask bit */

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/* $NetBSD: i82586.h,v 1.3 1995/01/23 04:50:56 mycroft Exp $ */
/*-
* Copyright (c) 1992, University of Vermont and State Agricultural College.
* Copyright (c) 1992, Garrett A. Wollman.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* Vermont and State Agricultural College and Garrett A. Wollman.
* 4. Neither the name of the University nor the name of the author
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR AUTHOR BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Intel 82586 Ethernet chip
* Register, bit, and structure definitions.
*
* Written by GAW with reference to the Clarkson Packet Driver code for this
* chip written by Russ Nelson and others.
*/
struct ie_en_addr {
u_char data[6];
};
/*
* This is the master configuration block. It tells the hardware where all
* the rest of the stuff is.
*/
struct ie_sys_conf_ptr {
u_short mbz; /* must be zero */
u_char ie_bus_use; /* true if 8-bit only */
u_char mbz2[5]; /* must be zero */
caddr_t ie_iscp_ptr; /* 24-bit physaddr of ISCP */
};
/*
* Note that this is wired in hardware; the SCP is always located here, no
* matter what.
*/
#define IE_SCP_ADDR 0xfffff4
/*
* The tells the hardware where all the rest of the stuff is, too.
* FIXME: some of these should be re-commented after we figure out their
* REAL function.
*/
struct ie_int_sys_conf_ptr {
u_char ie_busy; /* zeroed after init */
u_char mbz;
u_short ie_scb_offset; /* 16-bit physaddr of next struct */
caddr_t ie_base; /* 24-bit physaddr for all 16-bit vars */
};
/*
* This FINALLY tells the hardware what to do and where to put it.
*/
struct ie_sys_ctl_block {
u_short ie_status; /* status word */
u_short ie_command; /* command word */
u_short ie_command_list; /* 16-pointer to command block list */
u_short ie_recv_list; /* 16-pointer to receive frame list */
u_short ie_err_crc; /* CRC errors */
u_short ie_err_align; /* Alignment errors */
u_short ie_err_resource; /* Resource errors */
u_short ie_err_overrun; /* Overrun errors */
};
/* Command values */
#define IE_RU_COMMAND 0x0070 /* mask for RU command */
#define IE_RU_NOP 0 /* for completeness */
#define IE_RU_START 0x0010 /* start receive unit command */
#define IE_RU_ENABLE 0x0020 /* enable receiver command */
#define IE_RU_DISABLE 0x0030 /* disable receiver command */
#define IE_RU_ABORT 0x0040 /* abort current receive operation */
#define IE_CU_COMMAND 0x0700 /* mask for CU command */
#define IE_CU_NOP 0 /* included for completeness */
#define IE_CU_START 0x0100 /* do-command command */
#define IE_CU_RESUME 0x0200 /* resume a suspended cmd list */
#define IE_CU_STOP 0x0300 /* SUSPEND was already taken */
#define IE_CU_ABORT 0x0400 /* abort current command */
#define IE_ACK_COMMAND 0xf000 /* mask for ACK command */
#define IE_ACK_CX 0x8000 /* ack IE_ST_DONE */
#define IE_ACK_FR 0x4000 /* ack IE_ST_RECV */
#define IE_ACK_CNA 0x2000 /* ack IE_ST_ALLDONE */
#define IE_ACK_RNR 0x1000 /* ack IE_ST_RNR */
#define IE_ACTION_COMMAND(x) (((x) & IE_CU_COMMAND) == IE_CU_START)
/* is this command an action command? */
/* Status values */
#define IE_ST_WHENCE 0xf000 /* mask for cause of interrupt */
#define IE_ST_DONE 0x8000 /* command with I bit completed */
#define IE_ST_RECV 0x4000 /* frame received */
#define IE_ST_ALLDONE 0x2000 /* all commands completed */
#define IE_ST_RNR 0x1000 /* receive not ready */
#define IE_CU_STATUS 0x700 /* mask for command unit status */
#define IE_CU_ACTIVE 0x200 /* command unit is active */
#define IE_CU_SUSPEND 0x100 /* command unit is suspended */
#define IE_RU_STATUS 0x70 /* mask for receiver unit status */
#define IE_RU_SUSPEND 0x10 /* receiver is suspended */
#define IE_RU_NOSPACE 0x20 /* receiver has no resources */
#define IE_RU_READY 0x40 /* reveiver is ready */
/*
* This is filled in partially by the chip, partially by us.
*/
struct ie_recv_frame_desc {
u_short ie_fd_status; /* status for this frame */
u_short ie_fd_last; /* end of frame list flag */
u_short ie_fd_next; /* 16-pointer to next RFD */
u_short ie_fd_buf_desc; /* 16-pointer to list of buffer desc's */
struct ie_en_addr dest; /* destination ether */
struct ie_en_addr src; /* source ether */
u_short ie_length; /* 802 length/Ether type */
u_short mbz; /* must be zero */
};
#define IE_FD_LAST 0x8000 /* last rfd in list */
#define IE_FD_SUSP 0x4000 /* suspend RU after receipt */
#define IE_FD_COMPLETE 0x8000 /* frame is complete */
#define IE_FD_BUSY 0x4000 /* frame is busy */
#define IE_FD_OK 0x2000 /* frame is bad */
#define IE_FD_RNR 0x0200 /* receiver out of resources here */
/*
* linked list of buffers...
*/
struct ie_recv_buf_desc {
u_short ie_rbd_actual; /* status for this buffer */
u_short ie_rbd_next; /* 16-pointer to next RBD */
caddr_t ie_rbd_buffer; /* 24-pointer to buffer for this RBD */
u_short ie_rbd_length; /* length of the buffer */
u_short mbz; /* must be zero */
};
#define IE_RBD_LAST 0x8000 /* last buffer */
#define IE_RBD_USED 0x4000 /* this buffer has data */
/*
* All commands share this in common.
*/
struct ie_cmd_common {
u_short ie_cmd_status; /* status of this command */
u_short ie_cmd_cmd; /* command word */
u_short ie_cmd_link; /* link to next command */
};
#define IE_STAT_COMPL 0x8000 /* command is completed */
#define IE_STAT_BUSY 0x4000 /* command is running now */
#define IE_STAT_OK 0x2000 /* command completed successfully */
#define IE_STAT_ABORT 0x1000 /* command was aborted */
#define IE_CMD_NOP 0x0000 /* NOP */
#define IE_CMD_IASETUP 0x0001 /* initial address setup */
#define IE_CMD_CONFIG 0x0002 /* configure command */
#define IE_CMD_MCAST 0x0003 /* multicast setup command */
#define IE_CMD_XMIT 0x0004 /* transmit command */
#define IE_CMD_TDR 0x0005 /* time-domain reflectometer command */
#define IE_CMD_DUMP 0x0006 /* dump command */
#define IE_CMD_DIAGNOSE 0x0007 /* diagnostics command */
#define IE_CMD_LAST 0x8000 /* this is the last command in the list */
#define IE_CMD_SUSPEND 0x4000 /* suspend CU after this command */
#define IE_CMD_INTR 0x2000 /* post an interrupt after completion */
/*
* This is the command to transmit a frame.
*/
struct ie_xmit_cmd {
struct ie_cmd_common com; /* common part */
#define ie_xmit_status com.ie_cmd_status
u_short ie_xmit_desc; /* 16-pointer to buffer descriptor */
struct ie_en_addr ie_xmit_addr; /* destination address */
u_short ie_xmit_length; /* 802.3 length/Ether type field */
};
#define IE_XS_MAXCOLL 0x000f /* number of collisions during transmit */
#define IE_XS_EXCMAX 0x0020 /* exceeded maximum number of collisions */
#define IE_XS_SQE 0x0040 /* SQE positive */
#define IE_XS_DEFERRED 0x0080 /* transmission deferred */
#define IE_XS_UNDERRUN 0x0100 /* DMA underrun */
#define IE_XS_LOSTCTS 0x0200 /* Lost CTS */
#define IE_XS_NOCARRIER 0x0400 /* No Carrier */
/*
* This is a buffer descriptor for a frame to be transmitted.
*/
struct ie_xmit_buf {
u_short ie_xmit_flags; /* see below */
u_short ie_xmit_next; /* 16-pointer to next desc. */
caddr_t ie_xmit_buf; /* 24-pointer to the actual buffer */
};
#define IE_XMIT_LAST 0x8000 /* this TBD is the last one */
/* The rest of the `flags' word is actually the length. */
/*
* Multicast setup command.
*/
#define MAXMCAST 250 /* must fit in transmit buffer */
struct ie_mcast_cmd {
struct ie_cmd_common com; /* common part */
#define ie_mcast_status com.ie_cmd_status
u_short ie_mcast_bytes; /* size (in bytes) of multicast addresses */
struct ie_en_addr ie_mcast_addrs[MAXMCAST + 1]; /* space for them */
};
/*
* Time Domain Reflectometer command.
*/
struct ie_tdr_cmd {
struct ie_cmd_common com; /* common part */
#define ie_tdr_status com.ie_cmd_status
u_short ie_tdr_time; /* error bits and time */
};
#define IE_TDR_SUCCESS 0x8000 /* TDR succeeded without error */
#define IE_TDR_XCVR 0x4000 /* detected a transceiver problem */
#define IE_TDR_OPEN 0x2000 /* detected an open */
#define IE_TDR_SHORT 0x1000 /* TDR detected a short */
#define IE_TDR_TIME 0x07ff /* mask for reflection time */
/*
* Initial Address Setup command
*/
struct ie_iasetup_cmd {
struct ie_cmd_common com;
#define ie_iasetup_status com.ie_cmd_status
struct ie_en_addr ie_address;
};
/*
* Configuration command
*/
struct ie_config_cmd {
struct ie_cmd_common com; /* common part */
#define ie_config_status com.ie_cmd_status
u_char ie_config_count; /* byte count (0x0c) */
u_char ie_fifo; /* fifo (8) */
u_char ie_save_bad; /* save bad frames (0x40) */
u_char ie_addr_len; /* address length (0x2e) (AL-LOC == 1) */
u_char ie_priority; /* priority and backoff (0x0) */
u_char ie_ifs; /* inter-frame spacing (0x60) */
u_char ie_slot_low; /* slot time, LSB (0x0) */
u_char ie_slot_high; /* slot time, MSN, and retries (0xf2) */
u_char ie_promisc; /* 1 if promiscuous, else 0 */
u_char ie_crs_cdt; /* CSMA/CD parameters (0x0) */
u_char ie_min_len; /* min frame length (0x40) */
u_char ie_junk; /* stuff for 82596 (0xff) */
};

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/* $NetBSD: nec765.h,v 1.3 1994/10/27 04:18:41 cgd Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)nec765.h 7.1 (Berkeley) 5/9/91
*/
/*
* Nec 765 floppy disc controller definitions
*/
/* Main status register */
#define NE7_DAB 0x01 /* Diskette drive A is seeking, thus busy */
#define NE7_DBB 0x02 /* Diskette drive B is seeking, thus busy */
#define NE7_CB 0x10 /* Diskette Controller Busy */
#define NE7_NDM 0x20 /* Diskette Controller in Non Dma Mode */
#define NE7_DIO 0x40 /* Diskette Controller Data register I/O */
#define NE7_RQM 0x80 /* Diskette Controller ReQuest for Master */
/* Status register ST0 */
#define NE7_ST0BITS "\020\010invld\007abnrml\006seek_cmplt\005drv_chck\004drive_rdy\003top_head"
/* Status register ST1 */
#define NE7_ST1BITS "\020\010end_of_cyl\006bad_crc\005data_overrun\003sec_not_fnd\002write_protect\001no_am"
/* Status register ST2 */
#define NE7_ST2BITS "\020\007ctrl_mrk\006bad_crc\005wrong_cyl\004scn_eq\003scn_not_fnd\002bad_cyl\001no_dam"
/* Status register ST3 */
#define NE7_ST3BITS "\020\010fault\007write_protect\006drdy\005tk0\004two_side\003side_sel\002"
/* Commands */
#define NE7CMD_SPECIFY 3 /* specify drive parameters - requires unit
parameters byte */
#define NE7CMD_SENSED 4 /* sense drive - requires unit select byte */
#define NE7CMD_WRITE 0xc5 /* write - requires eight additional bytes */
#define NE7CMD_READ 0xe6 /* read - requires eight additional bytes */
#define NE7CMD_FORMAT 0x4c /* format - requires five additional bytes */
#define NE7CMD_RECAL 7 /* recalibrate drive - requires
unit select byte */
#define NE7CMD_SENSEI 8 /* sense controller interrupt status */
#define NE7CMD_SEEK 15 /* seek drive - requires unit select byte
and new cyl byte */

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/* $NetBSD: ns16450.h,v 1.3 1994/10/27 04:18:42 cgd Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)ns16450.h 7.1 (Berkeley) 5/9/91
*/
/*
* NS16450 UART registers
*/
#define com_data 0 /* data register (R/W) */
#define com_dlbl 0 /* divisor latch low (W) */
#define com_dlbh 1 /* divisor latch high (W) */
#define com_ier 1 /* interrupt enable (W) */
#define com_iir 2 /* interrupt identification (R) */
#define com_lctl 3 /* line control register (R/W) */
#define com_cfcr 3 /* line control register (R/W) */
#define com_mcr 4 /* modem control register (R/W) */
#define com_lsr 5 /* line status register (R/W) */
#define com_msr 6 /* modem status register (R/W) */