Add driver to attach ARM PL210 L2 Cache Controller
arml2cc0 at armperiph0: ARM PL310 L2 r3p2 Cache Controller arml2cc0: 256KB/32B 16-way L2 Unified cache
This commit is contained in:
matt
parent
a73007ba40
commit
1e00bbeef6
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@ -31,7 +31,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.1 2012/09/01 00:03:14 matt Exp $");
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__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.2 2012/09/02 16:55:10 matt Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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@ -52,7 +52,7 @@ struct armperiph_softc {
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bus_space_handle_t sc_memh;
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};
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#ifdef CPU_CORTEXA9
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#ifdef CPU_CORTEXA5
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static const char * const a5_devices[] = {
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"armscu", "armgic", NULL
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};
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@ -66,7 +66,7 @@ static const char * const a7_devices[] = {
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#ifdef CPU_CORTEXA9
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static const char * const a9_devices[] = {
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"armscu", "armgic", "a9tmr", "a9wdt", NULL
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"armscu", "arml2cc", "armgic", "a9tmr", "a9wdt", NULL
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};
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#endif
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@ -82,7 +82,7 @@ static const struct mpcore_config {
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{ a7_devices, 0x410fc070, 32768 },
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#endif
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#ifdef CPU_CORTEXA9
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{ a9_devices, 0x410fc090, 8192 },
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{ a9_devices, 0x410fc090, 3*4096 },
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#endif
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#ifdef CPU_CORTEXA15
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{ a15_devices, 0x410fc0f0, 32768 },
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@ -1,4 +1,4 @@
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# $NetBSD: files.cortex,v 1.1 2012/09/01 00:03:14 matt Exp $
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# $NetBSD: files.cortex,v 1.2 2012/09/02 16:55:10 matt Exp $
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device armperiph {}
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attach armperiph at mainbus
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@ -9,6 +9,11 @@ device armgic: pic, pic_splfuncs
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attach armgic at armperiph
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file arch/arm/cortex/gic.c armgic
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# ARM PL310 L2 Cache Controller(initially on Cortex-A9)
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device arml2cc
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attach arml2cc at armperiph
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file arch/arm/cortex/pl310.c arml2cc
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# A9 MPCore Global Timer
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device a9tmr
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attach a9tmr at armperiph
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@ -0,0 +1,160 @@
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/* $NetBSD: pl310.c,v 1.1 2012/09/02 16:55:10 matt Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.1 2012/09/02 16:55:10 matt Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <arm/cortex/mpcore_var.h>
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#include <arm/cortex/pl310_reg.h>
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static int arml2cc_match(device_t, cfdata_t, void *);
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static void arml2cc_attach(device_t, device_t, void *);
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#define L2CC_BASE 0x2000
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#define L2CC_SIZE 0x1000
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struct arml2cc_softc {
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device_t sc_dev;
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bus_space_tag_t sc_memt;
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bus_space_handle_t sc_memh;
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};
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CFATTACH_DECL_NEW(arml2cc, sizeof(struct arml2cc_softc),
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arml2cc_match, arml2cc_attach, NULL, NULL);
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static bool attached;
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static inline uint32_t
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arml2cc_read_4(struct arml2cc_softc *sc, bus_size_t o)
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{
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return bus_space_read_4(sc->sc_memt, sc->sc_memh, o);
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}
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static inline void
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arml2cc_write_4(struct arml2cc_softc *sc, bus_size_t o, uint32_t v)
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{
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bus_space_write_4(sc->sc_memt, sc->sc_memh, o, v);
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}
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/* ARGSUSED */
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static int
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arml2cc_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct mpcore_attach_args * const mpcaa = aux;
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if (attached)
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return 0;
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if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid))
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return 0;
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if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0)
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return 0;
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/*
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* This isn't present on UP A9s (since CBAR isn't present).
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*/
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uint32_t mpidr = armreg_mpidr_read();
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if (mpidr == 0 || (mpidr & MPIDR_U))
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return 0;
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return 1;
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}
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static const struct {
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uint8_t rev;
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uint8_t str[7];
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} pl310_revs[] = {
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{ 0, " r0p0" },
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{ 2, " r1p0" },
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{ 4, " r2p0" },
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{ 5, " r3p0" },
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{ 6, " r3p1" },
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{ 8, " r3p2" },
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{ 9, " r3p3" },
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};
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static void
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arml2cc_attach(device_t parent, device_t self, void *aux)
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{
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struct arml2cc_softc * const sc = device_private(self);
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struct mpcore_attach_args * const mpcaa = aux;
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sc->sc_dev = self;
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sc->sc_memt = mpcaa->mpcaa_memt;
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bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh,
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L2CC_BASE, L2CC_SIZE, &sc->sc_memh);
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uint32_t id = arml2cc_read_4(sc, L2C_CACHE_ID);
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u_int rev = __SHIFTOUT(id, CACHE_ID_REV);
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const char *revstr = "";
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for (size_t i = 0; i < __arraycount(pl310_revs); i++) {
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if (rev == pl310_revs[i].rev) {
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revstr = pl310_revs[i].str;
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break;
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}
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}
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aprint_naive("\n");
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aprint_normal(": ARM PL310 L2%s Cache Controller\n", revstr);
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uint32_t cfg = arml2cc_read_4(sc, L2C_CACHE_TYPE);
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//u_int cfg_ctype = __SHIFTOUT(cfg, CACHE_TYPE_CTYPE);
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bool cfg_harvard_p = __SHIFTOUT(cfg, CACHE_TYPE_HARVARD) != 0;
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u_int cfg_dsize = __SHIFTOUT(cfg, CACHE_TYPE_DSIZE);
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u_int d_waysize = 8192 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xWAYSIZE);
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u_int d_assoc = 8 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xASSOC);
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u_int d_linesize = 32 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xLINESIZE);
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u_int d_size = d_waysize * d_assoc;
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if (cfg_harvard_p) {
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u_int cfg_isize = __SHIFTOUT(cfg, CACHE_TYPE_ISIZE);
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u_int i_waysize = 8192 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xWAYSIZE);
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u_int i_assoc = 8 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xASSOC);
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u_int i_linesize = 32 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xLINESIZE);
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u_int i_size = i_waysize * i_assoc;
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aprint_normal_dev(self, "%uKB/%uB %u-way L2 Instruction cache\n",
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i_size / 1024, i_linesize, i_assoc);
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}
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aprint_normal_dev(self, "%uKB/%uB %u-way L2 %s cache\n",
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d_size / 1024, d_linesize, d_assoc,
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(cfg_harvard_p ? "Data" : "Unified"));
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}
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@ -0,0 +1,108 @@
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/* $NetBSD: pl310_reg.h,v 1.1 2012/09/02 16:55:10 matt Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_CORTEX_PL310_REG_H_
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#define _ARM_CORTEX_PL310_REG_H_
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/*
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* ARM PL310 L2 Cache Controller
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* Used by Cortex cores
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*/
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#define L2C_CACHE_ID 0x000
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#define CACHE_ID_IMPL __BITS(31,24)
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#define CACHE_ID_ID __BITS(15,10)
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#define CACHE_ID_PART __BITS(9,6)
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#define CACHE_ID_PART_PL310 3
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#define CACHE_ID_REV __BITS(5,0)
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#define CACHE_ID_REV_R3P3 9
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#define CACHE_ID_REV_R3P2 8
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#define L2C_CACHE_TYPE 0x004
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#define CACHE_TYPE_DATA_BANKING __BIT(31)
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#define CACHE_TYPE_CTYPE __BITS(28,25)
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#define CACHE_TYPE_HARVARD __BIT(24)
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#define CACHE_TYPE_DSIZE __BITS(23,12)
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#define CACHE_TYPE_ISIZE __BITS(11,0)
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#define CACHE_TYPE_xWAYSIZE __BITS(10,8)
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#define CACHE_TYPE_xASSOC __BIT(6)
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#define CACHE_TYPE_xLINESIZE __BITS(5,0)
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#define L2C_CTL 0x100
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#define L2C_AUXCTL 0x104
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#define L2C_TAGRAM_CTL 0x108
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#define L2C_DATARAM_CTL 0x10c
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#define L2C_EV_CTR_CTL 0x200
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#define L2C_EV_CTR1_CTL 0x204
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#define L2C_EV_CTR0_CTL 0x208
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#define L2C_EV_CTR1 0x20c
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#define L2C_EV_CTR0 0x210
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#define L2C_INT_MASK 0x214
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#define L2C_INT_MASK_STS 0x218
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#define L2C_INT_RAW_STS 0x21c
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#define L2C_INT_CLR 0x220
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#define L2C_CACHE_SYNC 0x730
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#define L2C_INV_PA 0x770
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#define L2C_INV_WAY 0x77c
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#define L2C_CLEAN_PA 0x7b0
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#define L2C_CLEAN_INDEX 0x7b8
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#define L2C_CLEAN_WAY 0x7bc
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#define L2C_CLEAN_INV_PA 0x7f0
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#define L2C_CLEAN_INV_INDEX 0x7f8
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#define L2C_CLEAN_INV_WAY 0x7fc
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#define L2C_D_LOCKDOWN0 0x900
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#define L2C_I_LOCKDOWN0 0x904
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#define L2C_D_LOCKDOWN1 0x908
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#define L2C_I_LOCKDOWN1 0x90c
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#define L2C_D_LOCKDOWN2 0x910
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#define L2C_I_LOCKDOWN2 0x914
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#define L2C_D_LOCKDOWN3 0x918
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#define L2C_I_LOCKDOWN3 0x91c
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#define L2C_D_LOCKDOWN4 0x920
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#define L2C_I_LOCKDOWN4 0x924
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#define L2C_D_LOCKDOWN5 0x928
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#define L2C_I_LOCKDOWN5 0x92c
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#define L2C_D_LOCKDOWN6 0x930
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#define L2C_I_LOCKDOWN6 0x934
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#define L2C_D_LOCKDOWN7 0x938
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#define L2C_I_LOCKDOWN7 0x93c
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#define L2C_LOCK_LINE_EN 0x950
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#define L2C_UNLOCK_WAY 0x954
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#define L2C_ADDR_FILTER_START 0xc00
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#define L2C_ADDR_FILTER_END 0xc04
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#define L2C_DEBUG_CTL 0xf40
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#define L2C_PREFETCH_CTL 0xf60
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#define L2C_POWER_CTL 0xf80
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#endif /* _ARM_CORTEX_PL310_REG_H_ */
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