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Apply patch hpcmips/26158 (requested by darkstar) 

This patch solves install/28656.
This commit is contained in:
hamajima 2005-01-16 03:21:21 +00:00
parent 78ec5c8f06
commit 1daa6c5284
1 changed files with 22 additions and 19 deletions
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41
sys/arch/hpcmips/vr/vr.c
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@ -1,4 +1,4 @@
/* $NetBSD: vr.c,v 1.44 2003/10/25 18:04:34 mycroft Exp $ */
/* $NetBSD: vr.c,v 1.45 2005/01/16 03:21:21 hamajima Exp $ */
/*-
* Copyright (c) 1999-2002
@ -35,7 +35,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: vr.c,v 1.44 2003/10/25 18:04:34 mycroft Exp $");
__KERNEL_RCSID(0, "$NetBSD: vr.c,v 1.45 2005/01/16 03:21:21 hamajima Exp $");
#include "opt_vr41xx.h"
#include "opt_tx39xx.h"
@ -546,33 +546,36 @@ VR_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
{
uvmexp.intrs++;
/* Deal with unneded compare interrupts occasionally so that we can
* keep spllowersoftclock. */
if (ipending & MIPS_INT_MASK_5) {
/*
* spl* uses MIPS_INT_MASK not MIPS3_INT_MASK. it causes
* INT5 interrupt.
*/
mips3_cp0_compare_write(mips3_cp0_count_read());
mips3_cp0_compare_write(0);
}
/* for spllowersoftclock */
_splset(((status & ~cause) & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
if (ipending & MIPS_INT_MASK_1) {
(*vr_intr_handler[1])(vr_intr_arg[1], pc, status);
cause &= ~MIPS_INT_MASK_1;
_splset(((status & ~cause) & MIPS_HARD_INT_MASK)
| MIPS_SR_INT_IE);
_splset(MIPS_SR_INT_IE); /* for spllowersoftclock */
/* Remove the lower priority pending bits from status so that
* spllowersoftclock will not happen if other interrupts are
* pending. */
(*vr_intr_handler[1])(vr_intr_arg[1], pc, status & ~(ipending
& (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)));
}
if (ipending & MIPS_INT_MASK_0) {
_splset(MIPS_INT_MASK_1|MIPS_SR_INT_IE);
(*vr_intr_handler[0])(vr_intr_arg[0], pc, status);
cause &= ~MIPS_INT_MASK_0;
}
_splset(((status & ~cause) & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
softintr(ipending);
if (ipending & MIPS_SOFT_INT_MASK_1) {
_splset(MIPS_INT_MASK_1|MIPS_INT_MASK_0|MIPS_SR_INT_IE);
softintr(MIPS_SOFT_INT_MASK_1);
}
if (ipending & MIPS_SOFT_INT_MASK_0) {
_splset(MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_1|MIPS_INT_MASK_0|
MIPS_SR_INT_IE);
softintr(MIPS_SOFT_INT_MASK_0);
}
}
void *