Make all of the COM_xxx type options runtime selectable. Kernel configs
with the existing options (COM_16650, COM_16750, COM_AWIN, COM_HAYESP, and COM_PXA2X0) will select the correct type in com_attach_subr. New code should specify the com type by passing COM_TYPE_xxx to comcnattach and/or setting sc_type.
This commit is contained in:
jmcneill
parent
2247cb6b7f
commit
1d72c7e24d
230
sys/dev/ic/com.c
230
sys/dev/ic/com.c
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@ -1,4 +1,4 @@
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/* $NetBSD: com.c,v 1.343 2017/10/28 04:53:55 riastradh Exp $ */
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/* $NetBSD: com.c,v 1.344 2017/10/29 14:06:08 jmcneill Exp $ */
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/*-
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* Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc.
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@ -66,7 +66,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: com.c,v 1.343 2017/10/28 04:53:55 riastradh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: com.c,v 1.344 2017/10/29 14:06:08 jmcneill Exp $");
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#include "opt_com.h"
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#include "opt_ddb.h"
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@ -122,9 +122,7 @@ __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.343 2017/10/28 04:53:55 riastradh Exp $");
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#include <dev/ic/comvar.h>
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#include <dev/ic/ns16550reg.h>
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#include <dev/ic/st16650reg.h>
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#ifdef COM_HAYESP
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#include <dev/ic/hayespreg.h>
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#endif
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#define com_lcr com_cfcr
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#include <dev/cons.h>
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@ -252,20 +250,12 @@ void com_kgdb_putc(void *, int);
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#ifdef COM_REGMAP
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/* initializer for typical 16550-ish hardware */
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#define COM_REG_16550 { \
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com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \
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com_efr, com_lcr, com_mcr, com_lsr, com_msr }
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/* 16750-specific register set, additional UART status register */
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#define COM_REG_16750 { \
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#define COM_REG_STD { \
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com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \
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com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr }
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#ifdef COM_16750
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const bus_size_t com_std_map[32] = COM_REG_16750;
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#else
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const bus_size_t com_std_map[16] = COM_REG_16550;
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#endif /* COM_16750 */
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const bus_size_t com_std_map[32] = COM_REG_STD;
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#endif /* COM_REGMAP */
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#define COMDIALOUT_MASK TTDIALOUT_MASK
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@ -393,9 +383,7 @@ com_attach_subr(struct com_softc *sc)
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{
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struct com_regs *regsp = &sc->sc_regs;
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struct tty *tp;
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#if defined(COM_16650) || defined(COM_16750)
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u_int8_t lcr;
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#endif
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const char *fifo_msg = NULL;
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prop_dictionary_t dict;
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bool is_console = true;
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@ -407,6 +395,18 @@ com_attach_subr(struct com_softc *sc)
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callout_init(&sc->sc_diag_callout, 0);
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mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);
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#if defined(COM_16650)
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sc->sc_type = COM_TYPE_16650;
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#elif defined(COM_16750)
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sc->sc_type = COM_TYPE_16750;
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#elif defined(COM_AWIN)
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sc->sc_type = COM_TYPE_SUNXI;
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#elif defined(COM_HAYESP)
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sc->sc_type = COM_TYPE_HAYESP;
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#elif defined(COM_PXA2X0)
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sc->sc_type = COM_TYPE_PXA2x0;
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#endif
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/* Disable interrupts before configuring the device. */
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if (sc->sc_type == COM_TYPE_PXA2x0)
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sc->sc_ier = IER_EUART;
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@ -424,10 +424,13 @@ com_attach_subr(struct com_softc *sc)
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(u_long)comcons_info.regs.cr_iobase);
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}
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#if defined(COM_16750) || defined(COM_AWIN)
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/* Use in comintr(). */
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sc->sc_lcr = cflag2lcr(comcons_info.cflag);
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#endif
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switch (sc->sc_type) {
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case COM_TYPE_16750:
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case COM_TYPE_SUNXI:
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/* Use in comintr(). */
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sc->sc_lcr = cflag2lcr(comcons_info.cflag);
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break;
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}
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/* Make sure the console is always "hardwired". */
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delay(10000); /* wait for output to finish */
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@ -501,7 +504,8 @@ com_attach_subr(struct com_softc *sc)
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== FIFO_TRIGGER_14) {
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SET(sc->sc_hwflags, COM_HW_FIFO);
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#ifdef COM_16650
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fifo_msg = "ns16550a, working fifo";
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/*
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* IIR changes into the EFR if LCR is set to LCR_EERS
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* on 16650s. We also know IIR != 0 at this point.
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@ -513,23 +517,32 @@ com_attach_subr(struct com_softc *sc)
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* setting DLAB enable gives access to the EFR on
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* these chips.
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*/
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lcr = CSR_READ_1(regsp, COM_REG_LCR);
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CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
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CSR_WRITE_1(regsp, COM_REG_EFR, 0);
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if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
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CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
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if (sc->sc_type == COM_TYPE_16650) {
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lcr = CSR_READ_1(regsp, COM_REG_LCR);
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CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
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CSR_WRITE_1(regsp, COM_REG_EFR, 0);
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if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
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CLR(sc->sc_hwflags, COM_HW_FIFO);
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sc->sc_fifolen = 0;
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} else {
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SET(sc->sc_hwflags, COM_HW_FLOW);
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sc->sc_fifolen = 32;
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}
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} else
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#endif
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sc->sc_fifolen = 16;
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CSR_WRITE_1(regsp, COM_REG_LCR,
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lcr | LCR_DLAB);
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if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
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CLR(sc->sc_hwflags, COM_HW_FIFO);
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sc->sc_fifolen = 0;
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} else {
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SET(sc->sc_hwflags, COM_HW_FLOW);
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sc->sc_fifolen = 32;
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}
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} else
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sc->sc_fifolen = 16;
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CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
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if (sc->sc_fifolen == 0)
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fifo_msg = "st16650, broken fifo";
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else if (sc->sc_fifolen == 32)
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fifo_msg = "st16650a, working fifo";
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else
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fifo_msg = "ns16550a, working fifo";
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}
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#ifdef COM_16750
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/*
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* TL16C750 can enable 64byte FIFO, only when DLAB
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* is 1. However, some 16750 may always enable. For
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@ -539,54 +552,43 @@ com_attach_subr(struct com_softc *sc)
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* use SC16C750. Probably 32 bytes of FIFO and HW FLOW
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* should become effective.
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*/
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uint8_t iir1, iir2;
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uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14;
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if (sc->sc_type == COM_TYPE_16750) {
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uint8_t iir1, iir2;
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uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14;
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if (sc->sc_type == COM_TYPE_INGENIC)
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fcr |= FIFO_UART_ON;
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lcr = CSR_READ_1(regsp, COM_REG_LCR);
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CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB);
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CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE);
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iir1 = CSR_READ_1(regsp, COM_REG_IIR);
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CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
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CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
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CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE);
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iir2 = CSR_READ_1(regsp, COM_REG_IIR);
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CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
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if (!ISSET(iir1, IIR_64B_FIFO) &&
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ISSET(iir2, IIR_64B_FIFO)) {
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/* It is TL16C750. */
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sc->sc_fifolen = 64;
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SET(sc->sc_hwflags, COM_HW_AFE);
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} else
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lcr = CSR_READ_1(regsp, COM_REG_LCR);
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CSR_WRITE_1(regsp, COM_REG_LCR,
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lcr & ~LCR_DLAB);
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CSR_WRITE_1(regsp, COM_REG_FIFO,
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fcr | FIFO_64B_ENABLE);
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iir1 = CSR_READ_1(regsp, COM_REG_IIR);
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CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
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#endif
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CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
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CSR_WRITE_1(regsp, COM_REG_FIFO,
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fcr | FIFO_64B_ENABLE);
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iir2 = CSR_READ_1(regsp, COM_REG_IIR);
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#ifdef COM_16650
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CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
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if (sc->sc_fifolen == 0)
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fifo_msg = "st16650, broken fifo";
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else if (sc->sc_fifolen == 32)
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fifo_msg = "st16650a, working fifo";
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else
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#endif
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#ifdef COM_16750
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if (sc->sc_fifolen == 64)
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fifo_msg = "tl16c750, working fifo";
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else
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#endif
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fifo_msg = "ns16550a, working fifo";
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CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
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if (!ISSET(iir1, IIR_64B_FIFO) &&
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ISSET(iir2, IIR_64B_FIFO)) {
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/* It is TL16C750. */
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sc->sc_fifolen = 64;
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SET(sc->sc_hwflags, COM_HW_AFE);
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} else
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CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
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if (sc->sc_fifolen == 64)
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fifo_msg = "tl16c750, working fifo";
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else
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fifo_msg = "ns16750, working fifo";
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}
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} else
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fifo_msg = "ns16550, broken fifo";
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else
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fifo_msg = "ns8250 or ns16450, no fifo";
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if (sc->sc_type == COM_TYPE_INGENIC) {
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CSR_WRITE_1(regsp, COM_REG_FIFO, FIFO_UART_ON);
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} else
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CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
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CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
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fifodelay:
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/*
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* Some chips will clear down both Tx and Rx FIFOs when zero is
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@ -685,7 +687,6 @@ com_config(struct com_softc *sc)
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CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
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(void) CSR_READ_1(regsp, COM_REG_IIR);
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#ifdef COM_HAYESP
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/* Look for a Hayes ESP board. */
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if (sc->sc_type == COM_TYPE_HAYESP) {
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@ -716,7 +717,6 @@ com_config(struct com_softc *sc)
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bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
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HAYESP_LOBYTE(HAYESP_RXLOWMARK));
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}
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#endif
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if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB))
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com_enable_debugport(sc);
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@ -1360,7 +1360,6 @@ comparam(struct tty *tp, struct termios *t)
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if (COM_ISALIVE(sc) == 0)
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return (EIO);
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#ifdef COM_HAYESP
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if (sc->sc_type == COM_TYPE_HAYESP) {
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int prescaler, speed;
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@ -1378,8 +1377,7 @@ comparam(struct tty *tp, struct termios *t)
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return (EINVAL);
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sc->sc_prescaler = prescaler;
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} else
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#endif
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ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type);
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ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type);
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/* Check requested parameters. */
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if (ospeed < 0)
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@ -1565,6 +1563,7 @@ void
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com_iflush(struct com_softc *sc)
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{
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struct com_regs *regsp = &sc->sc_regs;
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uint8_t fifo;
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#ifdef DIAGNOSTIC
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int reg;
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#endif
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@ -1588,19 +1587,21 @@ com_iflush(struct com_softc *sc)
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aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg);
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#endif
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#if defined(COM_16750) || defined(COM_AWIN)
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uint8_t fifo;
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/*
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* Reset all Rx/Tx FIFO, preserve current FIFO length.
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* This should prevent triggering busy interrupt while
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* manipulating divisors.
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*/
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fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 |
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FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14);
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CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST |
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FIFO_XMT_RST);
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delay(100);
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#endif
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switch (sc->sc_type) {
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case COM_TYPE_16750:
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case COM_TYPE_SUNXI:
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/*
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* Reset all Rx/Tx FIFO, preserve current FIFO length.
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* This should prevent triggering busy interrupt while
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* manipulating divisors.
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*/
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fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 |
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FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14);
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CSR_WRITE_1(regsp, COM_REG_FIFO,
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fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST);
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delay(100);
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break;
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}
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}
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void
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@ -1640,14 +1641,12 @@ com_loadchannelregs(struct com_softc *sc)
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CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
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CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr);
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CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo);
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#ifdef COM_HAYESP
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if (sc->sc_type == COM_TYPE_HAYESP) {
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bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
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HAYESP_SETPRESCALER);
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bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
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sc->sc_prescaler);
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}
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#endif
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if (sc->sc_type == COM_TYPE_OMAP) {
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/* setup the fifos. the FCR value is not used as long
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as SCR[6] and SCR[7] are 0, which they are at reset
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@ -1922,10 +1921,8 @@ com_rxsoft(struct com_softc *sc, struct tty *tp)
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if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
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CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
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SET(sc->sc_ier, IER_ERXRDY);
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#ifdef COM_PXA2X0
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if (sc->sc_type == COM_TYPE_PXA2x0)
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SET(sc->sc_ier, IER_ERXTOUT);
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#endif
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if (sc->sc_type == COM_TYPE_INGENIC ||
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sc->sc_type == COM_TYPE_TEGRA)
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SET(sc->sc_ier, IER_ERXTOUT);
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@ -2034,13 +2031,9 @@ comintr(void *arg)
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iir = CSR_READ_1(regsp, COM_REG_IIR);
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/* Handle ns16750-specific busy interrupt. */
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#ifdef COM_16750
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#ifdef COM_AWIN
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#error "COM_16750 and COM_AWIN are exclusive"
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#endif
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int timeout;
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if ((iir & IIR_BUSY) == IIR_BUSY) {
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for (timeout = 10000;
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if (sc->sc_type == COM_TYPE_16750 &&
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(iir & IIR_BUSY) == IIR_BUSY) {
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for (int timeout = 10000;
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(CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--)
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if (timeout <= 0) {
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aprint_error_dev(sc->sc_dev,
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@ -2053,10 +2046,10 @@ comintr(void *arg)
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CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
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iir = CSR_READ_1(regsp, COM_REG_IIR);
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}
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#endif /* COM_16750 */
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#ifdef COM_AWIN
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/* Allwinner BUSY interrupt */
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if ((iir & IIR_BUSY) == IIR_BUSY) {
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if (sc->sc_type == COM_TYPE_SUNXI &&
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(iir & IIR_BUSY) == IIR_BUSY) {
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if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) {
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CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN);
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CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
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|
@ -2086,7 +2079,6 @@ comintr(void *arg)
|
|||
CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
|
||||
}
|
||||
}
|
||||
#endif /* COM_AWIN */
|
||||
|
||||
if (ISSET(iir, IIR_NOPEND)) {
|
||||
mutex_spin_exit(&sc->sc_lock);
|
||||
|
|
@ -2166,17 +2158,19 @@ again: do {
|
|||
*/
|
||||
if (!cc) {
|
||||
SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
|
||||
#ifdef COM_PXA2X0
|
||||
if (sc->sc_type == COM_TYPE_PXA2x0)
|
||||
switch (sc->sc_type) {
|
||||
case COM_TYPE_PXA2x0:
|
||||
CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT);
|
||||
else
|
||||
#endif
|
||||
if (sc->sc_type == COM_TYPE_INGENIC ||
|
||||
sc->sc_type == COM_TYPE_TEGRA)
|
||||
break;
|
||||
case COM_TYPE_INGENIC:
|
||||
case COM_TYPE_TEGRA:
|
||||
CLR(sc->sc_ier,
|
||||
IER_ERXRDY | IER_ERXTOUT);
|
||||
else
|
||||
break;
|
||||
default:
|
||||
CLR(sc->sc_ier, IER_ERXRDY);
|
||||
break;
|
||||
}
|
||||
CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
|
||||
}
|
||||
} else {
|
||||
|
|
@ -2444,11 +2438,9 @@ cominit(struct com_regs *regsp, int rate, int frequency, int type,
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef COM_PXA2X0
|
||||
if (type == COM_TYPE_PXA2x0)
|
||||
CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
|
||||
else
|
||||
#endif
|
||||
CSR_WRITE_1(regsp, COM_REG_IER, 0);
|
||||
|
||||
return (0);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: comreg.h,v 1.25 2016/05/27 20:01:49 bouyer Exp $ */
|
||||
/* $NetBSD: comreg.h,v 1.26 2017/10/29 14:06:08 jmcneill Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1991 The Regents of the University of California.
|
||||
|
|
@ -64,9 +64,7 @@
|
|||
#define IIR_NOPEND 0x1 /* No pending interrupts */
|
||||
#define IIR_64B_FIFO 0x20 /* 64byte FIFO Enabled (16750) */
|
||||
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
|
||||
#if defined(COM_16750) || defined(COM_AWIN)
|
||||
#define IIR_BUSY 0x7 /* Busy indicator */
|
||||
#endif
|
||||
#define IIR_BUSY 0x7 /* Busy indicator (16750/SUNXI) */
|
||||
|
||||
/* fifo control register */
|
||||
#define FIFO_ENABLE 0x01 /* Turn the FIFO on */
|
||||
|
|
@ -160,11 +158,9 @@
|
|||
#define MDR1_MODE_UART_16X 0x00
|
||||
#define MDR1_MODE_MASK 0x07
|
||||
|
||||
#ifdef COM_AWIN
|
||||
/* AWIN-specific registers */
|
||||
/* SUNXI-specific registers */
|
||||
#define HALT_CHCFG_UD 0x04 /* apply updates to LCR/dividors */
|
||||
#define HALT_CHCFG_EN 0x02 /* enable change while busy */
|
||||
#endif
|
||||
|
||||
|
||||
/* XXX ISA-specific. */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: comvar.h,v 1.83 2017/07/31 09:25:14 jmcneill Exp $ */
|
||||
/* $NetBSD: comvar.h,v 1.84 2017/10/29 14:06:08 jmcneill Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
|
||||
|
|
@ -91,33 +91,20 @@ int com_is_console(bus_space_tag_t, bus_addr_t, bus_space_handle_t *);
|
|||
#define COM_REG_MCR 9
|
||||
#define COM_REG_LSR 10
|
||||
#define COM_REG_MSR 11
|
||||
#ifdef COM_16750
|
||||
#define COM_REG_USR 31
|
||||
#endif
|
||||
#ifdef COM_AWIN
|
||||
#define COM_REG_USR 31
|
||||
#define COM_REG_TFL 32
|
||||
#define COM_REG_RFL 33
|
||||
#define COM_REG_HALT 41
|
||||
#endif
|
||||
#define COM_REG_USR 31 /* 16750/SUNXI */
|
||||
#define COM_REG_TFL 32 /* SUNXI */
|
||||
#define COM_REG_RFL 33 /* SUNXI */
|
||||
#define COM_REG_HALT 41 /* SUNXI */
|
||||
|
||||
struct com_regs {
|
||||
bus_space_tag_t cr_iot;
|
||||
bus_space_handle_t cr_ioh;
|
||||
bus_addr_t cr_iobase;
|
||||
bus_size_t cr_nports;
|
||||
#ifdef COM_16750
|
||||
bus_size_t cr_map[32];
|
||||
#else
|
||||
bus_size_t cr_map[16];
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef COM_16750
|
||||
extern const bus_size_t com_std_map[32];
|
||||
#else
|
||||
extern const bus_size_t com_std_map[16];
|
||||
#endif
|
||||
|
||||
#define COM_INIT_REGS(regs, tag, hdl, addr) \
|
||||
do { \
|
||||
|
|
@ -144,15 +131,10 @@ extern const bus_size_t com_std_map[16];
|
|||
#define COM_REG_TCR com_msr
|
||||
#define COM_REG_TLR com_scratch
|
||||
#define COM_REG_MDR1 8
|
||||
#ifdef COM_16750
|
||||
#define COM_REG_USR com_usr
|
||||
#endif
|
||||
#ifdef COM_AWIN
|
||||
#define COM_REG_USR com_usr
|
||||
#define COM_REG_TFL com_tfl
|
||||
#define COM_REG_RFL com_rfl
|
||||
#define COM_REG_HALT com_halt
|
||||
#endif
|
||||
#define COM_REG_USR com_usr /* 16750/SUNXI */
|
||||
#define COM_REG_TFL com_tfl /* SUNXI */
|
||||
#define COM_REG_RFL com_rfl /* SUNXI */
|
||||
#define COM_REG_HALT com_halt /* SUNXI */
|
||||
|
||||
struct com_regs {
|
||||
bus_space_tag_t cr_iot;
|
||||
|
|
@ -229,9 +211,7 @@ struct com_softc {
|
|||
sc_mcr_active, sc_lcr, sc_ier, sc_fifo, sc_dlbl, sc_dlbh, sc_efr;
|
||||
u_char sc_mcr_dtr, sc_mcr_rts, sc_msr_cts, sc_msr_dcd;
|
||||
|
||||
#ifdef COM_HAYESP
|
||||
u_char sc_prescaler;
|
||||
#endif
|
||||
u_char sc_prescaler; /* for COM_TYPE_HAYESP */
|
||||
|
||||
/*
|
||||
* There are a great many almost-ns16550-compatible UARTs out
|
||||
|
|
@ -248,6 +228,9 @@ struct com_softc {
|
|||
#define COM_TYPE_INGENIC 6 /* JZ4780 built-in */
|
||||
#define COM_TYPE_TEGRA 7 /* NVIDIA Tegra built-in */
|
||||
#define COM_TYPE_BCMAUXUART 8 /* BCM2835 AUX UART */
|
||||
#define COM_TYPE_16650 9
|
||||
#define COM_TYPE_16750 10
|
||||
#define COM_TYPE_SUNXI 11 /* Allwinner built-in */
|
||||
|
||||
/* power management hooks */
|
||||
int (*enable)(struct com_softc *);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: ns16550reg.h,v 1.11 2016/05/27 20:01:49 bouyer Exp $ */
|
||||
/* $NetBSD: ns16550reg.h,v 1.12 2017/10/29 14:06:08 jmcneill Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1991 The Regents of the University of California.
|
||||
|
|
@ -51,12 +51,11 @@
|
|||
/*
|
||||
* Additional register present in NS16750
|
||||
*/
|
||||
#ifdef COM_16750
|
||||
#define com_usr 31 /* status register (R) */
|
||||
#endif
|
||||
#ifdef COM_AWIN
|
||||
#define com_usr 31 /* status register (R) */
|
||||
#define com_tfl 32 /* transmit fifo level (R) */
|
||||
#define com_rfl 33 /* receive fifo level (R) */
|
||||
#define com_halt 41 /* halt tx (R/W) */
|
||||
#endif
|
||||
#define com_usr 31 /* status register (R) (16750/SUNXI) */
|
||||
|
||||
/*
|
||||
* Additional registers present on Allwinner hardware
|
||||
*/
|
||||
#define com_tfl 32 /* transmit fifo level (R) (SUNXI) */
|
||||
#define com_rfl 33 /* receive fifo level (R) (SUNXI) */
|
||||
#define com_halt 41 /* halt tx (R/W) (SUNXI) */
|
||||
|
|
|
|||
Loading…
Reference in New Issue