First cut at implementing software single stepping for sh3. We need
it because sh3 ports don't provide PT_STEP. It is finally possible to run programs under gdb now, though there are still issues to be resolved. It was deemed useful enough to commit early, while the work is still in progress. Tested on hpcsh. Blessed by christos@.
This commit is contained in:
uwe
parent
9356ead951
commit
1d729d7bc4
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@ -25,4 +25,9 @@
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#include "sh/tm-sh.h"
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#include "solib.h"
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#define SOFTWARE_SINGLE_STEP_P() 1
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extern void shnbsd_software_single_step (enum target_signal, int);
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#define SOFTWARE_SINGLE_STEP(sig,bp_p) shnbsd_software_single_step (sig,bp_p)
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#endif /* TM_NBSD_H */
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@ -21,6 +21,7 @@
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#include "defs.h"
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#include "gdbcore.h"
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#include "inferior.h"
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#include "regcache.h"
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#include "value.h"
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@ -172,12 +173,197 @@ shnbsd_pc_in_sigtramp (CORE_ADDR pc, char *func_name)
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return (nbsd_pc_in_sigtramp (pc, func_name));
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}
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/* Hitachi SH instruction encoding masks and opcodes */
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/*
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* xxxx x--x ---- ---- 0xf900 mask
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* 1001 1**1 ---- ---- 0x8900 match
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* BT 1000 1001 dddd dddd
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* BF 1000 1011 dddd dddd
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* BT/S 1000 1101 dddd dddd
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* BF/S 1000 1111 dddd dddd
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* ---- --x- ---- ---- T or F?
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* ---- -x-- ---- ---- has delay slot
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*/
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#define CONDITIONAL_BRANCH_P(insn) (((insn) & 0xf900) == 0x8900)
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#define CONDITIONAL_BRANCH_TAKEN_P(insn, sr) ((((insn) >> 9) ^ sr) & 0x1)
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#define CONDITIONAL_BRANCH_SLOT_P(insn) (((insn) & 0x0400) != 0)
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/*
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* xxx- ---- ---- ---- 0xe000 mask
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* 101* ---- ---- ---- 0xa000 match
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* BRA 1010 dddd dddd dddd
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* BSR 1011 dddd dddd dddd
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*/
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#define BRANCH_P(insn) (((insn) & 0xe000) == 0xa000)
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/*
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* xxxx ---- xx-x xxxx 0xf0df mask
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* 0000 ---- 00*0 0011 0x0003 match
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* BSRF 0000 rrrr 0000 0011
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* BRAF 0000 rrrr 0010 0011
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*/
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#define BRANCH_FAR_P(insn) (((insn) & 0xf0df) == 0x0003)
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#define BRANCH_FAR_REG(insn) (((insn) >> 8) & 0xf)
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/*
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* xxxx ---- xx-x xxxx 0xf0df mask
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* 0100 ---- 00*0 1011 0x400b match
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* JSR 0100 rrrr 0000 1011
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* JMP 0100 rrrr 0010 1011
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*/
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#define JUMP_P(insn) (((insn) & 0xf0df) == 0x400b)
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#define JUMP_REG(insn) (((insn) >> 8) & 0xf)
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/*
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* RTS 0000 0000 0000 1011
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* RTE 0000 0000 0010 1011
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*/
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#define RTS_INSN 0x000b
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#define RTE_INSN 0x002b
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/*
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* xxxx xxxx ---- ---- 0xff00 mask
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*TRAPA 1100 0011 tttt tttt 0xc300 match
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*/
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#define TRAPA_P(insn) (((insn) & 0xff00) == 0xc300)
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/* signed 8-bit displacement */
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static int
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shnbsd_displacement_8 (unsigned short insn)
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{
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int displacement;
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if (insn & 0x80)
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displacement = insn | 0xffffff00;
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else
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displacement = insn & 0x000000ff;
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return displacement;
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}
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/* signed 12-bit displacement */
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static int
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shnbsd_displacement_12 (unsigned short insn)
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{
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int displacement;
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if (insn & 0x800)
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displacement = insn | 0xfffff000;
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else
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displacement = insn & 0x00000fff;
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return displacement;
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}
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static CORE_ADDR
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shnbsd_get_next_pc (CORE_ADDR pc)
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{
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unsigned short insn;
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ULONGEST sr;
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int displacement;
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int reg;
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CORE_ADDR next_pc;
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insn = read_memory_integer (pc, sizeof (insn));
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/* BT, BF, BT/S, BF/S */
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if (CONDITIONAL_BRANCH_P(insn))
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{
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sr = read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM);
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if (!CONDITIONAL_BRANCH_TAKEN_P(insn, sr))
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next_pc = pc + 2;
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else
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{
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displacement = shnbsd_displacement_8 (insn);
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/* XXX: cannot step through delay slot, so break at the target */
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next_pc = pc + 4 + (displacement << 1);
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}
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}
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/* BRA, BSR */
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else if (BRANCH_P(insn))
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{
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displacement = shnbsd_displacement_12 (insn);
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/* XXX: cannot step through delay slot, so break at the target */
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next_pc = pc + 4 + (displacement << 1);
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}
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/* BRAF, BSRF */
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else if (BRANCH_FAR_P(insn))
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{
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displacement = read_register (BRANCH_FAR_REG(insn));
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/* XXX: cannot step through delay slot, so break at the target */
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next_pc = pc + displacement;
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}
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/* JMP, JSR */
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else if (JUMP_P(insn))
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{
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/* XXX: cannot step through delay slot, so break at the target */
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next_pc = read_register (JUMP_REG(insn));
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}
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/* RTS */
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else if (insn == RTS_INSN)
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next_pc = read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM);
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/* RTE - XXX: privileged */
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else if (insn == RTE_INSN)
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next_pc = read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM);
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/* TRAPA */
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else if (TRAPA_P(insn))
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next_pc = pc + 2; /* XXX: after return from syscall */
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/* not a control transfer instruction */
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else
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next_pc = pc + 2;
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return next_pc;
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}
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/* Single step (in a painstaking fashion) by inspecting the current
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instruction and setting a breakpoint on the "next" instruction
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which would be executed.
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*/
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void
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shnbsd_software_single_step (enum target_signal ignore,
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int insert_breakpoints_p)
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{
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static CORE_ADDR next_pc;
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typedef char binsn_quantum[BREAKPOINT_MAX];
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static binsn_quantum break_mem;
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CORE_ADDR pc;
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if (insert_breakpoints_p)
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{
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pc = read_pc ();
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next_pc = shnbsd_get_next_pc (pc);
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target_insert_breakpoint (next_pc, break_mem);
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}
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else
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{
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target_remove_breakpoint (next_pc, break_mem);
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write_pc (next_pc);
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}
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}
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static void
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shnbsd_init_abi (struct gdbarch_info info,
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struct gdbarch *gdbarch)
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{
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set_gdbarch_pc_in_sigtramp (gdbarch, shnbsd_pc_in_sigtramp);
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/* NetBSD SuperH ports do not provide single step support via ptrace(2);
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we must use software single-stepping. */
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set_gdbarch_software_single_step (gdbarch, shnbsd_software_single_step);
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set_solib_svr4_fetch_link_map_offsets (gdbarch,
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nbsd_ilp32_solib_svr4_fetch_link_map_offsets);
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}
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@ -25,4 +25,9 @@
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#include "sh/tm-sh.h"
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#include "solib.h"
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#define SOFTWARE_SINGLE_STEP_P() 1
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extern void shnbsd_software_single_step (enum target_signal, int);
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#define SOFTWARE_SINGLE_STEP(sig,bp_p) shnbsd_software_single_step (sig,bp_p)
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#endif /* TM_NBSD_H */
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@ -25,4 +25,9 @@
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#include "sh/tm-sh.h"
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#include "solib.h"
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#define SOFTWARE_SINGLE_STEP_P() 1
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extern void shnbsd_software_single_step (enum target_signal, int);
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#define SOFTWARE_SINGLE_STEP(sig,bp_p) shnbsd_software_single_step (sig,bp_p)
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#endif /* TM_NBSD_H */
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