Merge from vmlocking: fix many timing problems on mips.
This commit is contained in:
ad
parent
be0770a433
commit
1d7050e5e2
199
sys/dev/dec/dz.c
199
sys/dev/dec/dz.c
@ -1,4 +1,4 @@
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/* $NetBSD: dz.c,v 1.28 2007/07/14 19:20:20 ad Exp $ */
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/* $NetBSD: dz.c,v 1.29 2007/10/08 16:52:49 ad Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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@ -67,7 +67,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: dz.c,v 1.28 2007/07/14 19:20:20 ad Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dz.c,v 1.29 2007/10/08 16:52:49 ad Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -91,18 +91,55 @@ __KERNEL_RCSID(0, "$NetBSD: dz.c,v 1.28 2007/07/14 19:20:20 ad Exp $");
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#include <dev/cons.h>
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#define DZ_READ_BYTE(adr) \
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bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->sc_dr.adr)
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#define DZ_READ_WORD(adr) \
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bus_space_read_2(sc->sc_iot, sc->sc_ioh, sc->sc_dr.adr)
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#define DZ_WRITE_BYTE(adr, val) \
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->sc_dr.adr, val)
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#define DZ_WRITE_WORD(adr, val) \
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, sc->sc_dr.adr, val)
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#define DZ_BARRIER() \
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bus_space_barrier(sc->sc_iot, sc->sc_ioh, sc->sc_dr.dr_firstreg, \
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sc->sc_dr.dr_winsize, \
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BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ)
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#ifdef __mips__
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#define DZ_DELAY(x) DELAY(x)
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#define control __attribute ((noinline))
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#else /* presumably vax */
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#define DZ_DELAY(x) /* nothing */
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#define control inline
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#endif
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static control uint
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dz_read1(struct dz_softc *sc, u_int off)
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{
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u_int rv;
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rv = bus_space_read_1(sc->sc_iot, sc->sc_ioh, off);
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DZ_DELAY(1);
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return rv;
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}
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static control u_int
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dz_read2(struct dz_softc *sc, u_int off)
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{
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u_int rv;
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rv = bus_space_read_2(sc->sc_iot, sc->sc_ioh, off);
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DZ_DELAY(1);
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return rv;
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}
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static control void
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dz_write1(struct dz_softc *sc, u_int off, u_int val)
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{
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, val);
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bus_space_barrier(sc->sc_iot, sc->sc_ioh, sc->sc_dr.dr_firstreg,
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sc->sc_dr.dr_winsize, BUS_SPACE_BARRIER_WRITE |
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BUS_SPACE_BARRIER_READ);
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DZ_DELAY(10);
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}
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static control void
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dz_write2(struct dz_softc *sc, u_int off, u_int val)
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{
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, val);
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bus_space_barrier(sc->sc_iot, sc->sc_ioh, sc->sc_dr.dr_firstreg,
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sc->sc_dr.dr_winsize, BUS_SPACE_BARRIER_WRITE |
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BUS_SPACE_BARRIER_READ);
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DZ_DELAY(10);
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}
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#include "ioconf.h"
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@ -171,11 +208,10 @@ dzattach(struct dz_softc *sc, struct evcnt *parent_evcnt, int consline)
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sc->sc_consline = consline;
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sc->sc_dr.dr_tcrw = sc->sc_dr.dr_tcr;
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DZ_WRITE_WORD(dr_csr, DZ_CSR_MSE | DZ_CSR_RXIE | DZ_CSR_TXIE);
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DZ_WRITE_BYTE(dr_dtr, 0);
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DZ_WRITE_BYTE(dr_break, 0);
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DZ_BARRIER();
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DELAY(50000);
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dz_write2(sc, sc->sc_dr.dr_csr, DZ_CSR_MSE | DZ_CSR_RXIE | DZ_CSR_TXIE);
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dz_write1(sc, sc->sc_dr.dr_dtr, 0);
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dz_write1(sc, sc->sc_dr.dr_break, 0);
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DELAY(10000);
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/* Initialize our softc structure. Should be done in open? */
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@ -186,9 +222,9 @@ dzattach(struct dz_softc *sc, struct evcnt *parent_evcnt, int consline)
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}
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evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, parent_evcnt,
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sc->sc_dev.dv_xname, "rintr");
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sc->sc_dev.dv_xname, "rintr");
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evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, parent_evcnt,
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sc->sc_dev.dv_xname, "tintr");
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sc->sc_dev.dv_xname, "tintr");
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/* Console magic keys */
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cn_init_magic(&dz_cnm_state);
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@ -196,7 +232,6 @@ dzattach(struct dz_softc *sc, struct evcnt *parent_evcnt, int consline)
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/* VAX will change it in MD code */
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/* Alas no interrupt on modem bit changes, so we manually scan */
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if (dz_timer == 0) {
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dz_timer = 1;
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callout_init(&dzscan_ch, 0);
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@ -218,7 +253,7 @@ dzrint(void *arg)
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sc->sc_rxint++;
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while ((c = DZ_READ_WORD(dr_rbuf)) & DZ_RBUF_DATA_VALID) {
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while ((c = dz_read2(sc, sc->sc_dr.dr_rbuf)) & DZ_RBUF_DATA_VALID) {
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cc = c & 0xFF;
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line = DZ_PORT(c>>8);
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tp = sc->sc_dz[line].dz_tty;
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@ -284,10 +319,12 @@ dzxint(void *arg)
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* Remove the pdma stuff; no great need of it right now.
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*/
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while (((csr = DZ_READ_WORD(dr_csr)) & DZ_CSR_TX_READY) != 0) {
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line = DZ_PORT(csr>>8);
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for (;;) {
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csr = dz_read2(sc, sc->sc_dr.dr_csr);
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if ((csr & DZ_CSR_TX_READY) == 0)
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break;
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line = DZ_PORT(csr >> 8);
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tp = sc->sc_dz[line].dz_tty;
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cl = &tp->t_outq;
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tp->t_state &= ~TS_BUSY;
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@ -297,17 +334,16 @@ dzxint(void *arg)
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if (cl->c_cc) {
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tp->t_state |= TS_BUSY;
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ch = getc(cl);
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DZ_WRITE_BYTE(dr_tbuf, ch);
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DZ_BARRIER();
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dz_write1(sc, sc->sc_dr.dr_tbuf, ch);
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continue;
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}
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/* Nothing to send; clear the scan bit */
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/* Clear xmit scanner bit; dzstart may set it again */
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tcr = DZ_READ_WORD(dr_tcrw);
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tcr = dz_read2(sc, sc->sc_dr.dr_tcrw);
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tcr &= 255;
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tcr &= ~(1 << line);
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DZ_WRITE_BYTE(dr_tcr, tcr);
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DZ_BARRIER();
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dz_write1(sc, sc->sc_dr.dr_tcr, tcr);
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if (sc->sc_dz[line].dz_catch)
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continue;
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@ -326,7 +362,8 @@ dzopen(dev_t dev, int flag, int mode, struct lwp *l)
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struct tty *tp;
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int unit, line;
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struct dz_softc *sc;
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int s, error = 0;
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int error = 0;
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int s;
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unit = DZ_I2C(minor(dev));
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line = DZ_PORT(minor(dev));
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@ -364,6 +401,7 @@ dzopen(dev_t dev, int flag, int mode, struct lwp *l)
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(void) dzparam(tp, &tp->t_termios);
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ttsetwater(tp);
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}
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/* Use DMBIS and *not* DMSET or else we clobber incoming bits */
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if (dzmctl(sc, line, DML_DTR, DMBIS) & DML_DCD)
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tp->t_state |= TS_CARR_ON;
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@ -426,11 +464,11 @@ int
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dzwrite(dev_t dev, struct uio *uio, int flag)
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{
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struct tty *tp;
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struct dz_softc *sc;
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struct dz_softc *sc;
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sc = dz_cd.cd_devs[DZ_I2C(minor(dev))];
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tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty;
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return ((*tp->t_linesw->l_write)(tp, uio, flag));
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}
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@ -441,11 +479,11 @@ dzpoll(dev, events, l)
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struct lwp *l;
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{
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struct tty *tp;
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struct dz_softc *sc;
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struct dz_softc *sc;
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sc = dz_cd.cd_devs[DZ_I2C(minor(dev))];
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tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty;
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return ((*tp->t_linesw->l_poll)(tp, events, l));
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}
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@ -472,7 +510,6 @@ dzioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
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return (error);
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switch (cmd) {
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case TIOCSBRK:
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(void) dzmctl(sc, line, DML_BRK, DMBIS);
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break;
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@ -514,8 +551,11 @@ dzioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
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struct tty *
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dztty(dev_t dev)
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{
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struct dz_softc *sc = dz_cd.cd_devs[DZ_I2C(minor(dev))];
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struct tty *tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty;
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struct dz_softc *sc;
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struct tty *tp;
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sc = dz_cd.cd_devs[DZ_I2C(minor(dev))];
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tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty;
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return (tp);
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}
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@ -524,9 +564,9 @@ dztty(dev_t dev)
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void
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dzstop(struct tty *tp, int flag)
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{
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if (tp->t_state & TS_BUSY)
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if (!(tp->t_state & TS_TTSTOP))
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tp->t_state |= TS_FLUSH;
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if ((tp->t_state & (TS_BUSY | TS_TTSTOP)) == TS_BUSY)
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tp->t_state |= TS_FLUSH;
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}
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void
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@ -561,11 +601,9 @@ dzstart(struct tty *tp)
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tp->t_state |= TS_BUSY;
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state = DZ_READ_WORD(dr_tcrw) & 255;
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if ((state & (1 << line)) == 0) {
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DZ_WRITE_BYTE(dr_tcr, state | (1 << line));
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DZ_BARRIER();
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}
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state = dz_read2(sc, sc->sc_dr.dr_tcrw) & 255;
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if ((state & (1 << line)) == 0)
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dz_write1(sc, sc->sc_dr.dr_tcr, state | (1 << line));
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dzxint(sc);
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splx(s);
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}
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@ -627,8 +665,7 @@ dzparam(struct tty *tp, struct termios *t)
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if (cflag & CSTOPB)
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lpr |= DZ_LPR_2_STOP;
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DZ_WRITE_WORD(dr_lpr, lpr);
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DZ_BARRIER();
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dz_write2(sc, sc->sc_dr.dr_lpr, lpr);
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(void) splx(s);
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DELAY(10000);
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@ -644,30 +681,21 @@ dzmctl(struct dz_softc *sc, int line, int bits, int how)
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int s;
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s = spltty();
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mbits = 0;
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bit = (1 << line);
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/* external signals as seen from the port */
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status = DZ_READ_BYTE(dr_dcd) | sc->sc_dsr;
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status = dz_read1(sc, sc->sc_dr.dr_dcd) | sc->sc_dsr;
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if (status & bit)
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mbits |= DML_DCD;
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status = DZ_READ_BYTE(dr_ring);
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status = dz_read1(sc, sc->sc_dr.dr_ring);
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if (status & bit)
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mbits |= DML_RI;
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/* internal signals/state delivered to port */
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status = DZ_READ_BYTE(dr_dtr);
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status = dz_read1(sc, sc->sc_dr.dr_dtr);
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if (status & bit)
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mbits |= DML_DTR;
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if (sc->sc_brk & bit)
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mbits |= DML_BRK;
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@ -691,22 +719,19 @@ dzmctl(struct dz_softc *sc, int line, int bits, int how)
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}
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if (mbits & DML_DTR) {
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DZ_WRITE_BYTE(dr_dtr, DZ_READ_BYTE(dr_dtr) | bit);
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dz_write1(sc, sc->sc_dr.dr_dtr, dz_read1(sc, sc->sc_dr.dr_dtr) | bit);
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} else {
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DZ_WRITE_BYTE(dr_dtr, DZ_READ_BYTE(dr_dtr) & ~bit);
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dz_write1(sc, sc->sc_dr.dr_dtr, dz_read1(sc, sc->sc_dr.dr_dtr) & ~bit);
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}
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DZ_BARRIER();
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if (mbits & DML_BRK) {
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sc->sc_brk |= bit;
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DZ_WRITE_BYTE(dr_break, sc->sc_brk);
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dz_write1(sc, sc->sc_dr.dr_break, sc->sc_brk);
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} else {
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sc->sc_brk &= ~bit;
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DZ_WRITE_BYTE(dr_break, sc->sc_brk);
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dz_write1(sc, sc->sc_dr.dr_break, sc->sc_brk);
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}
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DZ_BARRIER();
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(void) splx(s);
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return (mbits);
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@ -722,31 +747,25 @@ dzscan(void *arg)
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struct dz_softc *sc;
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struct tty *tp;
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int n, bit, port;
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unsigned csr;
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unsigned csr, tmp;
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int s;
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s = spltty();
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for (n = 0; n < dz_cd.cd_ndevs; n++) {
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if (dz_cd.cd_devs[n] == NULL)
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if ((sc = dz_cd.cd_devs[n]) == NULL)
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continue;
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sc = dz_cd.cd_devs[n];
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for (port = 0; port < sc->sc_type; port++) {
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tp = sc->sc_dz[port].dz_tty;
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bit = (1 << port);
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if ((DZ_READ_BYTE(dr_dcd) | sc->sc_dsr) & bit) {
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if ((dz_read1(sc, sc->sc_dr.dr_dcd) | sc->sc_dsr) & bit) {
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if (!(tp->t_state & TS_CARR_ON))
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(*tp->t_linesw->l_modem) (tp, 1);
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} else if ((tp->t_state & TS_CARR_ON) &&
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(*tp->t_linesw->l_modem)(tp, 0) == 0) {
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DZ_WRITE_BYTE(dr_tcr,
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(DZ_READ_WORD(dr_tcrw) & 255) & ~bit);
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DZ_BARRIER();
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tmp = dz_read2(sc, sc->sc_dr.dr_tcrw) & 255;
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dz_write1(sc, sc->sc_dr.dr_tcr, tmp & ~bit);
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}
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}
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@ -758,18 +777,18 @@ dzscan(void *arg)
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* Avoid oscillating SA on and off by not turning
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* if off unless the rate is appropriately low.
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*/
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csr = DZ_READ_WORD(dr_csr);
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if (sc->sc_rxint > (16*10)) {
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if ((csr & DZ_CSR_SAE) == 0)
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DZ_WRITE_WORD(dr_csr, csr | DZ_CSR_SAE);
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} else if ((csr & DZ_CSR_SAE) != 0)
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if (sc->sc_rxint < 10)
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DZ_WRITE_WORD(dr_csr, csr & ~(DZ_CSR_SAE));
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DZ_BARRIER();
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csr = dz_read2(sc, sc->sc_dr.dr_csr);
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tmp = csr;
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if (sc->sc_rxint > 16*10)
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csr |= DZ_CSR_SAE;
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else if (sc->sc_rxint < 10)
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csr &= ~DZ_CSR_SAE;
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if (csr != tmp)
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dz_write2(sc, sc->sc_dr.dr_csr, csr);
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sc->sc_rxint = 0;
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dzxint(sc);
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dzrint(sc);
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}
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(void) splx(s);
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callout_reset(&dzscan_ch, hz, dzscan, NULL);
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