From 1d2fa0cf4dffabf04b6618c08d2672f9eb74b172 Mon Sep 17 00:00:00 2001
From: deraadt <deraadt@NetBSD.org>
Date: Tue, 22 Mar 1994 08:08:43 +0000
Subject: [PATCH] move defn of trapvec to cpu.h

---
 sys/arch/sparc/include/cpu.h  | 21 ++++++++++++++++++++-
 sys/arch/sparc/include/trap.h | 22 +---------------------
 2 files changed, 21 insertions(+), 22 deletions(-)

diff --git a/sys/arch/sparc/include/cpu.h b/sys/arch/sparc/include/cpu.h
index 002584eb5150..045b879946ad 100644
--- a/sys/arch/sparc/include/cpu.h
+++ b/sys/arch/sparc/include/cpu.h
@@ -42,7 +42,7 @@
  *	@(#)cpu.h	8.1 (Berkeley) 6/11/93
  *
  * from: Header: cpu.h,v 1.12 93/05/25 10:36:34 torek Exp  (LBL)
- * $Id: cpu.h,v 1.3 1994/02/01 06:01:25 deraadt Exp $
+ * $Id: cpu.h,v 1.4 1994/03/22 08:08:43 deraadt Exp $
  */
 
 #ifndef _CPU_H_
@@ -163,5 +163,24 @@ void	intr_establish __P((int level, struct intrhand *));
  */
 void	intr_fasttrap __P((int level, void (*vec)(void)));
 
+/*
+ *
+ * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits
+ * of the trap vector table.  The next eight bits are supplied by the
+ * hardware when the trap occurs, and the bottom four bits are always
+ * zero (so that we can shove up to 16 bytes of executable code---exactly
+ * four instructions---into each trap vector).
+ *
+ * The hardware allocates half the trap vectors to hardware and half to
+ * software.
+ *
+ * Traps have priorities assigned (lower number => higher priority).
+ */
+
+struct trapvec {
+	int	tv_instr[4];		/* the four instructions */
+};
+extern struct trapvec trapbase[256];	/* the 256 vectors */
+
 #endif /* KERNEL */
 #endif /* _CPU_H_ */
diff --git a/sys/arch/sparc/include/trap.h b/sys/arch/sparc/include/trap.h
index d34f515ef548..ac5b9e164f6a 100644
--- a/sys/arch/sparc/include/trap.h
+++ b/sys/arch/sparc/include/trap.h
@@ -42,31 +42,11 @@
  *	@(#)trap.h	8.1 (Berkeley) 6/11/93
  *
  * from: Header: trap.h,v 1.9 92/11/26 02:04:47 torek Exp 
- * $Id: trap.h,v 1.2 1993/11/10 03:13:19 deraadt Exp $
+ * $Id: trap.h,v 1.3 1994/03/22 08:08:44 deraadt Exp $
  */
 
 #ifndef	_MACHINE_TRAP_H
 #define	_MACHINE_TRAP_H
-/*
- *
- * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits
- * of the trap vector table.  The next eight bits are supplied by the
- * hardware when the trap occurs, and the bottom four bits are always
- * zero (so that we can shove up to 16 bytes of executable code---exactly
- * four instructions---into each trap vector).
- *
- * The hardware allocates half the trap vectors to hardware and half to
- * software.
- *
- * Traps have priorities assigned (lower number => higher priority).
- */
-
-#if defined(KERNEL) && !defined(LOCORE)
-struct trapvec {
-	int	tv_instr[4];		/* the four instructions */
-};
-extern struct trapvec trapbase[256];	/* the 256 vectors */
-#endif
 
 /*	trap		vec	  (pri) description	*/
 #define	T_RESET		0x00	/* (1) not actually vectored; jumps to 0 */