Pull up following revision(s) (requested by msaitoh in ticket #1773):
share/man/man4/man4.x86/amdsmn.4 1.4,1.5
share/man/man4/man4.x86/amdzentemp.4 1.7
sys/arch/x86/pci/amdsmn.c 1.7-1.9,1.13,1.14
sys/arch/x86/pci/amdzentemp.c 1.8-1.10,1.12-1.15
adjust for possible 49K offset
presence of this offset is indicated by a set 19th bit which is shifted away
this brings the temperature to "normal" levels on my ryzen 2700
(I assumed the same 49K offset as the k10temp project)
correct for known temperature bias values.
Update to support Family 15h Model 60 temperature sensors.
Changes based on FreeBSD amdtemp driver changes by Conrad Meyer.
XXX: Some code duplication between this driver and amdtemp as
parts of the 15h refresh code share more in common with
older CPUs while accessing the device more like 17h.
Don't mix sign and unsigned operands. Just use size_t for the loop.
Apply previous change ("Don't mix sign and unsigned operands. Just use
size_t for the loop.") to another loop variable.
amdzentemp(4): Add Zen 3 support.
amdzentemp(4): Add support for per CCD temperature sensor from FreeBSD.
Fix build failure on i386.
Rename for AMD F15/6X device. No functional change.
amdsmn(4),amdzentemp(4): Add support for 17h/6xh and 19h/6xh.
Note that these drivers are present on some newer AMD Family 15h
processors.
amdsmn.4: Now support AMD Family 19h processors.
This commit is contained in:
martin
parent
e236846411
commit
1c848b0cd3
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@ -1,4 +1,4 @@
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.\" $NetBSD: amdsmn.4,v 1.3.2.2 2018/02/05 13:06:55 martin Exp $
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.\" $NetBSD: amdsmn.4,v 1.3.2.3 2022/10/11 18:22:44 martin Exp $
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.\"
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.\" Copyright (c) 2018 Ian Clark <mrrooster@gmail.com>
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.\" All rights reserved.
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@ -54,7 +54,7 @@
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.\"
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.\" $FreeBSD: head/share/man/man4/amdsmn.4 323184 2017-09-05 15:13:41Z cem $
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.\"
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.Dd January 22, 2018
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.Dd October 2, 2022
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.Dt AMDSMN 4 x86
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.Os
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.Sh NAME
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@ -66,7 +66,8 @@
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The
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.Nm
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driver provides support for resources on the System Management Network bus
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in AMD Family 17h processors.
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in AMD Family 19h processors, 17h processors and some later
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AMD Family 15h processors.
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.Sh SEE ALSO
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.Xr amdzentemp 4
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.Sh HISTORY
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@ -1,4 +1,4 @@
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.\" $NetBSD: amdzentemp.4,v 1.6.2.2 2018/02/05 13:06:55 martin Exp $
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.\" $NetBSD: amdzentemp.4,v 1.6.2.3 2022/10/11 18:22:44 martin Exp $
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.\"-
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.\" Copyright (c) 2008 Christoph Egger
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.\" All rights reserved.
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@ -26,7 +26,7 @@
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.\"
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.\" $FreeBSD: src/share/man/man4/coretemp.4,v 1.4 2007/10/15 20:00:19 netchild Exp $
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.\"
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.Dd January 28, 2018
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.Dd April 20, 2020
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.Dt AMDZENTEMP 4 x86
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.Os
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.Sh NAME
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@ -38,7 +38,7 @@
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The
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.Nm
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driver provides support for the on-die digital thermal sensor present
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on AMD Ryzen CPUs
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on AMD Ryzen CPUs and some later AMD Opteron CPUs.
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.Pp
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These sensors provide 0.125\(deC accuracy.
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There is one sensor for each CPU socket.
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@ -1,7 +1,7 @@
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/* $NetBSD: amdsmn.c,v 1.3.2.4 2019/08/06 16:05:11 martin Exp $ */
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/* $NetBSD: amdsmn.c,v 1.3.2.5 2022/10/11 18:22:44 martin Exp $ */
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/*-
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* Copyright (c) 2017 Conrad Meyer <cem@FreeBSD.org>
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* Copyright (c) 2017, 2019 Conrad Meyer <cem@FreeBSD.org>
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* All rights reserved.
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*
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* NetBSD port by Ian Clark <mrrooster@gmail.com>
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@ -29,10 +29,11 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: amdsmn.c,v 1.3.2.4 2019/08/06 16:05:11 martin Exp $ ");
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__KERNEL_RCSID(0, "$NetBSD: amdsmn.c,v 1.3.2.5 2022/10/11 18:22:44 martin Exp $ ");
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/*
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* Driver for the AMD Family 17h CPU System Management Network.
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* Driver for the AMD Family 15h (model 60+) and 17h CPU
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* System Management Network.
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*/
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#include <sys/param.h>
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@ -52,11 +53,15 @@ __KERNEL_RCSID(0, "$NetBSD: amdsmn.c,v 1.3.2.4 2019/08/06 16:05:11 martin Exp $
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#include "amdsmn.h"
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#include "ioconf.h"
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#define SMN_ADDR_REG 0x60
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#define SMN_DATA_REG 0x64
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#define F15H_SMN_ADDR_REG 0xb8
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#define F15H_SMN_DATA_REG 0xbc
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#define F17H_SMN_ADDR_REG 0x60
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#define F17H_SMN_DATA_REG 0x64
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struct amdsmn_softc {
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kmutex_t smn_lock;
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uint8_t smn_addr_reg;
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uint8_t smn_data_reg;
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struct pci_attach_args pa;
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pci_chipset_tag_t pc;
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pcitag_t pcitag;
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@ -64,10 +69,39 @@ struct amdsmn_softc {
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static const struct pciid {
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uint16_t amdsmn_deviceid;
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uint8_t amdsmn_addr_reg;
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uint8_t amdsmn_data_reg;
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} amdsmn_ids[] = {
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{ PCI_PRODUCT_AMD_F17_RC },
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{ PCI_PRODUCT_AMD_F17_1X_RC },
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{ PCI_PRODUCT_AMD_F17_7X_RC },
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{
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.amdsmn_deviceid = PCI_PRODUCT_AMD_F15_6X_RC,
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.amdsmn_addr_reg = F15H_SMN_ADDR_REG,
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.amdsmn_data_reg = F15H_SMN_DATA_REG,
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},
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{
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.amdsmn_deviceid = PCI_PRODUCT_AMD_F17_RC,
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.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
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.amdsmn_data_reg = F17H_SMN_DATA_REG,
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},
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{
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.amdsmn_deviceid = PCI_PRODUCT_AMD_F17_1X_RC,
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.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
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.amdsmn_data_reg = F17H_SMN_DATA_REG,
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},
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{
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.amdsmn_deviceid = PCI_PRODUCT_AMD_F17_6X_RC,
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.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
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.amdsmn_data_reg = F17H_SMN_DATA_REG,
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},
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{
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.amdsmn_deviceid = PCI_PRODUCT_AMD_F17_7X_RC,
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.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
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.amdsmn_data_reg = F17H_SMN_DATA_REG,
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},
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{
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.amdsmn_deviceid = PCI_PRODUCT_AMD_F19_6X_RC,
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.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
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.amdsmn_data_reg = F17H_SMN_DATA_REG,
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},
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};
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static int amdsmn_match(device_t, cfdata_t, void *);
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amdsmn_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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unsigned int i;
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size_t i;
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if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD)
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return 0;
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@ -110,12 +144,21 @@ amdsmn_attach(device_t parent, device_t self, void *aux)
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struct amdsmn_softc *sc = device_private(self);
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struct pci_attach_args *pa = aux;
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int flags = 0;
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size_t i;
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mutex_init(&sc->smn_lock, MUTEX_DEFAULT, IPL_NONE);
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sc->pa = *pa;
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sc->pc = pa->pa_pc;
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sc->pcitag = pa->pa_tag;
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aprint_normal(": AMD Family 17h System Management Network\n");
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for (i = 0; i < __arraycount(amdsmn_ids); i++)
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if (PCI_PRODUCT(pa->pa_id) == amdsmn_ids[i].amdsmn_deviceid) {
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sc->smn_addr_reg = amdsmn_ids[i].amdsmn_addr_reg;
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sc->smn_data_reg = amdsmn_ids[i].amdsmn_data_reg;
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}
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// aprint_normal(": AMD Family 17h System Management Network\n");
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aprint_normal(": AMD System Management Network\n");
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amdsmn_rescan(self, "amdsmnbus", &flags);
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}
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@ -146,8 +189,8 @@ amdsmn_read(device_t dev, uint32_t addr, uint32_t *value)
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struct amdsmn_softc *sc = device_private(dev);
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mutex_enter(&sc->smn_lock);
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pci_conf_write(sc->pc, sc->pcitag, SMN_ADDR_REG, addr);
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*value = pci_conf_read(sc->pc, sc->pcitag, SMN_DATA_REG);
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pci_conf_write(sc->pc, sc->pcitag, sc->smn_addr_reg, addr);
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*value = pci_conf_read(sc->pc, sc->pcitag, sc->smn_data_reg);
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mutex_exit(&sc->smn_lock);
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return 0;
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@ -159,8 +202,8 @@ amdsmn_write(device_t dev, uint32_t addr, uint32_t value)
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struct amdsmn_softc *sc = device_private(dev);
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mutex_enter(&sc->smn_lock);
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pci_conf_write(sc->pc, sc->pcitag, SMN_ADDR_REG, addr);
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pci_conf_write(sc->pc, sc->pcitag, SMN_DATA_REG, value);
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pci_conf_write(sc->pc, sc->pcitag, sc->smn_addr_reg, addr);
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pci_conf_write(sc->pc, sc->pcitag, sc->smn_data_reg, value);
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mutex_exit(&sc->smn_lock);
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return 0;
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@ -1,8 +1,11 @@
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/* $NetBSD: amdzentemp.c,v 1.7.2.2 2018/02/05 13:06:55 martin Exp $ */
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/* $NetBSD: amdzentemp.c,v 1.7.2.3 2022/10/11 18:22:44 martin Exp $ */
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/* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */
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/*
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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* Copyright (c) 2008, 2020 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* Copyright (c) 2019 Conrad Meyer <cem@FreeBSD.org>
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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@ -50,7 +53,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.7.2.2 2018/02/05 13:06:55 martin Exp $ ");
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__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.7.2.3 2022/10/11 18:22:44 martin Exp $ ");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -70,17 +73,64 @@ __KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.7.2.2 2018/02/05 13:06:55 martin Ex
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#include "amdsmn.h"
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/* Address to query for temp on family 17h */
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#define AMD_17H_CUR_TMP 0x59800
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#define AMD_CURTMP_RANGE_ADJUST 49000000 /* in microKelvins (ie, 49C) */
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#define AMD_CURTMP_RANGE_CHECK __BIT(19)
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#define F10_TEMP_CURTMP __BITS(31,21) /* XXX same as amdtemp.c */
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#define F10_TEMP_CURTMP_MASK 0x7ff
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#define F15M60_CURTMP_TJSEL __BITS(17,16)
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/*
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* Reported Temperature, Family 15h, M60+
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*
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* Same register bit definitions as other Family 15h CPUs, but access is
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* indirect via SMN, like Family 17h.
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*/
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#define AMD_15H_M60H_REPTMP_CTRL 0xd8200ca4
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/*
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* Reported Temperature, Family 17h
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*
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* According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register
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* provide the current temp. bit 19, when clear, means the temp is reported in
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* a range 0.."225C" (probable typo for 255C), and when set changes the range
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* to -49..206C.
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*/
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#define AMD_17H_CUR_TMP 0x59800
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/*
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* The following register set was discovered experimentally by Ondrej Čerman
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* and collaborators, but is not (yet) documented in a PPR/OSRR (other than
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* the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to
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* SMU::THM). It seems plausible and the Linux sensor folks have adopted it.
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*/
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#define AMD_17H_CCD_TMP_BASE 0x59954
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#define AMD_17H_CCD_TMP_VALID __BIT(11)
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struct amdzentemp_softc {
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pci_chipset_tag_t sc_pc;
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pcitag_t sc_pcitag;
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device_t sc_dev;
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struct sysmon_envsys *sc_sme;
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device_t sc_smn;
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envsys_data_t *sc_sensor;
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size_t sc_sensor_len;
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size_t sc_numsensors;
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size_t sc_numsensors;
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int32_t sc_offset;
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uint32_t sc_ccd_tmp_base;
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};
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enum {
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NOSENSOR = 0,
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CORE0_SENSOR0,
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CCD_BASE,
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CCD0 = CCD_BASE,
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CCD1,
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CCD2,
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CCD3,
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CCD4,
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CCD5,
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CCD6,
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CCD7,
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CCD_MAX,
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NUM_CCDS = CCD_MAX - CCD_BASE
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};
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@ -88,9 +138,12 @@ static int amdzentemp_match(device_t, cfdata_t, void *);
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static void amdzentemp_attach(device_t, device_t, void *);
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static int amdzentemp_detach(device_t, int);
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static void amdzentemp_family17_init(struct amdzentemp_softc *);
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static void amdzentemp_family17_setup_sensors(struct amdzentemp_softc *, int);
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static void amdzentemp_init(struct amdzentemp_softc *, int, int);
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static void amdzentemp_setup_sensors(struct amdzentemp_softc *);
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static void amdzentemp_family15_refresh(struct sysmon_envsys *, envsys_data_t *);
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static void amdzentemp_family17_refresh(struct sysmon_envsys *, envsys_data_t *);
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static int amdzentemp_probe_ccd_sensors(struct amdzentemp_softc *, int, int);
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static void amdzentemp_setup_ccd_sensors(struct amdzentemp_softc *);
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CFATTACH_DECL_NEW(amdzentemp, sizeof(struct amdzentemp_softc),
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amdzentemp_match, amdzentemp_attach, amdzentemp_detach, NULL);
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@ -101,9 +154,9 @@ amdzentemp_match(device_t parent, cfdata_t match, void *aux)
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struct pci_attach_args *pa __diagused = aux;
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KASSERT(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD);
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cfdata_t parent_cfdata = device_cfdata(parent);
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/* Got AMD family 17h system management network */
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return parent_cfdata->cf_name &&
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memcmp(parent_cfdata->cf_name, "amdsmn", 6) == 0;
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@ -113,18 +166,21 @@ static void
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amdzentemp_attach(device_t parent, device_t self, void *aux)
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{
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struct amdzentemp_softc *sc = device_private(self);
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struct pci_attach_args *pa = aux;
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struct cpu_info *ci = curcpu();
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int family, model;
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int error;
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size_t i;
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aprint_naive("\n");
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aprint_normal(": AMD CPU Temperature Sensors (Family17h)");
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sc->sc_dev = self;
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family = CPUID_TO_FAMILY(ci->ci_signature);
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model = CPUID_TO_MODEL(ci->ci_signature);
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aprint_naive("\n");
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aprint_normal(": AMD CPU Temperature Sensors (Family%xh)", family);
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sc->sc_pc = pa->pa_pc;
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sc->sc_pcitag = pa->pa_tag;
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sc->sc_smn = parent;
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amdzentemp_family17_init(sc);
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amdzentemp_init(sc, family, model);
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aprint_normal("\n");
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@ -132,12 +188,14 @@ amdzentemp_attach(device_t parent, device_t self, void *aux)
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sc->sc_sensor_len = sizeof(envsys_data_t) * sc->sc_numsensors;
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sc->sc_sensor = kmem_zalloc(sc->sc_sensor_len, KM_SLEEP);
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amdzentemp_family17_setup_sensors(sc, device_unit(self));
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amdzentemp_setup_sensors(sc);
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/*
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* Set properties in sensors.
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*/
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for (i = 0; i < sc->sc_numsensors; i++) {
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if (sc->sc_sensor[i].private == NOSENSOR)
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continue;
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if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[i]))
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goto bad;
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}
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@ -148,7 +206,18 @@ amdzentemp_attach(device_t parent, device_t self, void *aux)
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sc->sc_sme->sme_name = device_xname(self);
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sc->sc_sme->sme_cookie = sc;
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sc->sc_sme->sme_refresh = amdzentemp_family17_refresh;
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switch (family) {
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case 0x15:
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sc->sc_sme->sme_refresh = amdzentemp_family15_refresh;
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break;
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case 0x17:
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case 0x19:
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sc->sc_sme->sme_refresh = amdzentemp_family17_refresh;
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break;
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default:
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/* XXX panic */
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break;
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}
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|
||||
error = sysmon_envsys_register(sc->sc_sme);
|
||||
if (error) {
|
||||
|
|
@ -188,37 +257,206 @@ amdzentemp_detach(device_t self, int flags)
|
|||
|
||||
|
||||
static void
|
||||
amdzentemp_family17_init(struct amdzentemp_softc *sc)
|
||||
amdzentemp_init(struct amdzentemp_softc *sc, int family, int model)
|
||||
{
|
||||
sc->sc_numsensors = 1;
|
||||
|
||||
sc->sc_numsensors = 1 + amdzentemp_probe_ccd_sensors(sc, family, model);
|
||||
sc->sc_offset = 0;
|
||||
|
||||
if (strstr(cpu_brand_string, "AMD Ryzen 5 1600X")
|
||||
|| strstr(cpu_brand_string, "AMD Ryzen 7 1700X")
|
||||
|| strstr(cpu_brand_string, "AMD Ryzen 7 1800X"))
|
||||
sc->sc_offset = -20000000;
|
||||
else if (strstr(cpu_brand_string, "AMD Ryzen 7 2700X"))
|
||||
sc->sc_offset = -10000000;
|
||||
else if (strstr(cpu_brand_string, "AMD Ryzen Threadripper 19")
|
||||
|| strstr(cpu_brand_string, "AMD Ryzen Threadripper 29"))
|
||||
sc->sc_offset = -27000000;
|
||||
}
|
||||
|
||||
static void
|
||||
amdzentemp_family17_setup_sensors(struct amdzentemp_softc *sc, int dv_unit)
|
||||
amdzentemp_setup_sensors(struct amdzentemp_softc *sc)
|
||||
{
|
||||
sc->sc_sensor[0].units = ENVSYS_STEMP;
|
||||
sc->sc_sensor[0].state = ENVSYS_SVALID;
|
||||
sc->sc_sensor[0].flags = ENVSYS_FHAS_ENTROPY;
|
||||
sc->sc_sensor[0].private = CORE0_SENSOR0;
|
||||
|
||||
snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc),
|
||||
"cpu%u temperature", dv_unit);
|
||||
"cpu%u temperature", device_unit(sc->sc_dev));
|
||||
|
||||
if (sc->sc_numsensors > 1)
|
||||
amdzentemp_setup_ccd_sensors(sc);
|
||||
}
|
||||
|
||||
static void
|
||||
amdzentemp_family17_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
|
||||
amdzentemp_family15_refresh(struct sysmon_envsys *sme,
|
||||
envsys_data_t *edata)
|
||||
{
|
||||
struct amdzentemp_softc *sc = sme->sme_cookie;
|
||||
uint32_t temp;
|
||||
uint32_t val, temp;
|
||||
int error;
|
||||
|
||||
error = amdsmn_read(sc->sc_smn, AMD_17H_CUR_TMP, &temp);
|
||||
|
||||
error = amdsmn_read(sc->sc_smn, AMD_15H_M60H_REPTMP_CTRL, &val);
|
||||
if (error) {
|
||||
edata->state = ENVSYS_SINVALID;
|
||||
return;
|
||||
}
|
||||
|
||||
/* from amdtemp.c:amdtemp_family10_refresh() */
|
||||
temp = __SHIFTOUT(val, F10_TEMP_CURTMP);
|
||||
|
||||
/* From Celsius to micro-Kelvin. */
|
||||
edata->value_cur = (temp * 125000) + 273150000;
|
||||
|
||||
/*
|
||||
* On Family 15h and higher, if CurTmpTjSel is 11b, the range is
|
||||
* adjusted down by 49.0 degrees Celsius. (This adjustment is not
|
||||
* documented in BKDGs prior to family 15h model 00h.)
|
||||
*
|
||||
* XXX should be in amdtemp.c:amdtemp_family10_refresh() for f15
|
||||
* as well??
|
||||
*/
|
||||
if (__SHIFTOUT(val, F15M60_CURTMP_TJSEL) == 0x3)
|
||||
edata->value_cur -= AMD_CURTMP_RANGE_ADJUST;
|
||||
|
||||
edata->state = ENVSYS_SVALID;
|
||||
/* From C to uK. */
|
||||
edata->value_cur = ((temp >> 21) * 125000) + 273150000;
|
||||
}
|
||||
|
||||
static void
|
||||
amdzentemp_family17_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
|
||||
{
|
||||
struct amdzentemp_softc *sc = sme->sme_cookie;
|
||||
uint32_t temp;
|
||||
bool minus49;
|
||||
int i, error;
|
||||
|
||||
switch (edata->private) {
|
||||
case CORE0_SENSOR0:
|
||||
/* Tctl */
|
||||
error = amdsmn_read(sc->sc_smn, AMD_17H_CUR_TMP, &temp);
|
||||
if (error) {
|
||||
edata->state = ENVSYS_SINVALID;
|
||||
return;
|
||||
}
|
||||
minus49 = (temp & AMD_CURTMP_RANGE_CHECK) ? true : false;
|
||||
temp = __SHIFTOUT(temp, F10_TEMP_CURTMP);
|
||||
break;
|
||||
case CCD_BASE ... (CCD_MAX - 1):
|
||||
/* Tccd */
|
||||
i = edata->private - CCD_BASE;
|
||||
error = amdsmn_read(sc->sc_smn,
|
||||
sc->sc_ccd_tmp_base + (i * sizeof(temp)), &temp);
|
||||
if (error || !ISSET(temp, AMD_17H_CCD_TMP_VALID)) {
|
||||
edata->state = ENVSYS_SINVALID;
|
||||
return;
|
||||
}
|
||||
minus49 = true;
|
||||
temp &= F10_TEMP_CURTMP_MASK;
|
||||
break;
|
||||
default:
|
||||
edata->state = ENVSYS_SINVALID;
|
||||
return;
|
||||
}
|
||||
edata->state = ENVSYS_SVALID;
|
||||
/* From C to uK. */
|
||||
edata->value_cur = (temp * 125000) + 273150000;
|
||||
/* adjust for possible offset of 49K */
|
||||
if (minus49)
|
||||
edata->value_cur -= AMD_CURTMP_RANGE_ADJUST;
|
||||
edata->value_cur += sc->sc_offset;
|
||||
}
|
||||
|
||||
static int
|
||||
amdzentemp_probe_ccd_sensors17h(struct amdzentemp_softc *sc, int model)
|
||||
{
|
||||
int maxreg;
|
||||
|
||||
switch (model) {
|
||||
case 0x00 ... 0x2f: /* Zen1, Zen+ */
|
||||
maxreg = 4;
|
||||
break;
|
||||
case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */
|
||||
case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */
|
||||
case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */
|
||||
maxreg = 8;
|
||||
break;
|
||||
default:
|
||||
aprint_error_dev(sc->sc_dev,
|
||||
"Unrecognized Family 17h Model: %02xh\n", model);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return maxreg;
|
||||
}
|
||||
|
||||
static int
|
||||
amdzentemp_probe_ccd_sensors19h(struct amdzentemp_softc *sc, int model)
|
||||
{
|
||||
int maxreg;
|
||||
|
||||
switch (model) {
|
||||
case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */
|
||||
case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */
|
||||
maxreg = 8;
|
||||
break;
|
||||
case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */
|
||||
sc->sc_ccd_tmp_base = 0x59b08;
|
||||
maxreg = 8;
|
||||
break;
|
||||
default:
|
||||
aprint_error_dev(sc->sc_dev,
|
||||
"Unrecognized Family 19h Model: %02xh\n", model);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return maxreg;
|
||||
}
|
||||
|
||||
static int
|
||||
amdzentemp_probe_ccd_sensors(struct amdzentemp_softc *sc, int family, int model)
|
||||
{
|
||||
int nccd;
|
||||
|
||||
/* Set default CCD temp sensor base address. */
|
||||
sc->sc_ccd_tmp_base = 0x59954;
|
||||
|
||||
switch (family) {
|
||||
case 0x17:
|
||||
nccd = amdzentemp_probe_ccd_sensors17h(sc, model);
|
||||
break;
|
||||
case 0x19:
|
||||
nccd = amdzentemp_probe_ccd_sensors19h(sc, model);
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
return nccd;
|
||||
}
|
||||
|
||||
static void
|
||||
amdzentemp_setup_ccd_sensors(struct amdzentemp_softc *sc)
|
||||
{
|
||||
envsys_data_t *edata;
|
||||
size_t i;
|
||||
uint32_t temp;
|
||||
int error;
|
||||
|
||||
for (i = 0; i < sc->sc_numsensors - 1; i++) {
|
||||
error = amdsmn_read(sc->sc_smn,
|
||||
sc->sc_ccd_tmp_base + (i * sizeof(temp)), &temp);
|
||||
if (error || !ISSET(temp, AMD_17H_CCD_TMP_VALID))
|
||||
continue;
|
||||
|
||||
edata = &sc->sc_sensor[1 + i];
|
||||
edata->units = ENVSYS_STEMP;
|
||||
edata->state = ENVSYS_SVALID;
|
||||
edata->flags = ENVSYS_FHAS_ENTROPY;
|
||||
edata->private = CCD_BASE + i;
|
||||
snprintf(edata->desc, sizeof(edata->desc),
|
||||
"cpu%u ccd%zu temperature", device_unit(sc->sc_dev), i);
|
||||
}
|
||||
}
|
||||
|
||||
MODULE(MODULE_CLASS_DRIVER, amdzentemp, "sysmon_envsys,amdsmn");
|
||||
|
|
@ -249,4 +487,3 @@ amdzentemp_modcmd(modcmd_t cmd, void *aux)
|
|||
return ENOTTY;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue