Remove X86_MAXPROCS. This fixes PR port-xen/41755.
This also reduces diff to x86/x86/cpu.c as a nice side effect. 'looks good' bouyer@
This commit is contained in:
cegger
parent
4898628cc1
commit
1b91587f84
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.37 2009/11/21 05:54:04 rmind Exp $ */
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/* $NetBSD: cpu.c,v 1.38 2009/11/24 13:04:04 cegger Exp $ */
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/* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */
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/*-
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@ -66,7 +66,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.37 2009/11/21 05:54:04 rmind Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.38 2009/11/24 13:04:04 cegger Exp $");
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#include "opt_ddb.h"
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#include "opt_multiprocessor.h"
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@ -112,7 +112,9 @@ __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.37 2009/11/21 05:54:04 rmind Exp $");
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#include <dev/ic/mc146818reg.h>
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#include <dev/isa/isareg.h>
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#define X86_MAXPROCS 32
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#if MAXCPUS > 32
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#error cpu_info contains 32bit bitmasks
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#endif
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int cpu_match(device_t, cfdata_t, void *);
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void cpu_attach(device_t, device_t, void *);
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@ -146,7 +148,7 @@ CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc),
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#include <machine/tlog.h>
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struct tlog tlog_primary;
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#endif
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struct cpu_info cpu_info_primary = {
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struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = {
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.ci_dev = 0,
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.ci_self = &cpu_info_primary,
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.ci_idepth = -1,
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@ -157,30 +159,26 @@ struct cpu_info cpu_info_primary = {
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#endif
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};
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struct cpu_info phycpu_info_primary = {
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struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = {
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.ci_dev = 0,
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.ci_self = &phycpu_info_primary,
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};
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struct cpu_info *cpu_info_list = &cpu_info_primary;
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struct cpu_info *phycpu_info_list = &phycpu_info_primary;
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static void cpu_set_tss_gates(struct cpu_info *ci);
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uint32_t cpus_attached = 0;
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uint32_t cpus_running = 0;
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uint32_t phycpus_attached = 0;
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uint32_t phycpus_running = 0;
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bool x86_mp_online;
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paddr_t mp_trampoline_paddr = MP_TRAMPOLINE;
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struct cpu_info *phycpu_info[X86_MAXPROCS] = { &cpu_info_primary };
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#ifdef MULTIPROCESSOR
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/*
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* Array of CPU info structures. Must be statically-allocated because
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* curproc, etc. are used early.
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*/
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struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary };
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#if defined(MULTIPROCESSOR)
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void cpu_hatch(void *);
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static void cpu_boot_secondary(struct cpu_info *ci);
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static void cpu_start_secondary(struct cpu_info *ci);
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@ -195,16 +193,11 @@ static void cpu_copy_trampoline(void);
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void
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cpu_init_first(void)
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{
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int cpunum = lapic_cpu_number();
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if (cpunum != 0) {
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cpu_info[0] = NULL;
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cpu_info[cpunum] = &cpu_info_primary;
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}
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cpu_info_primary.ci_cpuid = lapic_cpu_number();
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cpu_copy_trampoline();
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}
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#endif
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#endif /* MULTIPROCESSOR */
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int
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cpu_match(device_t parent, cfdata_t match, void *aux)
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@ -220,11 +213,11 @@ cpu_attach(device_t parent, device_t self, void *aux)
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struct cpu_attach_args *caa = aux;
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struct cpu_info *ci;
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uintptr_t ptr;
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int cpunum = caa->cpu_number;
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static bool again = false;
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sc->sc_dev = self;
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if (cpus_attached == ~0) {
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if (phycpus_attached == ~0) {
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aprint_error(": increase MAXCPUS\n");
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return;
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}
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@ -247,17 +240,10 @@ cpu_attach(device_t parent, device_t self, void *aux)
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ci = (struct cpu_info *)((ptr + CACHE_LINE_SIZE - 1) &
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~(CACHE_LINE_SIZE - 1));
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ci->ci_curldt = -1;
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if (phycpu_info[cpunum] != NULL)
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panic("cpu at apic id %d already attached?", cpunum);
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phycpu_info[cpunum] = ci;
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} else {
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aprint_naive(": %s Processor\n",
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caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot");
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ci = &phycpu_info_primary;
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if (cpunum != 0) {
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phycpu_info[0] = NULL;
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phycpu_info[cpunum] = ci;
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}
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}
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ci->ci_self = ci;
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@ -267,16 +253,26 @@ cpu_attach(device_t parent, device_t self, void *aux)
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ci->ci_cpuid = caa->cpu_number;
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ci->ci_vcpu = NULL;
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/*
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* Boot processor may not be attached first, but the below
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* must be done to allow booting other processors.
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*/
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if (!again) {
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atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY);
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/* Basic init */
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again = true;
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}
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printf(": ");
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switch (caa->cpu_role) {
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case CPU_ROLE_SP:
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printf("(uniprocessor)\n");
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atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY);
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atomic_or_32(&ci->ci_flags, CPUF_SP);
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break;
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case CPU_ROLE_BP:
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printf("(boot processor)\n");
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atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY);
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atomic_or_32(&ci->ci_flags, CPUF_BSP);
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break;
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case CPU_ROLE_AP:
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@ -284,13 +280,22 @@ cpu_attach(device_t parent, device_t self, void *aux)
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* report on an AP
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*/
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printf("(application processor)\n");
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if (ci->ci_flags & CPUF_PRESENT) {
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struct cpu_info *tmp;
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tmp = phycpu_info_list;
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while (tmp->ci_next)
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tmp = tmp->ci_next;
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tmp->ci_next = ci;
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}
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break;
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default:
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panic("unknown processor type??\n");
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}
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atomic_or_32(&cpus_attached, ci->ci_cpumask);
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atomic_or_32(&phycpus_attached, ci->ci_cpumask);
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return;
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}
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@ -356,6 +361,7 @@ cpu_attach_common(device_t parent, device_t self, void *aux)
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struct cpu_info *ci;
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uintptr_t ptr;
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int cpunum = caa->cpu_number;
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static bool again = false;
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sc->sc_dev = self;
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@ -364,22 +370,12 @@ cpu_attach_common(device_t parent, device_t self, void *aux)
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* structure, otherwise use the primary's.
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*/
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if (caa->cpu_role == CPU_ROLE_AP) {
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if (cpunum >= X86_MAXPROCS) {
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aprint_error(": apic id %d ignored, "
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"please increase X86_MAXPROCS\n", cpunum);
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}
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aprint_naive(": Application Processor\n");
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ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1,
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KM_SLEEP);
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ci = (struct cpu_info *)((ptr + CACHE_LINE_SIZE - 1) &
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~(CACHE_LINE_SIZE - 1));
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memset(ci, 0, sizeof(*ci));
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#if defined(MULTIPROCESSOR)
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if (cpu_info[cpunum] != NULL)
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panic("cpu at apic id %d already attached?", cpunum);
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cpu_info[cpunum] = ci;
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#endif
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#ifdef TRAPLOG
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ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP);
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#endif
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@ -387,18 +383,26 @@ cpu_attach_common(device_t parent, device_t self, void *aux)
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aprint_naive(": %s Processor\n",
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caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot");
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ci = &cpu_info_primary;
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#if defined(MULTIPROCESSOR)
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#if NLAPIC > 0
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if (cpunum != lapic_cpu_number()) {
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panic("%s: running CPU is at apic %d"
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" instead of at expected %d",
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device_xname(sc->sc_dev), lapic_cpu_number(), cpunum);
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/* XXX should be done earlier */
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uint32_t reg;
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aprint_verbose("\n");
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aprint_verbose_dev(self, "running CPU at apic %d"
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" instead of at expected %d", lapic_cpu_number(),
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cpunum);
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reg = i82489_readreg(LAPIC_ID);
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i82489_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) |
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(cpunum << LAPIC_ID_SHIFT));
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}
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if (cpunum != lapic_cpu_number()) {
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aprint_error_dev(self, "unable to reset apic id\n");
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}
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#endif
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}
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ci->ci_self = ci;
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sc->sc_info = ci;
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ci->ci_dev = self;
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ci->ci_cpuid = cpunum;
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@ -407,18 +411,19 @@ cpu_attach_common(device_t parent, device_t self, void *aux)
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ci->ci_func = caa->cpu_func;
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/* Must be called before mi_cpu_attach(). */
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cpu_vm_init(ci);
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if (caa->cpu_role == CPU_ROLE_AP) {
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#if defined(MULTIPROCESSOR)
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int error;
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error = mi_cpu_attach(ci);
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if (error != 0) {
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aprint_normal("\n");
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aprint_error_dev(sc->sc_dev, "mi_cpu_attach failed with %d\n",
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error);
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aprint_error_dev(self,
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"mi_cpu_attach failed with %d\n", error);
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return;
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}
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#endif
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} else {
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KASSERT(ci->ci_data.cpu_idlelwp != NULL);
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}
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@ -428,45 +433,51 @@ cpu_attach_common(device_t parent, device_t self, void *aux)
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ci->ci_pmap = pmap_kernel();
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ci->ci_tlbstate = TLBSTATE_STALE;
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/*
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* Boot processor may not be attached first, but the below
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* must be done to allow booting other processors.
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*/
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if (!again) {
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atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY);
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/* Basic init. */
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cpu_intr_init(ci);
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cpu_get_tsc_freq(ci);
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cpu_init(ci);
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cpu_set_tss_gates(ci);
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pmap_cpu_init_late(ci);
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#if NLAPIC > 0
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if (caa->cpu_role != CPU_ROLE_SP) {
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/* Enable lapic. */
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lapic_enable();
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lapic_set_lvt();
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lapic_calibrate_timer();
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}
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#endif
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/* Make sure DELAY() is initialized. */
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DELAY(1);
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again = true;
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}
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/* further PCB init done later. */
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switch (caa->cpu_role) {
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case CPU_ROLE_SP:
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atomic_or_32(&ci->ci_flags,
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CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY);
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cpu_intr_init(ci);
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cpu_get_tsc_freq(ci);
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atomic_or_32(&ci->ci_flags, CPUF_SP);
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cpu_identify(ci);
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cpu_init(ci);
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cpu_set_tss_gates(ci);
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pmap_cpu_init_late(ci);
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x86_cpu_idle_init();
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#if 0
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x86_errata();
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#endif
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x86_cpu_idle_init();
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break;
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case CPU_ROLE_BP:
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atomic_or_32(&ci->ci_flags,
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CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY);
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cpu_intr_init(ci);
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cpu_get_tsc_freq(ci);
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atomic_or_32(&ci->ci_flags, CPUF_BSP);
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cpu_identify(ci);
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cpu_init(ci);
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cpu_set_tss_gates(ci);
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pmap_cpu_init_late(ci);
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x86_cpu_idle_init();
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#if NLAPIC > 0
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/*
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* Enable local apic
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*/
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lapic_enable();
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lapic_set_lvt();
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lapic_calibrate_timer(ci);
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#endif
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#if 0
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x86_errata();
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#endif
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x86_cpu_idle_init();
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break;
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case CPU_ROLE_AP:
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@ -492,7 +503,7 @@ cpu_attach_common(device_t parent, device_t self, void *aux)
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tmp->ci_next = ci;
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}
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#else
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aprint_normal_dev(sc->sc_dev, "not started\n");
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aprint_error_dev(self, "not started\n");
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#endif
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break;
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@ -500,7 +511,6 @@ cpu_attach_common(device_t parent, device_t self, void *aux)
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aprint_normal("\n");
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panic("unknown processor type??\n");
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}
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cpu_vm_init(ci);
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atomic_or_32(&cpus_attached, ci->ci_cpumask);
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@ -514,7 +524,8 @@ cpu_attach_common(device_t parent, device_t self, void *aux)
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struct lwp *l = ci->ci_data.cpu_idlelwp;
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struct pcb *pcb = lwp_getpcb(l);
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aprint_verbose_dev(sc->sc_dev, "idle lwp at %p, idle sp at 0x%p\n",
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aprint_verbose_dev(self,
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"idle lwp at %p, idle sp at 0x%p\n",
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l,
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#ifdef i386
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(void *)pcb->pcb_esp
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@ -577,8 +588,8 @@ cpu_boot_secondary_processors(void)
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struct cpu_info *ci;
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u_long i;
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for (i = 0; i < X86_MAXPROCS; i++) {
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ci = cpu_info[i];
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for (i = 0; i < maxcpus; i++) {
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ci = cpu_lookup(i);
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if (ci == NULL)
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continue;
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if (ci->ci_data.cpu_idlelwp == NULL)
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@ -608,8 +619,8 @@ cpu_init_idle_lwps(void)
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struct cpu_info *ci;
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u_long i;
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for (i = 0; i < X86_MAXPROCS; i++) {
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ci = cpu_info[i];
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for (i = 0; i < maxcpus; i++) {
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ci = cpu_lookup(i);
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if (ci == NULL)
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continue;
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if (ci->ci_data.cpu_idlelwp == NULL)
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@ -787,7 +798,7 @@ cpu_debug_dump(void)
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ci->ci_fpcurlwp);
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}
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}
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#endif
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#endif /* DDB */
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static void
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cpu_copy_trampoline(void)
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@ -815,7 +826,7 @@ cpu_copy_trampoline(void)
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uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY);
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}
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#endif
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#endif /* MULTIPROCESSOR */
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#ifdef i386
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#if 0
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