augustss
parent
3d963db4f2
commit
1b0216af5c
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@ -1,4 +1,4 @@
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/* $NetBSD: ehci.c,v 1.2 2000/12/24 06:42:35 augustss Exp $ */
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/* $NetBSD: ehci.c,v 1.3 2001/11/10 17:06:11 augustss Exp $ */
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/*
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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@ -37,12 +37,11 @@
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*/
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/*
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* USB Enhanced Host Controller Driver.
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* USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
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*
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* EHCI 0.95 spec can be found at
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* http://developer.intel.com/technology/usb/download/ehci-r095.pdf
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* EHCI 0.96 spec can be found at
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* http://developer.intel.com/technology/usb/download/ehci-r096.pdf
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*
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* This is just a stub.
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*/
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#include <sys/param.h>
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@ -69,7 +68,7 @@
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#ifdef EHCI_DEBUG
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#define DPRINTF(x) if (ehcidebug) printf x
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#define DPRINTFN(n,x) if (ehcidebug>(n)) printf x
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int ehcidebug = 0;
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int ehcidebug = 1;
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#define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f))
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#else
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#define DPRINTF(x)
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@ -79,7 +78,71 @@ int ehcidebug = 0;
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usbd_status
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ehci_init(ehci_softc_t *sc)
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{
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printf("EHCI not supported yet.\n");
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u_int32_t version, sparams, cparams, hcr;
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u_int i;
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usbd_status err;
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DPRINTF(("ehci_init: start\n"));
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sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
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version = EREAD2(sc, EHCI_HCIVERSION);
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printf("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev),
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version >> 8, version & 0xff);
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sparams = EREAD4(sc, EHCI_HCSPARAMS);
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DPRINTF(("ehci_init: sparams=0x%x\n", sparams));
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if (EHCI_HCS_N_CC(sparams) != sc->sc_ncomp) {
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printf("%s: wrong number of companions (%d != %d)\n",
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USBDEVNAME(sc->sc_bus.bdev),
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EHCI_HCS_N_CC(sparams), sc->sc_ncomp);
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return (USBD_IOERROR);
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}
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if (sc->sc_ncomp > 0) {
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printf("%s: companion controller%s, %d port%s each:",
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USBDEVNAME(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "",
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EHCI_HCS_N_PCC(sparams),
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EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "");
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for (i = 0; i < sc->sc_ncomp; i++)
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printf(" %s", USBDEVNAME(sc->sc_comps[i]->bdev));
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printf("\n");
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}
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cparams = EREAD4(sc, EHCI_HCCPARAMS);
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DPRINTF(("ehci_init: cparams=0x%x\n", cparams));
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sc->sc_bus.usbrev = USBREV_2_0;
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/* Reset the controller */
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DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev)));
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EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
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usb_delay_ms(&sc->sc_bus, 1);
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EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
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for (i = 0; i < 100; i++) {
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delay(10);
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hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
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if (!hcr)
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break;
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}
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if (hcr) {
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printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev));
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return (USBD_IOERROR);
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}
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/* frame list size at default, read back what we got and use that */
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switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
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case 0: sc->sc_flsize = 1024*4; break;
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case 1: sc->sc_flsize = 512*4; break;
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case 2: sc->sc_flsize = 256*4; break;
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case 3: return (USBD_IOERROR);
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}
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err = usb_allocmem(&sc->sc_bus, sc->sc_flsize,
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EHCI_FLALIGN_ALIGN, &sc->sc_fldma);
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if (err)
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return (err);
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//sc->sc_fl = (struct ohci_hcca *)KERNADDR(&sc->sc_hccadma);
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DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize));
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printf("%s: EHCI not supported yet.\n", USBDEVNAME(sc->sc_bus.bdev));
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return (USBD_IOERROR);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: ehcireg.h,v 1.3 2001/08/20 07:16:35 gehenna Exp $ */
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/* $NetBSD: ehcireg.h,v 1.4 2001/11/10 17:06:11 augustss Exp $ */
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/*
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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@ -46,28 +46,111 @@
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/*** PCI config registers ***/
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#define PCI_USBREV 0x60 /* USB protocol revision */
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#define PCI_CBMEM 0x10 /* configuration base MEM */
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#define PCI_INTERFACE_EHCI 0x20
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#define PCI_USBREV 0x60 /* RO USB protocol revision */
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#define PCI_USBREV_MASK 0xff
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#define PCI_USBREV_PRE_1_0 0x00
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#define PCI_USBREV_1_0 0x10
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#define PCI_USBREV_1_1 0x11
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#define PCI_USBREV_2_0 0x20
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#define PCI_CBMEM 0x10 /* configuration base MEM */
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#define PCI_EHCI_FLADJ 0x61 /*RW Frame len adj, SOF=59488+6*fladj */
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#define PCI_INTERFACE_EHCI 0x20
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#define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */
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#define PCI_EHCI_FLADJ 0x61 /* Frame length adj, SOF counter = 59488+6*fladj */
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/* Regs ar EECP + offset */
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#define PCI_EHCI_USBLEGSUP 0x00
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#define PCI_EHCI_USBLEGCTLSTS 0x04
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#define PCI_EHCI_PORTWAKECAP 0x62
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/*** EHCI capability registers ***/
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/*** EHCI registers ***/
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#define EHCI_CAPLENGTH 0x00 /*RO Capability register length field */
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/* reserved 0x01 */
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#define EHCI_HCIVERSION 0x02 /* RO Interface version number */
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#define EHCI_CAPLENGTH 0x00 /* 1 Capability register length field */
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#define EHCI_HCIVERSION 0x02 /* 2 Interface version number */
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#define EHCI_HCSPARAMS 0x04 /* 4 Structural parameters */
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#define EHCI_HCCPARAMS 0x08 /* 4 Capability parameters */
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#define EHCI_HCSP_PORTROUTE 0x0c /* 15 Companion port route description */
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#define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */
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#define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf)
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#define EHCI_HCS_P_INCICATOR(x) ((x) & 0x10000)
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#define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */
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#define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */
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#define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */
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#define EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */
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#define EHCI_HCCPARAMS 0x08 /* RO Capability parameters */
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#define EHCI_HCC_EECP(x) (((x) >> 8) & 0xff) /* extended ports caps */
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#define EHCI_HCC_IST(x) (((x) >> 4) & 0xf) /* isoc sched threshold */
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#define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */
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#define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */
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#define EHCI_HCC_64BIT(x) ((x) & 0x1) /* 64 bit address cap */
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#define EHCI_HCSP_PORTROUTE 0x0c /*RO Companion port route description */
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/* EHCI operational registers. Offset given by EHCI_CAPLENGTH register */
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#define EHCI_USBCMD 0x00 /* RO, RW, WO Command register */
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#define EHCI_CMD_ITC_M 0x00ff0000 /* RW interrupt threshold ctrl */
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#define EHCI_CMD_ASPME 0x00000800 /* RW/RO async park enable */
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#define EHCI_CMD_ASPMC 0x00000300 /* RW/RO async park count */
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#define EHCI_CMD_LHCR 0x00000080 /* RW light host ctrl reset */
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#define EHCI_CMD_IAAD 0x00000040 /* RW intr on async adv door bell */
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#define EHCI_CMD_ASE 0x00000020 /* RW async sched enable */
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#define EHCI_CMD_PSE 0x00000010 /* RW periodic sched enable */
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#define EHCI_CMD_FLS(x) (((x) >> 2) & 3) /* RW/RO frame list size */
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#define EHCI_CMD_HCRESET 0x00000002 /* RW reset */
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#define EHCI_CMD_RS 0x00000001 /* RW run/stop */
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#define EHCI_USBSTS 0x04 /* RO, RW, RWC Status register */
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#define EHCI_STS_ASS 0x00008000 /* RO async sched status */
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#define EHCI_STS_PSS 0x00004000 /* RO periodic sched status */
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#define EHCI_STS_REC 0x00002000 /* RO reclamation */
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#define EHCI_STS_HCH 0x00001000 /* RO host controller halted */
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#define EHCI_STS_IAA 0x00000020 /* RWC interrupt on async adv */
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#define EHCI_STS_HSE 0x00000010 /* RWC host system error */
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#define EHCI_STS_FLR 0x00000008 /* RWC frame list rollover */
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#define EHCI_STS_PCD 0x00000004 /* RWC port change detect */
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#define EHCI_STS_ERRINT 0x00000002 /* RWC error interrupt */
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#define EHCI_STS_INT 0x00000001 /* RWC interrupt */
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#define EHCI_USBINTR 0x08 /* RW Interrupt register */
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#define EHCI_INTR_IAAE 0x00000020 /* interrupt on async advance ena */
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#define EHCI_INTR_HSEE 0x00000010 /* host system error ena */
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#define EHCI_INTR_FLRE 0x00000008 /* frame list rollover ena */
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#define EHCI_INTR_PCIE 0x00000004 /* port change ena */
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#define EHCI_INTR_UEIE 0x00000002 /* USB error intr ena */
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#define EHCI_INTR_UIE 0x00000001 /* USB intr ena */
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#define EHCI_FRINDEX 0x0c /* RW Frame Index register */
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#define EHCI_CTRLDSSEGMENT 0x10 /* RW Control Data Structure Segment */
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#define EHCI_PERIODICLISTBASE 0x14 /* RW Periodic List Base */
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#define EHCI_ASYNCLISTADDR 0x18 /* RW Async List Base */
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#define EHCI_CONFIGFLAG 0x40 /* RW Configure Flag register */
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#define EHCI_CONF_CF 0x00000001 /* RW configure flag */
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#define EHCI_PORTSC(n) (0x40+4*(n)) /* RO, RW, RWC Port Status reg */
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#define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current ena */
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#define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */
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#define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */
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#define EHCI_PS_PTC 0x000f0000 /* RW port test control */
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#define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */
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#define EHCI_PS_PO 0x00002000 /* RW port owner */
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#define EHCI_PS_PP 0x00001000 /* RW,RO port power */
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#define EHCI_PS_LS 0x00000c00 /* RO line status */
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#define EHCI_PS_PR 0x00000100 /* RW port reset */
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#define EHCI_PS_SUSP 0x00000080 /* RW suspend */
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#define EHCI_PS_FPR 0x00000040 /* RW force port resume */
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#define EHCI_PS_OCC 0x00000020 /* RWC over current change */
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#define EHCI_PS_OCA 0x00000010 /* RO over current active */
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#define EHCI_PS_PEC 0x00000008 /* RWC port enable change */
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#define EHCI_PS_PE 0x00000004 /* RO port enable */
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#define EHCI_PS_CSC 0x00000002 /* RWC connect status change */
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#define EHCI_PS_CS 0x00000001 /* RO connect status */
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#define EHCI_FLALIGN_ALIGN 0x1000
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#endif /* _DEV_PCI_EHCIREG_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: ehcivar.h,v 1.2 2001/11/06 03:16:17 augustss Exp $ */
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/* $NetBSD: ehcivar.h,v 1.3 2001/11/10 17:06:11 augustss Exp $ */
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/*
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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@ -36,6 +36,7 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#define EHCI_COMPANION_MAX 8
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typedef struct ehci_softc {
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struct usbd_bus sc_bus; /* base device */
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bus_space_tag_t iot;
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@ -49,9 +50,21 @@ typedef struct ehci_softc {
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void *sc_powerhook; /* cookie from power hook */
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void *sc_shutdownhook; /* cookie from shutdown hook */
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u_int sc_ncomp;
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struct usbd_bus *sc_comps[EHCI_COMPANION_MAX];
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usb_dma_t sc_fldma;
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u_int sc_flsize;
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device_ptr_t sc_child; /* /dev/usb# device */
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} ehci_softc_t;
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#define EREAD1(sc, a) bus_space_read_1((sc)->iot, (sc)->ioh, (a))
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#define EREAD2(sc, a) bus_space_read_2((sc)->iot, (sc)->ioh, (a))
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#define EREAD4(sc, a) bus_space_read_4((sc)->iot, (sc)->ioh, (a))
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#define EWRITE1(sc, a, x) bus_space_write_1((sc)->iot, (sc)->ioh, (a), (x))
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#define EWRITE2(sc, a, x) bus_space_write_2((sc)->iot, (sc)->ioh, (a), (x))
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#define EWRITE4(sc, a, x) bus_space_write_4((sc)->iot, (sc)->ioh, (a), (x))
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#define EOREAD1(sc, a) bus_space_read_1((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a))
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#define EOREAD2(sc, a) bus_space_read_2((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a))
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#define EOREAD4(sc, a) bus_space_read_4((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a))
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