Add a cacheop for purging/invalidating the whole operand/insn caches.

This is currently not used (actually, it was used locally for a short time
while tracking down a pmap bug), but is here in case it's needed later.

sys/arch/evbsh5/evbsh5/machdep.c

@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.7 2002/10/05 11:01:13 scw Exp $	*/
+/*	$NetBSD: machdep.c,v 1.8 2002/10/07 14:48:14 scw Exp $	*/
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -153,6 +153,7 @@ evbsh5_init(void)
 	__cpu_cache_dinv_iinv = _sh5_stb1_cache_dinv_iinv;
 	__cpu_cache_iinv = _sh5_stb1_cache_iinv;
 	__cpu_cache_iinv_all = _sh5_stb1_cache_iinv_all;
+	__cpu_cache_purge_all = _sh5_stb1_cache_purge_all;
 
 #if NDTFCONS > 0
 	dtfbuf = (vaddr_t) &_dtf_buffer;

sys/arch/sh5/include/cacheops.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: cacheops.h,v 1.4 2002/10/01 07:50:36 scw Exp $	*/
+/*	$NetBSD: cacheops.h,v 1.5 2002/10/07 14:48:14 scw Exp $	*/
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -51,5 +51,6 @@ extern void (*__cpu_cache_dinv)(vaddr_t, paddr_t, vsize_t);
 extern void (*__cpu_cache_dinv_iinv)(vaddr_t, paddr_t, vsize_t);
 extern void (*__cpu_cache_iinv)(vaddr_t, paddr_t, vsize_t);
 extern void (*__cpu_cache_iinv_all)(void);
+extern void (*__cpu_cache_purge_all)(void);
 
 #endif /* __SH5_CACHEOPS_H */

sys/arch/sh5/sh5/sh5_machdep.c

@@ -1,4 +1,4 @@
-/*	$NetBSD: sh5_machdep.c,v 1.4 2002/10/05 11:01:14 scw Exp $	*/
+/*	$NetBSD: sh5_machdep.c,v 1.5 2002/10/07 14:48:14 scw Exp $	*/
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -74,6 +74,7 @@ void (*__cpu_cache_dinv)(vaddr_t, paddr_t, vsize_t);
 void (*__cpu_cache_dinv_iinv)(vaddr_t, paddr_t, vsize_t);
 void (*__cpu_cache_iinv)(vaddr_t, paddr_t, vsize_t);
 void (*__cpu_cache_iinv_all)(void);
+void (*__cpu_cache_purge_all)(void);
 
 /*
  * These variables are needed by /sbin/savecore

sys/arch/sh5/sh5/stb1_locore.S

@@ -1,4 +1,4 @@
-/*	$NetBSD: stb1_locore.S,v 1.7 2002/09/12 12:44:14 scw Exp $	*/
+/*	$NetBSD: stb1_locore.S,v 1.8 2002/10/07 14:48:14 scw Exp $	*/
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -613,6 +613,51 @@ ENTRY_NOPROFILE(_sh5_stb1_cache_iinv_all)
 	putcfg	r0, 0, r1		/* Inv & Enable instruction cache */
 	blink	tr0, r63
 
+/******************************************************************************
+ *
+ * void _sh5_stb1_cache_purge_all(void)
+ *
+ * This one's just stupid. The SH5 has no easy was to writeback and invalidate
+ * all cachelines. We have to force all the cachelines out by accessing
+ * the fixed KSEG0 mapping in such a way that we cover all cache sets. This
+ * will purge any dirty cachelines. We can then safely invalidate the
+ * operand and insn caches.
+ */
+ENTRY_NOPROFILE(_sh5_stb1_cache_purge_all)
+	ptabs/u	r18, tr0
+	pta/l	1f, tr1
+	movi	(STB1_CACHE_NSETS * STB1_CACHE_LINE_SIZE), r0
+
+	/*
+	 * r1-r4 are associated with each of the 4 ways
+	 */
+#ifndef _LP64
+	LDSC32(SH5_KSEG0_BASE, r1)
+#else
+	LDSC64(SH5_KSEG0_BASE, r1)
+#endif
+	add	r1, r0, r2
+	add	r2, r0, r3
+	add	r3, r0, r4
+
+1:	addi	r0, -STB1_CACHE_LINE_SIZE, r0
+	ldx.q	r1, r0, r5
+	ldx.q	r2, r0, r5
+	ldx.q	r3, r0, r5
+	ldx.q	r4, r0, r5
+	bnei/l	r0, 0, tr1
+	synci
+	synco
+
+	movi	3, r1			/* Inv/Enable the Cache */
+	LDC32(STB1_ICCR, r0)		/* Instruction Cache Control Register */
+	putcfg	r0, 0, r1		/* Inv & Enable instruction cache */
+	LDC32(STB1_OCCR, r0)		/* Operand Cache Control Register */
+	putcfg	r0, 0, r1		/* Inv & Enable operand cache */
+	synci
+	synco
+	blink	tr0, r63
+
 
 /******************************************************************************
  *