PR port-arm/54702
Add support for earmv6hf binaries on COMPAT_NETBSD32 for aarch64: - Emulate ARMv6 instructions with cache operations register (c7), that are deprecated since ARMv7, and disabled on ARMv8 with LP64 kernel. - ep_machine_arch (default: earmv7hf) is copied from executables, as we do for mips64. "uname -p" reports earmv6hf if compiled for earmv6hf; configure scripts etc can determine the appropriate architecture. Many thanks to ryo@ for helping me to add support of Thumb-mode, as well as providing exhaustive test cases: https://github.com/ryo/mcr_test/ We've confirmed: - Emulation works in Thumb-mode. - T32 16-bit length illegal instruction results in SIGILL, even if it is located nearby a boundary b/w mapped and unmapped pages. - T32 32-bit instruction results in SIGSEGV if it is located across a boundary b/w mapped and unmapped pages. XXX pullup to netbsd-9
This commit is contained in:
rin
parent
8add6aa962
commit
197cf882e7
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@ -1,4 +1,4 @@
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/* $NetBSD: exec_machdep.c,v 1.4 2018/11/28 08:12:15 ryo Exp $ */
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/* $NetBSD: exec_machdep.c,v 1.5 2019/11/24 04:08:36 rin Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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@ -31,7 +31,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: exec_machdep.c,v 1.4 2018/11/28 08:12:15 ryo Exp $");
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__KERNEL_RCSID(1, "$NetBSD: exec_machdep.c,v 1.5 2019/11/24 04:08:36 rin Exp $");
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#include "opt_compat_netbsd.h"
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#include "opt_compat_netbsd32.h"
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@ -83,6 +83,13 @@ aarch64_netbsd_elf32_probe(struct lwp *l, struct exec_package *epp, void *eh0,
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ID_AA64PFR0_EL1_EL0_64_32)
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return ENOEXEC;
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/*
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* Copy (if any) the machine_arch of the executable to the proc.
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*/
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if (epp->ep_machine_arch[0] != 0)
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strlcpy(l->l_proc->p_md.md_march32, epp->ep_machine_arch,
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sizeof(l->l_proc->p_md.md_march32));
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return 0;
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}
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: netbsd32_machdep.c,v 1.8 2019/11/20 19:37:51 pgoyette Exp $ */
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/* $NetBSD: netbsd32_machdep.c,v 1.9 2019/11/24 04:08:36 rin Exp $ */
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/*
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* Copyright (c) 2018 Ryo Shimizu <ryo@nerv.org>
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@ -27,7 +27,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.8 2019/11/20 19:37:51 pgoyette Exp $");
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__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.9 2019/11/24 04:08:36 rin Exp $");
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#if defined(_KERNEL_OPT)
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#include "opt_compat_netbsd.h"
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@ -55,11 +55,7 @@ __KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.8 2019/11/20 19:37:51 pgoyett
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#include <aarch64/userret.h>
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const char machine32[] = MACHINE;
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#ifdef __AARCH64EB__
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const char machine_arch32[] = "earmv7hfeb";
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#else
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const char machine_arch32[] = "earmv7hf";
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#endif
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const char machine_arch32[] = MACHINE32_ARCH;
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void
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netbsd32_setregs(struct lwp *l, struct exec_package *pack, vaddr_t stack)
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@ -1,4 +1,4 @@
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/* $NetBSD: trap.c,v 1.20 2019/11/21 19:23:58 ad Exp $ */
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/* $NetBSD: trap.c,v 1.21 2019/11/24 04:08:36 rin Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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@ -31,7 +31,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.20 2019/11/21 19:23:58 ad Exp $");
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__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.21 2019/11/24 04:08:36 rin Exp $");
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#include "opt_arm_intr_impl.h"
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#include "opt_compat_netbsd32.h"
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@ -321,6 +321,103 @@ interrupt(struct trapframe *tf)
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cpu_dosoftints();
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}
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#ifdef COMPAT_NETBSD32
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/*
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* 32-bit length Thumb instruction. See ARMv7 DDI0406A A6.3.
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*/
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#define THUMB_32BIT(hi) (((hi) & 0xe000) == 0xe000 && ((hi) & 0x1800))
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static int
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fetch_arm_insn(struct trapframe *tf, uint32_t *insn)
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{
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/* THUMB? */
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if (tf->tf_spsr & SPSR_A32_T) {
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uint16_t *pc = (uint16_t *)(tf->tf_pc & ~1UL); /* XXX */
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uint16_t hi, lo;
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hi = *pc;
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if (!THUMB_32BIT(hi)) {
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/* 16-bit Thumb instruction */
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*insn = hi;
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return 2;
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}
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/*
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* 32-bit Thumb instruction:
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* We can safely retrieve the lower-half word without
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* consideration of a page fault; If present, it must
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* have occurred already in the decode stage.
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*/
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lo = *(pc + 1);
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*insn = ((uint32_t)hi << 16) | lo;
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return 4;
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}
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*insn = *(uint32_t *)tf->tf_pc;
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return 4;
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}
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static int
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emul_arm_insn(struct trapframe *tf)
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{
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uint32_t insn;
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int insn_size;
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insn_size = fetch_arm_insn(tf, &insn);
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switch (insn_size) {
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case 2:
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/* T32-16bit instruction */
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/* XXX: some T32 IT instruction deprecated should be emulated */
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break;
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case 4:
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/* T32-32bit instruction, or A32 instruction */
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/*
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* Emulate ARMv6 instructions with cache operations
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* register (c7), that can be used in user mode.
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*/
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switch (insn & 0x0fff0fff) {
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case 0x0e070f95:
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/*
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* mcr p15, 0, <Rd>, c7, c5, 4
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* (flush prefetch buffer)
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*/
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__asm __volatile("isb sy" ::: "memory");
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goto emulated;
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case 0x0e070f9a:
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/*
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* mcr p15, 0, <Rd>, c7, c10, 4
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* (data synchronization barrier)
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*/
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__asm __volatile("dsb sy" ::: "memory");
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goto emulated;
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case 0x0e070fba:
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/*
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* mcr p15, 0, <Rd>, c7, c10, 5
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* (data memory barrier)
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*/
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__asm __volatile("dmb sy" ::: "memory");
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goto emulated;
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default:
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break;
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}
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break;
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}
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/* unknown, or unsupported instruction */
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return 1;
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emulated:
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tf->tf_pc += insn_size;
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return 0;
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}
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#endif /* COMPAT_NETBSD32 */
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void
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trap_el0_32sync(struct trapframe *tf)
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{
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@ -371,11 +468,18 @@ trap_el0_32sync(struct trapframe *tf)
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userret(l);
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break;
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case ESR_EC_UNKNOWN:
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if (emul_arm_insn(tf))
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goto unknown;
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userret(l);
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break;
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case ESR_EC_CP15_RT:
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case ESR_EC_CP15_RRT:
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case ESR_EC_CP14_RT:
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case ESR_EC_CP14_DT:
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case ESR_EC_CP14_RRT:
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unknown:
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#endif /* COMPAT_NETBSD32 */
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default:
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#ifdef DDB
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/* $NetBSD: netbsd32_machdep.h,v 1.2 2018/10/12 01:28:58 ryo Exp $ */
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/* $NetBSD: netbsd32_machdep.h,v 1.3 2019/11/24 04:08:36 rin Exp $ */
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#ifndef _MACHINE_NETBSD32_H_
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#define _MACHINE_NETBSD32_H_
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@ -107,4 +107,7 @@ struct netbsd32_arm_sync_icache_args {
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netbsd32_size_t len; /* Region size */
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};
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/* Support varying ABI names for netbsd32 */
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#define PROC_MACHINE_ARCH32(P) ((P)->p_md.md_march32)
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#endif /* _MACHINE_NETBSD32_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: param.h,v 1.12 2019/10/19 18:04:26 jmcneill Exp $ */
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/* $NetBSD: param.h,v 1.13 2019/11/24 04:08:36 rin Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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@ -59,9 +59,13 @@
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# ifdef __AARCH64EB__
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# define _MACHINE_ARCH aarch64eb
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# define MACHINE_ARCH "aarch64eb"
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# define _MACHINE32_ARCH earmv7hfeb
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# define MACHINE32_ARCH "earmv7hfeb"
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# else
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# define _MACHINE_ARCH aarch64
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# define MACHINE_ARCH "aarch64"
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# define _MACHINE32_ARCH earmv7hf
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# define MACHINE32_ARCH "earmv7hf"
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# endif /* __AARCH64EB__ */
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# endif /* MACHINE_ARCH */
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#else
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# undef MACHINE
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# undef _MACHINE_ARCH
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# undef MACHINE_ARCH
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# undef _MACHINE32_ARCH
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# undef MACHINE32_ARCH
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# define _MACHINE aarch64
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# define MACHINE "aarch64"
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# ifdef __AARCH64EB__
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# define _MACHINE_ARCH aarch64eb
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# define MACHINE_ARCH "aarch64eb"
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# define _MACHINE32_ARCH earmv7hfeb
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# define MACHINE32_ARCH "earmv7hfeb"
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# else
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# define _MACHINE_ARCH aarch64
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# define MACHINE_ARCH "aarch64"
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# define _MACHINE32_ARCH earmv7hf
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# define MACHINE32_ARCH "earmv7hf"
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# endif /* __AARCH64EB__ */
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#endif /* !_KERNEL */
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/* $NetBSD: proc.h,v 1.3 2018/12/27 09:55:27 mrg Exp $ */
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/* $NetBSD: proc.h,v 1.4 2019/11/24 04:08:36 rin Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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@ -34,6 +34,10 @@
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#ifdef __aarch64__
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#ifdef _KERNEL_OPT
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#include "opt_compat_netbsd32.h"
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#endif
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struct mdlwp {
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void *md_onfault;
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struct trapframe *md_utf;
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struct mdproc {
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void (*md_syscall)(struct trapframe *);
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#ifdef COMPAT_NETBSD32
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char md_march32[12]; /* machine arch of executable */
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#endif
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};
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#ifdef COMPAT_NETBSD32
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#define PROC0_MD_INITIALIZERS .p_md = { .md_march32 = MACHINE32_ARCH },
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#endif
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#elif defined(__arm__)
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#include <arm/proc.h>
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