Always map the EISA configuration registers.
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@ -1,4 +1,4 @@
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/* $NetBSD: ahbreg.h,v 1.6 1998/08/15 01:59:25 thorpej Exp $ */
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/* $NetBSD: ahbreg.h,v 1.7 1998/08/15 02:26:31 mycroft Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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@ -87,21 +87,18 @@ typedef u_long physlen;
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/*
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* Offset of AHA1740 registers, relative from slot base.
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*/
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#define AHB_PORT_OFFSET 0xcc0
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#define AHB_PORT_SIZE 32
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#define AHB_PORT_OFFSET 0xc80
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#define AHB_PORT_SIZE 0x080
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/*
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* AHA1740 EISA board mode registers (relative to port offset)
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*/
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#define PORTADDR 0x00
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#define PORTADDR 0x40
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#define PORTADDR_ENHANCED 0x80
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#define BIOSADDR 0x01
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#define INTDEF 0x02
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#define SCSIDEF 0x03
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#define BUSDEF 0x04
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#define RESV0 0x05
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#define RESV1 0x06
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#define RESV2 0x07
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#define BIOSADDR 0x41
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#define INTDEF 0x42
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#define SCSIDEF 0x43
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#define BUSDEF 0x44
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/**** bit definitions for INTDEF ****/
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#define INT9 0x00
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#define INT10 0x01
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@ -122,22 +119,22 @@ typedef u_long physlen;
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/*
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* AHA1740 ENHANCED mode mailbox control regs (relative to port offset)
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*/
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#define MBOXOUT0 0x10
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#define MBOXOUT1 0x11
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#define MBOXOUT2 0x12
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#define MBOXOUT3 0x13
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#define MBOXOUT0 0x50
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#define MBOXOUT1 0x51
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#define MBOXOUT2 0x52
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#define MBOXOUT3 0x53
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#define ATTN 0x14
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#define G2CNTRL 0x15
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#define G2INTST 0x16
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#define G2STAT 0x17
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#define ATTN 0x54
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#define G2CNTRL 0x55
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#define G2INTST 0x56
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#define G2STAT 0x57
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#define MBOXIN0 0x18
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#define MBOXIN1 0x19
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#define MBOXIN2 0x1A
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#define MBOXIN3 0x1B
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#define MBOXIN0 0x58
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#define MBOXIN1 0x59
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#define MBOXIN2 0x5A
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#define MBOXIN3 0x5B
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#define G2STAT2 0x1C
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#define G2STAT2 0x5C
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/*
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* Bit definitions for the 5 control/status registers
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