From 19387f230c0a841450220b8da996d612e7ba4c3d Mon Sep 17 00:00:00 2001
From: andvar <andvar@NetBSD.org>
Date: Thu, 23 May 2024 08:30:51 +0000
Subject: [PATCH] fix typos in comments.

---
 sys/arch/hpcmips/dev/mq200reg.h     | 6 +++---
 sys/arch/hpcmips/dev/plumvideoreg.h | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/sys/arch/hpcmips/dev/mq200reg.h b/sys/arch/hpcmips/dev/mq200reg.h
index 61882eba6a88..c4e6f98af94a 100644
--- a/sys/arch/hpcmips/dev/mq200reg.h
+++ b/sys/arch/hpcmips/dev/mq200reg.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: mq200reg.h,v 1.11 2010/02/28 15:52:16 snj Exp $	*/
+/*	$NetBSD: mq200reg.h,v 1.12 2024/05/23 08:30:51 andvar Exp $	*/
 
 /*-
  * Copyright (c) 2000, 2001 TAKEMURA Shin
@@ -195,7 +195,7 @@
 #	define MQ200_GC2CRCC_RESULT_SHIFT	8
 #	define MQ200_GC2CRCC_RESULT_MASK	0x3fffff00
 
-/* GC Hotizontal Display Control (GC02R and GC22R)	*/
+/* GC Horizontal Display Control (GC02R and GC22R)	*/
 #define MQ200_GCHDCR(n)		(MQ200_GC(n)+0x08)
 #	define MQ200_GC1HDC_TOTAL_MASK		0x00000fff
 #	define MQ200_GC1HDC_TOTAL_SHIFT		0
@@ -213,7 +213,7 @@
 #	define MQ200_GCVDC_END_SHIFT		16
 	/* bits 31-28 are reserved */
 
-/* GC Hotizontal Sync Control (GC04R and GC24R)	*/
+/* GC Horizontal Sync Control (GC04R and GC24R)	*/
 #define MQ200_GCHSCR(n)		(MQ200_GC(n)+0x10)
 #	define MQ200_GCHSC_START_MASK		0x00000fff
 #	define MQ200_GCHSC_START_SHIFT		0
diff --git a/sys/arch/hpcmips/dev/plumvideoreg.h b/sys/arch/hpcmips/dev/plumvideoreg.h
index 6e61fcd8c805..e2b0a9d56abc 100644
--- a/sys/arch/hpcmips/dev/plumvideoreg.h
+++ b/sys/arch/hpcmips/dev/plumvideoreg.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: plumvideoreg.h,v 1.6 2008/04/28 20:23:21 martin Exp $ */
+/*	$NetBSD: plumvideoreg.h,v 1.7 2024/05/23 08:30:51 andvar Exp $ */
 
 /*-
  * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
@@ -99,7 +99,7 @@
 /*
  *	LCD Timing Register
  */
-/* Horizontanl Total */
+/* Horizontal Total */
 #define	PLUM_VIDEO_PLHT_REG		0x080
 /* Horizontal Display Start */
 #define	PLUM_VIDEO_PLHDS_REG		0x084
@@ -115,7 +115,7 @@
 #define	PLUM_VIDEO_PLVDS_REG		0x098
 /* V-Sync Start/End */
 #define	PLUM_VIDEO_PLVSEVSS_REG		0x09c
-/* V-Blankng Start/End */
+/* V-Blanking Start/End */
 #define	PLUM_VIDEO_PLVBEVBS_REG		0x0a0
 /* Current Line # */
 #define	PLUM_VIDEO_PLCLN_REG		0x0a8