Add support for imx6qp-pcie.
+ Add vpcie-supply support + Add ext_osc support Tested on SABRESD i.MX 6QP.
This commit is contained in:
hkenken
parent
d284e45ce6
commit
1914e34e1b
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@ -1,4 +1,4 @@
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/* $NetBSD: imx6_pcie.c,v 1.3 2019/08/19 03:45:51 hkenken Exp $ */
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/* $NetBSD: imx6_pcie.c,v 1.4 2019/09/02 01:28:41 hkenken Exp $ */
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/*-
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* Copyright (c) 2019 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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@ -25,7 +25,7 @@
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.3 2019/08/19 03:45:51 hkenken Exp $");
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__KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.4 2019/09/02 01:28:41 hkenken Exp $");
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#include "opt_pci.h"
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#include "opt_fdt.h"
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@ -69,6 +69,7 @@ struct imxpcie_fdt_softc {
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struct imxpcie_softc sc_imxpcie;
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struct fdtbus_gpio_pin *sc_pin_reset;
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struct fdtbus_regulator *sc_reg_vpcie;
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};
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static int imx6_pcie_match(device_t, cfdata_t, void *);
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@ -89,9 +90,10 @@ static void imx6_pcie_reset(void *);
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CFATTACH_DECL_NEW(imxpcie_fdt, sizeof(struct imxpcie_fdt_softc),
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imx6_pcie_match, imx6_pcie_attach, NULL, NULL);
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static const char * const compatible[] = {
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"fsl,imx6q-pcie",
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NULL
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static const struct of_compat_data compat_data[] = {
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{ "fsl,imx6q-pcie", false },
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{ "fsl,imx6qp-pcie", true },
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{ NULL }
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};
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static int
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@ -99,7 +101,7 @@ imx6_pcie_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct fdt_attach_args * const faa = aux;
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return of_match_compatible(faa->faa_phandle, compatible);
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return of_match_compat_data(faa->faa_phandle, compat_data);
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}
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static void
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@ -125,6 +127,7 @@ imx6_pcie_attach(device_t parent, device_t self, void *aux)
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sc->sc_gpr_read = imx6_pcie_gpr_read;
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sc->sc_gpr_write = imx6_pcie_gpr_write;
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sc->sc_reset = imx6_pcie_reset;
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sc->sc_have_sw_reset = of_search_compatible(phandle, compat_data)->data;
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if (fdtbus_get_reg_byname(phandle, "dbi", &addr, &size) != 0) {
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aprint_error(": couldn't get registers\n");
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@ -171,6 +174,49 @@ imx6_pcie_attach(device_t parent, device_t self, void *aux)
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return;
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}
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if (of_hasprop(phandle, "vpcie-supply")) {
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ifsc->sc_reg_vpcie = fdtbus_regulator_acquire(phandle, "vpcie-supply");
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if (ifsc->sc_reg_vpcie == NULL) {
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aprint_error(": couldn't acquire regulator\n");
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return;
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}
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aprint_normal_dev(self, "regulator On\n");
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fdtbus_regulator_enable(ifsc->sc_reg_vpcie);
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}
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if (of_hasprop(phandle, "ext_osc")) {
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aprint_normal_dev(self, "Use external OSC\n");
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sc->sc_ext_osc = true;
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sc->sc_clk_pcie_ext = fdtbus_clock_get(phandle, "pcie_ext");
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if (sc->sc_clk_pcie_ext == NULL) {
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aprint_error(": couldn't get clock pcie_ext\n");
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return;
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}
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sc->sc_clk_pcie_ext_src = fdtbus_clock_get(phandle, "pcie_ext_src");
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if (sc->sc_clk_pcie_ext_src == NULL) {
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aprint_error(": couldn't get clock pcie_ext_src\n");
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return;
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}
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struct clk *clk_lvds1_in = imx6_get_clock("lvds1_in");
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if (clk_lvds1_in == NULL) {
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aprint_error(": couldn't get clock lvds1_in\n");
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return;
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}
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int error = clk_set_parent(sc->sc_clk_pcie_ext_src, clk_lvds1_in);
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if (error) {
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aprint_error_dev(sc->sc_dev,
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"couldn't set '%s' parent to '%s': %d\n",
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sc->sc_clk_pcie_ext_src->name, clk_lvds1_in->name, error);
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}
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} else {
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sc->sc_ext_osc = false;
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sc->sc_clk_pcie_ext = NULL;
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sc->sc_clk_pcie_ext_src = NULL;
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}
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TAILQ_INIT(&sc->sc_intrs);
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mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
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@ -1,4 +1,4 @@
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/* $NetBSD: imx6_ccm.c,v 1.13 2019/07/30 11:11:15 hkenken Exp $ */
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/* $NetBSD: imx6_ccm.c,v 1.14 2019/09/02 01:28:41 hkenken Exp $ */
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/*
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* Copyright (c) 2010-2012, 2014 Genetec Corporation. All rights reserved.
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@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: imx6_ccm.c,v 1.13 2019/07/30 11:11:15 hkenken Exp $");
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__KERNEL_RCSID(0, "$NetBSD: imx6_ccm.c,v 1.14 2019/09/02 01:28:41 hkenken Exp $");
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#include "opt_cputypes.h"
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@ -886,6 +886,8 @@ static struct imx6_clk imx6_clks[] = {
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CLK_GATE_EXCLUSIVE("lvds1_gate", "lvds1_sel", CCM_ANALOG, MISC1, LVDS_CLK1_OBEN, LVDS_CLK1_IBEN),
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CLK_GATE_EXCLUSIVE("lvds2_gate", "lvds2_sel", CCM_ANALOG, MISC1, LVDS_CLK2_OBEN, LVDS_CLK2_IBEN),
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CLK_GATE_EXCLUSIVE("lvds1_in", "anaclk1", CCM_ANALOG, MISC1, LVDS_CLK1_IBEN, LVDS_CLK1_OBEN),
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CLK_GATE_EXCLUSIVE("lvds2_in", "anaclk2", CCM_ANALOG, MISC1, LVDS_CLK2_IBEN, LVDS_CLK2_OBEN),
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};
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static struct imx6_clk *imx6_clk_find(const char *);
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@ -1,4 +1,4 @@
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/* $NetBSD: imx6_iomuxreg.h,v 1.5 2019/07/22 11:44:01 hkenken Exp $ */
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/* $NetBSD: imx6_iomuxreg.h,v 1.6 2019/09/02 01:28:41 hkenken Exp $ */
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/*
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* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
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@ -33,6 +33,7 @@
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#define IOMUX_GPR1 0x00000004
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#define IOMUX_GPR1_CFG_L1_CLK_REMOVAL_EN __BIT(31)
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#define IOMUX_GPR1_APP_CLK_REQ_N __BIT(30)
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#define IOMUX_GPR1_PCIE_SW_RST __BIT(29)
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#define IOMUX_GPR1_APP_REQ_EXIT_L1 __BIT(28)
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#define IOMUX_GPR1_APP_READY_ENTR_L23 __BIT(27)
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#define IOMUX_GPR1_APP_REQ_ENTR_L1 __BIT(26)
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@ -1,4 +1,4 @@
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/* $NetBSD: imxpcie.c,v 1.1 2019/07/24 12:33:18 hkenken Exp $ */
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/* $NetBSD: imxpcie.c,v 1.2 2019/09/02 01:28:41 hkenken Exp $ */
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/*
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* Copyright (c) 2019 Genetec Corporation. All rights reserved.
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@ -31,7 +31,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: imxpcie.c,v 1.1 2019/07/24 12:33:18 hkenken Exp $");
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__KERNEL_RCSID(0, "$NetBSD: imxpcie.c,v 1.2 2019/09/02 01:28:41 hkenken Exp $");
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#include "opt_pci.h"
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#include "opt_fdt.h"
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@ -244,34 +244,32 @@ imxpcie_phy_read(struct imxpcie_softc *sc, uint32_t addr)
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static int
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imxpcie_assert_core_reset(struct imxpcie_softc *sc)
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{
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uint32_t gpr1;
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uint32_t gpr12;
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if (sc->sc_have_sw_reset) {
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uint32_t gpr1 = sc->sc_gpr_read(sc, IOMUX_GPR1);
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gpr1 |= IOMUX_GPR1_PCIE_SW_RST;
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sc->sc_gpr_write(sc, IOMUX_GPR1, gpr1);
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} else {
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uint32_t gpr1 = sc->sc_gpr_read(sc, IOMUX_GPR1);
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uint32_t gpr12 = sc->sc_gpr_read(sc, IOMUX_GPR12);
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gpr1 = sc->sc_gpr_read(sc, IOMUX_GPR1);
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gpr12 = sc->sc_gpr_read(sc, IOMUX_GPR12);
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/* already enabled by bootloader */
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if ((gpr1 & IOMUX_GPR1_REF_SSP_EN) &&
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(gpr12 & IOMUX_GPR12_APP_LTSSM_ENABLE)) {
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uint32_t v = PCIE_READ(sc, PCIE_PL_PFLR);
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v &= ~PCIE_PL_PFLR_LINK_STATE;
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v |= PCIE_PL_PFLR_FORCE_LINK;
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PCIE_WRITE(sc, PCIE_PL_PFLR, v);
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/* already enabled by bootloader */
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if ((gpr1 & IOMUX_GPR1_REF_SSP_EN) &&
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(gpr12 & IOMUX_GPR12_APP_LTSSM_ENABLE)) {
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uint32_t v = PCIE_READ(sc, PCIE_PL_PFLR);
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v &= ~PCIE_PL_PFLR_LINK_STATE;
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v |= PCIE_PL_PFLR_FORCE_LINK;
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PCIE_WRITE(sc, PCIE_PL_PFLR, v);
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gpr12 &= ~IOMUX_GPR12_APP_LTSSM_ENABLE;
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sc->sc_gpr_write(sc, IOMUX_GPR12, gpr12);
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}
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gpr12 &= ~IOMUX_GPR12_APP_LTSSM_ENABLE;
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sc->sc_gpr_write(sc, IOMUX_GPR12, gpr12);
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gpr1 |= IOMUX_GPR1_TEST_POWERDOWN;
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sc->sc_gpr_write(sc, IOMUX_GPR1, gpr1);
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gpr1 &= ~IOMUX_GPR1_REF_SSP_EN;
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sc->sc_gpr_write(sc, IOMUX_GPR1, gpr1);
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}
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#if defined(IMX6DQP)
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gpr1 |= IOMUX_GPR1_PCIE_SW_RST;
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sc->sc_gpr_write(sc, IOMUX_GPR1, gpr1);
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#endif
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gpr1 |= IOMUX_GPR1_TEST_POWERDOWN;
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sc->sc_gpr_write(sc, IOMUX_GPR1, gpr1);
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gpr1 &= ~IOMUX_GPR1_REF_SSP_EN;
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sc->sc_gpr_write(sc, IOMUX_GPR1, gpr1);
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return 0;
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}
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@ -285,11 +283,23 @@ imxpcie_deassert_core_reset(struct imxpcie_softc *sc)
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aprint_error_dev(sc->sc_dev, "couldn't enable pcie_axi: %d\n", error);
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return error;
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}
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error = clk_enable(sc->sc_clk_lvds1_gate);
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if (error) {
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aprint_error_dev(sc->sc_dev, "couldn't enable lvds1_gate: %d\n", error);
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return error;
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if (sc->sc_ext_osc) {
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clk_set_parent(sc->sc_clk_pcie_ext, sc->sc_clk_pcie_ext_src);
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error = clk_enable(sc->sc_clk_pcie_ext);
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if (error) {
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aprint_error_dev(sc->sc_dev, "couldn't enable ext: %d\n", error);
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return error;
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}
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} else {
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error = clk_enable(sc->sc_clk_lvds1_gate);
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if (error) {
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aprint_error_dev(sc->sc_dev, "couldn't enable lvds1_gate: %d\n",
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error);
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return error;
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}
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}
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error = clk_enable(sc->sc_clk_pcie_ref);
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if (error) {
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aprint_error_dev(sc->sc_dev, "couldn't enable pcie_ref: %d\n", error);
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@ -298,11 +308,6 @@ imxpcie_deassert_core_reset(struct imxpcie_softc *sc)
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uint32_t gpr1 = sc->sc_gpr_read(sc, IOMUX_GPR1);
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#if defined(IMX6DQP)
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gpr1 &= ~IOMUX_GPR1_PCIE_SW_RST;
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sc->sc_gpr_write(sc, IOMUX_GPR1, gpr1);
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#endif
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delay(50 * 1000);
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gpr1 &= ~IOMUX_GPR1_TEST_POWERDOWN;
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if (sc->sc_reset != NULL)
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sc->sc_reset(sc);
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if (sc->sc_have_sw_reset) {
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gpr1 &= ~IOMUX_GPR1_PCIE_SW_RST;
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sc->sc_gpr_write(sc, IOMUX_GPR1, gpr1);
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delay(200);
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}
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if (sc->sc_ext_osc) {
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delay(5 * 1000);
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uint32_t val;
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val = imxpcie_phy_read(sc, PCIE_PHY_MPLL_OVRD_IN_LO);
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val &= ~MPLL_MULTIPLIER;
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val |= __SHIFTIN(0x19, MPLL_MULTIPLIER);
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val |= MPLL_MULTIPLIER_OVRD;
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imxpcie_phy_write(sc, PCIE_PHY_MPLL_OVRD_IN_LO, val);
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delay(5 * 1000);
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val = imxpcie_phy_read(sc, PCIE_PHY_ATEOVRD);
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val |= REF_USB2_EN;
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imxpcie_phy_write(sc, PCIE_PHY_ATEOVRD, val);
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delay(5 * 1000);
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}
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return 0;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: imxpciereg.h,v 1.1 2019/07/24 12:33:18 hkenken Exp $ */
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/* $NetBSD: imxpciereg.h,v 1.2 2019/09/02 01:28:41 hkenken Exp $ */
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/*
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* Copyright (c) 2015 Ryo Shimizu <ryo@nerv.org>
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@ -220,8 +220,21 @@
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#define PCIE_PHY_SS_PHASE 0x0005
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#define PCIE_PHY_SS_FREQ 0x0006
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#define PCIE_PHY_ATEOVRD 0x0010
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#define ATEOVRD_EN __BIT(3)
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#define REF_USB2_EN __BIT(2)
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#define REF_CLKDIV2 __BIT(1)
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#define PCIE_PHY_MPLL_OVRD_IN_LO 0x0011
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#define PCIE_PHY_MPLL_OVRD_IN_HI 0x0011
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#define RES_ACK_IN_OVRD __BIT(15)
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#define RES_ACK_IN __BIT(14)
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#define RES_REQ_IN_OVRD __BIT(13)
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#define RES_REQ_IN __BIT(12)
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#define RTUNE_REQ_OVRD __BIT(11)
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#define RTUNE_REQ __BIT(10)
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#define MPLL_MULTIPLIER_OVRD __BIT(9)
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#define MPLL_MULTIPLIER __BITS(8, 2)
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#define MPLL_EN_OVRD __BIT(1)
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#define MPLL_EN __BIT(0)
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#define PCIE_PHY_SSC_OVRD_IN 0x0013
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#define PCIE_PHY_BS_OVRD_IN 0x0014
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#define PCIE_PHY_LEVEL_OVRD_IN 0x0015
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@ -1,4 +1,4 @@
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/* $NetBSD: imxpcievar.h,v 1.1 2019/07/24 12:33:18 hkenken Exp $ */
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/* $NetBSD: imxpcievar.h,v 1.2 2019/09/02 01:28:41 hkenken Exp $ */
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/*
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* Copyright (c) 2019 Genetec Corporation. All rights reserved.
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@ -54,12 +54,17 @@ struct imxpcie_softc {
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struct clk *sc_clk_pcie_axi;
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struct clk *sc_clk_lvds1_gate;
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struct clk *sc_clk_pcie_ref;
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struct clk *sc_clk_pcie_ext;
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struct clk *sc_clk_pcie_ext_src;
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bool sc_ext_osc;
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void *sc_cookie;
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void (* sc_pci_netbsd_configure)(void *);
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uint32_t (* sc_gpr_read)(void *, uint32_t);
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void (* sc_gpr_write)(void *, uint32_t, uint32_t);
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void (* sc_reset)(void *);
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bool sc_have_sw_reset;
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};
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struct imxpcie_ih {
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