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Remove acorn26's upc(4) devices.

This commit is contained in:
msaitoh 2019-11-11 04:04:29 +00:00
parent 0c3bbc580c
commit 18f068bbc4
5 changed files with 1 additions and 648 deletions
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13
sys/conf/files
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@ -1,4 +1,4 @@
# $NetBSD: files,v 1.1242 2019/11/09 23:27:50 jmcneill Exp $
# $NetBSD: files,v 1.1243 2019/11/11 04:04:29 msaitoh Exp $
# @(#)files.newconf 7.5 (Berkeley) 5/10/93
version 20171118
@ -1029,17 +1029,6 @@ file dev/ic/wdc.c (ata_dma | ata_udma | ata_piobm | atabus) & atabus & wdc_com
device njata: ata, ata_piobm, wdc_common
file dev/ic/ninjaata32.c njata
# CHIPS and Technologies 82C7[12][01] Universal Peripheral Controller
#
device upc { [offset = -1] }
attach wdc at upc with wdc_upc
attach com at upc with com_upc
attach lpt at upc with lpt_upc
file dev/ic/upc.c upc
file dev/ic/wdc_upc.c wdc_upc
file dev/ic/com_upc.c com_upc
file dev/ic/lpt_upc.c lpt_upc
# AHCI-compatible SATA controllers
define ahcisata_core
file dev/ic/ahcisata_core.c ahcisata_core

70
sys/dev/ic/com_upc.c
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@ -1,70 +0,0 @@
/* $NetBSD: com_upc.c,v 1.12 2018/12/08 17:46:13 thorpej Exp $ */
/*-
* Copyright (c) 2000 Ben Harris
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* This file is part of NetBSD/arm26 -- a port of NetBSD to ARM2/3 machines. */
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: com_upc.c,v 1.12 2018/12/08 17:46:13 thorpej Exp $");
#include <sys/param.h>
#include <sys/device.h>
#include <sys/termios.h> /* XXX for tcflag_t in comvar.h */
#include <sys/bus.h>
#include <sys/intr.h>
#include <dev/ic/comreg.h>
#include <dev/ic/comvar.h>
#include <dev/ic/upcvar.h>
static int com_upc_match(device_t, cfdata_t , void *);
static void com_upc_attach(device_t, device_t, void *);
CFATTACH_DECL_NEW(com_upc, sizeof(struct com_softc),
com_upc_match, com_upc_attach, NULL, NULL);
static int
com_upc_match(device_t parent, cfdata_t cf, void *aux)
{
struct upc_attach_args *ua = aux;
return !strcmp(ua->ua_devtype, "com");
}
static void
com_upc_attach(device_t parent, device_t self, void *aux)
{
struct com_softc *sc = device_private(self);
struct upc_attach_args *ua = aux;
sc->sc_dev = self;
sc->sc_frequency = COM_FREQ;
com_init_regs(&sc->sc_regs, ua->ua_iot, ua->ua_ioh, ua->ua_offset);
com_attach_subr(sc);
upc_intr_establish(ua->ua_irqhandle, IPL_SERIAL, comintr, sc);
}

70
sys/dev/ic/lpt_upc.c
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@ -1,70 +0,0 @@
/* $NetBSD: lpt_upc.c,v 1.10 2009/01/25 14:34:14 bjh21 Exp $ */
/*-
* Copyright (c) 2000 Ben Harris
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* This file is part of NetBSD/arm26 -- a port of NetBSD to ARM2/3 machines. */
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: lpt_upc.c,v 1.10 2009/01/25 14:34:14 bjh21 Exp $");
#include <sys/param.h>
#include <sys/device.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/intr.h>
#include <dev/ic/lptvar.h>
#include <dev/ic/upcvar.h>
static int lpt_upc_match(device_t, cfdata_t , void *);
static void lpt_upc_attach(device_t, device_t, void *);
CFATTACH_DECL_NEW(lpt_upc, sizeof(struct lpt_softc),
lpt_upc_match, lpt_upc_attach, NULL, NULL);
static int
lpt_upc_match(device_t parent, cfdata_t cf, void *aux)
{
struct upc_attach_args *ua = aux;
return !strcmp(ua->ua_devtype, "lpt");
}
static void
lpt_upc_attach(device_t parent, device_t self, void *aux)
{
struct lpt_softc *sc = device_private(self);
struct upc_attach_args *ua = aux;
sc->sc_dev = self;
sc->sc_iot = ua->ua_iot;
sc->sc_ioh = ua->ua_ioh;
lpt_attach_subr(sc);
upc_intr_establish(ua->ua_irqhandle, IPL_TTY, lptintr, sc);
aprint_normal("\n");
}

388
sys/dev/ic/upc.c
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@ -1,388 +0,0 @@
/* $NetBSD: upc.c,v 1.15 2012/10/27 17:18:23 chs Exp $ */
/*-
* Copyright (c) 2000, 2003 Ben Harris
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* upc - driver for C&T Universal Peripheral Controllers
*
* Supports:
* 82C710 Universal Peripheral Controller
* 82C711 Universal Peripheral Controller II
* 82C721 Universal Peripheral Controller III (untested)
*
* The 82C710 is substantially different from its successors.
* Functions that just handle the 82C710 are named upc1_*, which those
* that handle the 82C711 and 82C721 are named upc2_*.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: upc.c,v 1.15 2012/10/27 17:18:23 chs Exp $");
#include <sys/param.h>
#include <sys/device.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <dev/ata/atavar.h> /* XXX needed by wdcvar.h */
#include <dev/ic/comreg.h>
#include <dev/ic/lptreg.h>
#include <dev/ic/lptvar.h>
#include <dev/ic/wdcreg.h>
#include <dev/ic/wdcvar.h>
#include <dev/ic/upcreg.h>
#include <dev/ic/upcvar.h>
#include "locators.h"
/* Conventional port to use for 82C710 configuration */
#define UPC1_PORT_CRI 0x390
#define UPC1_PORT_CAP (UPC1_PORT_CRI + 1)
static int upc1_probe(struct upc_softc *);
static void upc1_attach(struct upc_softc *);
static void upc2_attach(struct upc_softc *);
static void upc_found(struct upc_softc *, char const *, int, int,
struct upc_irqhandle *);
static void upc_found2(struct upc_softc *, char const *, int, int, int, int,
struct upc_irqhandle *);
static int upc_print(void *, char const *);
static int upc2_com3_addr(int);
static int upc2_com4_addr(int);
void
upc_attach(struct upc_softc *sc)
{
if (upc1_probe(sc))
upc1_attach(sc);
else
upc2_attach(sc);
}
static int
upc1_probe(struct upc_softc *sc)
{
return upc1_read_config(sc, UPC1_CFGADDR_CONFBASE) ==
UPC1_PORT_CRI >> UPC1_CONFBASE_SHIFT;
}
static void
upc1_attach(struct upc_softc *sc)
{
u_int8_t cr[16];
int i;
aprint_normal(": 82C710\n");
/* Dump configuration */
for (i = 0; i < 16; i++)
cr[i] = upc1_read_config(sc, i);
aprint_verbose_dev(sc->sc_dev, "config state");
for (i = 0; i < 16; i++)
aprint_verbose(" %02x", cr[i]);
aprint_verbose("\n");
/* FDC */
if (cr[UPC1_CFGADDR_CRC] & UPC1_CRC_FDCEN)
upc_found(sc, "fdc", UPC_PORT_FDCBASE, 2, &sc->sc_fintr);
/* IDE */
if (cr[UPC1_CFGADDR_CRC] & UPC1_CRC_IDEEN)
upc_found2(sc, "wdc", UPC_PORT_IDECMDBASE, 8,
UPC_PORT_IDECTLBASE, 2, &sc->sc_wintr);
/* Parallel */
if (cr[UPC1_CFGADDR_CR0] & UPC1_CR0_PEN)
upc_found(sc, "lpt",
cr[UPC1_CFGADDR_PARBASE] << UPC1_PARBASE_SHIFT,
LPT_NPORTS, &sc->sc_pintr);
/* UART */
if (cr[UPC1_CFGADDR_CR0] & UPC1_CR0_SEN)
upc_found(sc, "com",
cr[UPC1_CFGADDR_UARTBASE] << UPC1_UARTBASE_SHIFT,
COM_NPORTS, &sc->sc_irq4);
/* Mouse */
/* XXX not yet supported */
}
static void
upc2_attach(struct upc_softc *sc)
{
u_int8_t cr[5];
int i;
aprint_normal(": 82C711/82C721");
/* Dump configuration */
for (i = 0; i < 5; i++)
cr[i] = upc2_read_config(sc, i);
aprint_verbose(", config state %02x %02x %02x %02x %02x",
cr[0], cr[1], cr[2], cr[3], cr[4]);
aprint_normal("\n");
/* "Find" the attached devices */
/* FDC */
if (cr[0] & UPC2_CR0_FDC_ENABLE)
upc_found(sc, "fdc", UPC_PORT_FDCBASE, 2, &sc->sc_fintr);
/* IDE */
if (cr[0] & UPC2_CR0_IDE_ENABLE)
upc_found2(sc, "wdc", UPC_PORT_IDECMDBASE, 8,
UPC_PORT_IDECTLBASE, 2, &sc->sc_wintr);
/* Parallel */
switch (cr[1] & UPC2_CR1_LPT_MASK) {
case UPC2_CR1_LPT_3BC:
upc_found(sc, "lpt", 0x3bc, LPT_NPORTS, &sc->sc_pintr);
break;
case UPC2_CR1_LPT_378:
upc_found(sc, "lpt", 0x378, LPT_NPORTS, &sc->sc_pintr);
break;
case UPC2_CR1_LPT_278:
upc_found(sc, "lpt", 0x278, LPT_NPORTS, &sc->sc_pintr);
break;
}
/* UART1 */
if (cr[2] & UPC2_CR2_UART1_ENABLE) {
switch (cr[2] & UPC2_CR2_UART1_MASK) {
case UPC2_CR2_UART1_3F8:
upc_found(sc, "com", 0x3f8, COM_NPORTS, &sc->sc_irq4);
break;
case UPC2_CR2_UART1_2F8:
upc_found(sc, "com", 0x2f8, COM_NPORTS, &sc->sc_irq3);
break;
case UPC2_CR2_UART1_COM3:
upc_found(sc, "com", upc2_com3_addr(cr[1]), COM_NPORTS,
&sc->sc_irq4);
break;
case UPC2_CR2_UART1_COM4:
upc_found(sc, "com", upc2_com4_addr(cr[1]), COM_NPORTS,
&sc->sc_irq3);
break;
}
}
/* UART2 */
if (cr[2] & UPC2_CR2_UART2_ENABLE) {
switch (cr[2] & UPC2_CR2_UART2_MASK) {
case UPC2_CR2_UART2_3F8:
upc_found(sc, "com", 0x3f8, COM_NPORTS, &sc->sc_irq4);
break;
case UPC2_CR2_UART2_2F8:
upc_found(sc, "com", 0x2f8, COM_NPORTS, &sc->sc_irq3);
break;
case UPC2_CR2_UART2_COM3:
upc_found(sc, "com", upc2_com3_addr(cr[1]), COM_NPORTS,
&sc->sc_irq4);
break;
case UPC2_CR2_UART2_COM4:
upc_found(sc, "com", upc2_com4_addr(cr[1]), COM_NPORTS,
&sc->sc_irq3);
break;
}
}
}
static void
upc_found(struct upc_softc *sc, char const *devtype, int offset, int size,
struct upc_irqhandle *uih)
{
struct upc_attach_args ua;
int locs[UPCCF_NLOCS];
ua.ua_devtype = devtype;
ua.ua_offset = offset;
ua.ua_iot = sc->sc_iot;
bus_space_subregion(sc->sc_iot, sc->sc_ioh, offset, size, &ua.ua_ioh);
ua.ua_irqhandle = uih;
locs[UPCCF_OFFSET] = offset;
config_found_sm_loc(sc->sc_dev, "upc", locs, &ua,
upc_print, config_stdsubmatch);
}
static void
upc_found2(struct upc_softc *sc, char const *devtype, int offset, int size,
int offset2, int size2, struct upc_irqhandle *uih)
{
struct upc_attach_args ua;
int locs[UPCCF_NLOCS];
ua.ua_devtype = devtype;
ua.ua_offset = offset;
ua.ua_iot = sc->sc_iot;
bus_space_subregion(sc->sc_iot, sc->sc_ioh, offset, size, &ua.ua_ioh);
bus_space_subregion(sc->sc_iot, sc->sc_ioh, offset2, size2,
&ua.ua_ioh2);
ua.ua_irqhandle = uih;
locs[UPCCF_OFFSET] = offset;
config_found_sm_loc(sc->sc_dev, "upc", locs, &ua,
upc_print, config_stdsubmatch);
}
void
upc_intr_establish(struct upc_irqhandle *uih, int level, int (*func)(void *),
void *arg) {
uih->uih_level = level;
uih->uih_func = func;
uih->uih_arg = arg;
/* Actual MD establishment will be handled later by bus attachment. */
}
static int
upc2_com3_addr(int cr1)
{
switch (cr1 & UPC2_CR1_COM34_MASK) {
case UPC2_CR1_COM34_338_238:
return 0x338;
case UPC2_CR1_COM34_3E8_2E8:
return 0x3e8;
case UPC2_CR1_COM34_2E8_2E0:
return 0x2e8;
case UPC2_CR1_COM34_220_228:
return 0x220;
}
return -1;
}
static int
upc2_com4_addr(int cr1)
{
switch (cr1 & UPC2_CR1_COM34_MASK) {
case UPC2_CR1_COM34_338_238:
return 0x238;
case UPC2_CR1_COM34_3E8_2E8:
return 0x2e8;
case UPC2_CR1_COM34_2E8_2E0:
return 0x2e0;
case UPC2_CR1_COM34_220_228:
return 0x228;
}
return -1;
}
static int
upc_print(void *aux, char const *pnp)
{
struct upc_attach_args *ua = aux;
if (pnp)
aprint_normal("%s at %s", ua->ua_devtype, pnp);
aprint_normal(" offset 0x%x", ua->ua_offset);
return UNCONF;
}
int
upc1_read_config(struct upc_softc *sc, int reg)
{
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
int retval;
/* Switch into configuration mode. */
bus_space_write_1(iot, ioh, UPC1_PORT_CFG1, UPC1_CFGMAGIC_1);
bus_space_write_1(iot, ioh, UPC1_PORT_CFG2, UPC1_CFGMAGIC_2);
bus_space_write_1(iot, ioh, UPC1_PORT_CFG2, UPC1_CFGMAGIC_3);
bus_space_write_1(iot, ioh, UPC1_PORT_CFG2,
UPC1_PORT_CRI >> UPC1_CONFBASE_SHIFT);
bus_space_write_1(iot, ioh, UPC1_PORT_CFG1,
(UPC1_PORT_CRI >> UPC1_CONFBASE_SHIFT) ^ 0xff);
/* Read register. */
bus_space_write_1(iot, ioh, UPC1_PORT_CRI, reg);
retval = bus_space_read_1(iot, ioh, UPC1_PORT_CAP);
/* Leave configuration mode. */
bus_space_write_1(iot, ioh, UPC1_PORT_CRI, UPC1_CFGADDR_EXIT);
bus_space_write_1(iot, ioh, UPC1_PORT_CAP, 0);
return retval;
}
void
upc1_write_config(struct upc_softc *sc, int reg, int val)
{
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
/* Switch into configuration mode. */
bus_space_write_1(iot, ioh, UPC1_PORT_CFG1, UPC1_CFGMAGIC_1);
bus_space_write_1(iot, ioh, UPC1_PORT_CFG2, UPC1_CFGMAGIC_2);
bus_space_write_1(iot, ioh, UPC1_PORT_CFG2, UPC1_CFGMAGIC_3);
bus_space_write_1(iot, ioh, UPC1_PORT_CFG2,
UPC1_PORT_CRI >> UPC1_CONFBASE_SHIFT);
bus_space_write_1(iot, ioh, UPC1_PORT_CFG1,
(UPC1_PORT_CRI >> UPC1_CONFBASE_SHIFT) ^ 0xff);
/* Read register. */
bus_space_write_1(iot, ioh, UPC1_PORT_CRI, reg);
bus_space_write_1(iot, ioh, UPC1_PORT_CAP, val);
/* Leave configuration mode. */
bus_space_write_1(iot, ioh, UPC1_PORT_CRI, UPC1_CFGADDR_EXIT);
bus_space_write_1(iot, ioh, UPC1_PORT_CAP, 0);
}
int
upc2_read_config(struct upc_softc *sc, int reg)
{
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
int retval;
/* Switch into configuration mode. */
bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, UPC2_CFGMAGIC_ENTER);
bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, UPC2_CFGMAGIC_ENTER);
/* Read register. */
bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, reg);
retval = bus_space_read_1(iot, ioh, UPC2_PORT_CFGDATA);
/* Leave configuration mode. */
bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, UPC2_CFGMAGIC_EXIT);
return retval;
}
void
upc2_write_config(struct upc_softc *sc, int reg, int val)
{
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
/* Switch into configuration mode. */
bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, UPC2_CFGMAGIC_ENTER);
bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, UPC2_CFGMAGIC_ENTER);
/* Write register. */
bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, reg);
bus_space_write_1(iot, ioh, UPC2_PORT_CFGDATA, val);
/* Leave configuration mode. */
bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, UPC2_CFGMAGIC_EXIT);
}

108
sys/dev/ic/wdc_upc.c
View File

@ -1,108 +0,0 @@
/* $NetBSD: wdc_upc.c,v 1.31 2017/10/20 07:06:07 jdolecek Exp $ */
/*-
* Copyright (c) 2000 Ben Harris
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* This file is part of NetBSD/arm26 -- a port of NetBSD to ARM2/3 machines. */
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: wdc_upc.c,v 1.31 2017/10/20 07:06:07 jdolecek Exp $");
#include <sys/param.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/intr.h>
#include <dev/ata/atavar.h> /* XXX needed by wdcvar.h */
#include <dev/ic/upcvar.h>
#include <dev/ic/wdcreg.h>
#include <dev/ic/wdcvar.h>
static int wdc_upc_match(device_t, cfdata_t, void *);
static void wdc_upc_attach(device_t, device_t, void *);
struct wdc_upc_softc {
struct wdc_softc sc_wdc;
struct ata_channel *sc_chanlist[1];
struct ata_channel sc_channel;
struct wdc_regs sc_wdc_regs;
};
CFATTACH_DECL_NEW(wdc_upc, sizeof(struct wdc_upc_softc),
wdc_upc_match, wdc_upc_attach, NULL, NULL);
static int
wdc_upc_match(device_t parent, cfdata_t cf, void *aux)
{
struct upc_attach_args *ua = aux;
return !strcmp(ua->ua_devtype, "wdc");
}
static void
wdc_upc_attach(device_t parent, device_t self, void *aux)
{
struct wdc_upc_softc *sc = device_private(self);
struct wdc_regs *wdr;
struct upc_attach_args *ua = aux;
int i;
sc->sc_wdc.sc_atac.atac_dev = self;
sc->sc_wdc.regs = wdr = &sc->sc_wdc_regs;
sc->sc_wdc.sc_atac.atac_cap = ATAC_CAP_DATA16;
sc->sc_wdc.sc_atac.atac_pio_cap = 1; /* XXX ??? */
sc->sc_wdc.sc_atac.atac_nchannels = 1;
sc->sc_chanlist[0] = &sc->sc_channel;
sc->sc_wdc.sc_atac.atac_channels = sc->sc_chanlist;
wdr->cmd_iot = ua->ua_iot;
wdr->cmd_baseioh = ua->ua_ioh;
wdr->ctl_iot = ua->ua_iot;
wdr->ctl_ioh = ua->ua_ioh2;
sc->sc_channel.ch_channel = 0;
sc->sc_channel.ch_atac = &sc->sc_wdc.sc_atac;
sc->sc_wdc.wdc_maxdrives = 2;
for (i = 0; i < WDC_NREG; i++) {
if (bus_space_subregion(ua->ua_iot, ua->ua_ioh, i,
i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
aprint_error_dev(sc->sc_wdc.sc_atac.atac_dev,
"can't subregion I/O space\n");
return;
}
}
wdc_init_shadow_regs(wdr);
upc_intr_establish(ua->ua_irqhandle, IPL_BIO, wdcintr,
&sc->sc_channel);
aprint_normal("\n");
aprint_naive("\n");
wdcattach(&sc->sc_channel);
}