Floppy trap handler.
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pk
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/*
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* Copyright (c) 1995 Paul Kranenburg
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Paul Kranenburg.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: bsd_fdintr.s,v 1.1 1995/02/22 21:14:18 pk Exp $
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*/
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#ifndef FDC_C_HANDLER
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#ifndef LOCORE
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#define LOCORE
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#endif
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#include "assym.s"
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#include <sparc/sparc/intreg.h>
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#include <sparc/sparc/auxreg.h>
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#include <sparc/sparc/vaddrs.h>
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#include <sparc/dev/fdreg.h>
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#include <sparc/dev/fdvar.h>
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/* XXX this goes in a header file -- currently, it's hidden in locore.s */
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#define INTREG_ADDR 0xf8002000
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/* Timeout waiting for chip ready */
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#define POLL_TIMO 100000
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/*
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* register mnemonics. note overlapping assignments.
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*/
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#define R_fdc %l0
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#define R_msr %l1
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#define R_fifo %l2
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#define R_buf %l3
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#define R_tc %l4
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#define R_stat %l3
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#define R_nstat %l4
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#define R_stcnt %l5
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/* use %l6 and %l7 as short term temporaries */
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.seg "data"
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.align 8
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.global _fdciop
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/* A save haven for three precious registers */
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save_l:
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.word 0
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.word 0
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.word 0
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/* Pointer to a `struct fdcio', set in fd.c */
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_fdciop:
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.word 0
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.seg "text"
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.align 4
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.global _fdchwintr
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_fdchwintr:
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set save_l, %l7
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std %l0, [%l7]
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st %l2, [%l7 + 8]
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! load fdc, if it's NULL there's nothing to do: schedule soft interrupt
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sethi %hi(_fdciop), %l7
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ld [%l7 + %lo(_fdciop)], R_fdc
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! load chips register addresses
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ld [R_fdc + FDC_REG_MSR], R_msr ! get chip MSR reg addr
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ld [R_fdc + FDC_REG_FIFO], R_fifo ! get chip FIFO reg addr
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!!ld [R_fdc + FDC_REG_DOR], R_dor ! get chip DOR reg addr
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! find out what we are supposed to do
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ld [R_fdc + FDC_ISTATE], %l7 ! examine flags
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cmp %l7, ISTATE_SENSEI
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be sensei
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nop
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cmp %l7, ISTATE_DMA
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bne spurious
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nop
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! pseudo DMA
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ld [R_fdc + FDC_TC], R_tc ! residual count
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ld [R_fdc + FDC_DATA], R_buf ! IO buffer
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ldub [R_msr], %l7 ! get MSR value
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nextc:
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btst NE7_RQM, %l7 ! room in fifo?
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bnz,a 0f
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btst NE7_NDM, %l7 ! overrun?
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! we filled/emptied the FIFO; update fdc->sc_buf & fdc->sc_tc
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st R_tc, [R_fdc + FDC_TC]
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b x
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st R_buf, [R_fdc + FDC_DATA]
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0:
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bz resultphase ! overrun/underrun
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btst NE7_DIO, %l7 ! IO direction
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bz 1f
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deccc R_tc
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ldub [R_fifo], %l7 ! reading:
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b 2f
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stb %l7, [R_buf] ! *fdc->sc_bufp = *reg_fifo
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1:
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ldub [R_buf], %l7 ! writing:
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stb %l7, [R_fifo] ! *reg_fifo = *fdc->sc_bufp
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2:
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inc R_buf ! fdc->sc_bufp++
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bne,a nextc ! if (--fdc->sc_tc) goto ...
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ldub [R_msr], %l7 ! get MSR value
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! xfer done: update fdc->sc_buf & fdc->sc_tc, mark istate IDLE
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st R_tc, [R_fdc + FDC_TC]
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st R_buf, [R_fdc + FDC_DATA]
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! flip TC bit in auxreg
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sethi %hi(_auxio_reg), %l6
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ld [%l6 + %lo(_auxio_reg)], %l6
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ldub [%l6], %l7
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or %l7, AUXIO_MB1|AUXIO_FTC, %l7
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stb %l7, [%l6]
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! we have some time to kill; anticipate on upcoming
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! result phase.
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add R_fdc, FDC_STATUS, R_stat ! &fdc->sc_status[0]
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mov -1, %l7
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st %l7, [R_fdc + FDC_NSTAT] ! fdc->sc_nstat = -1;
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ldub [%l6], %l7
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andn %l7, AUXIO_FTC, %l7
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or %l7, AUXIO_MB1, %l7
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stb %l7, [%l6]
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b resultphase1
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nop
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spurious:
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mov ISTATE_SPURIOUS, %l7
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st %l7, [R_fdc + FDC_ISTATE]
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b,a ssi
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sensei:
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ldub [R_msr], %l7
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set POLL_TIMO, %l6
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1: deccc %l6 ! timeout?
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be ssi
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and %l7, (NE7_RQM | NE7_DIO | NE7_CB), %l7
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cmp %l7, NE7_RQM
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bne,a 1b ! loop till chip ready
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ldub [R_msr], %l7
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mov NE7CMD_SENSEI, %l7
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stb %l7, [R_fifo]
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resultphase:
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! prepare for result phase
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add R_fdc, FDC_STATUS, R_stat ! &fdc->sc_status[0]
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mov -1, %l7
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st %l7, [R_fdc + FDC_NSTAT] ! fdc->sc_nstat = -1;
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resultphase1:
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clr R_stcnt
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ldub [R_msr], %l7
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set POLL_TIMO, %l6
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1: deccc %l6 ! timeout?
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be ssi
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and %l7, (NE7_RQM | NE7_DIO | NE7_CB), %l7
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cmp %l7, NE7_RQM
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be 3f ! done
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cmp %l7, (NE7_RQM | NE7_DIO | NE7_CB)
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bne,a 1b ! loop till chip ready
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ldub [R_msr], %l7
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cmp R_stcnt, FDC_NSTATUS ! status overrun?
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bge 2f ! if so, load but dont store
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ldub [R_fifo], %l7 ! load the status byte
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stb %l7, [R_stat]
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inc R_stat
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inc R_stcnt
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2: b 1b
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ldub [R_msr], %l7
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3:
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! got status, update sc_nstat and mark istate IDLE
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st R_stcnt, [R_fdc + FDC_NSTAT]
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mov ISTATE_IDLE, %l7
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st %l7, [R_fdc + FDC_ISTATE]
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ssi:
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! set software interrupt
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sethi %hi(INTREG_ADDR), %l7
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ldsb [%l7 + %lo(INTREG_ADDR)], %l6
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or %l6, IE_L4, %l6
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stb %l6, [%l7 + %lo(INTREG_ADDR)]
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x:
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/*
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* Restore psr -- note: psr delay honored by pc restore loads.
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*/
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set save_l, %l7
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ldd [%l7], %l0
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mov %l0, %psr
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nop
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ld [%l7 + 8], %l2
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jmp %l1
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rett %l2
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#endif
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