Add more ASYNC event codes here. Add NVRAM definitions.
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mjacob
parent
c0eabb441f
commit
170521610e
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@ -1,5 +1,4 @@
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/* $NetBSD: ispreg.h,v 1.6 1998/07/18 21:05:39 mjacob Exp $ */
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/* $Id: ispreg.h,v 1.6 1998/07/18 21:05:39 mjacob Exp $ */
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/* $Id: ispreg.h,v 1.7 1998/09/08 07:22:06 mjacob Exp $ */
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/*
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* Machine Independent (well, as best as possible) register
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* definitions for Qlogic ISP SCSI adapters.
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@ -197,6 +196,12 @@
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#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */
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#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */
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/* NVRAM SEMAPHORE REGISTER */
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#define BIU_NVRAM_CLOCK 0x0001
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#define BIU_NVRAM_SELECT 0x0002
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#define BIU_NVRAM_DATAOUT 0x0004
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#define BIU_NVRAM_DATAIN 0x0008
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#define ISP_NVRAM_READ 6
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/* COMNMAND && DATA DMA CONFIGURATION REGISTER */
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#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */
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@ -304,31 +309,6 @@
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#define NMBOX(isp) \
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(((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \
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((isp)->isp_type & ISP_HA_FC))? 8 : 6)
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/*
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* Mailbox Command Complete Status Codes
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*/
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#define MBOX_COMMAND_COMPLETE 0x4000
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#define MBOX_INVALID_COMMAND 0x4001
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#define MBOX_HOST_INTERFACE_ERROR 0x4002
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#define MBOX_TEST_FAILED 0x4003
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#define MBOX_COMMAND_ERROR 0x4005
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#define MBOX_COMMAND_PARAM_ERROR 0x4006
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/*
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* Asynchronous event status codes
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*/
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#define ASYNC_BUS_RESET 0x8001
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#define ASYNC_SYSTEM_ERROR 0x8002
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#define ASYNC_RQS_XFER_ERR 0x8003
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#define ASYNC_RSP_XFER_ERR 0x8004
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#define ASYNC_QWAKEUP 0x8005
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#define ASYNC_TIMEOUT_RESET 0x8006
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/* for ISP2100 only */
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#define ASYNC_LIP_OCCURRED 0x8010
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#define ASYNC_LOOP_UP 0x8011
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#define ASYNC_LOOP_DOWN 0x8012
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#define ASYNC_LOOP_RESET 0x8013
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/*
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* SXP Block Register Offsets
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@ -551,6 +531,10 @@
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#define RISC_PSR_ALU_MSB 0x0400
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#define RISC_PSR_ALU_CARRY 0x0200
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#define RISC_PSR_ALU_ZERO 0x0100
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#define RISC_PSR_PCI_ULTRA 0x0080
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#define RISC_PSR_SBUS_ULTRA 0x0020
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#define RISC_PSR_DMA_INT 0x0010
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#define RISC_PSR_SXP_INT 0x0008
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#define RISC_PSR_HOST_INT 0x0004
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@ -587,4 +571,123 @@
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#define HCCR_PAUSE 0x0020 /* R : RISC paused */
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#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */
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/*
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* Qlogic 1XXX NVRAM is an array of 128 bytes.
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*
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* Some portion of the front of this is for general host adapter properties
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* This is followed by an array of per-target parameters, and is tailed off
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* with a checksum xor byte at offset 127. For non-byte entities data is
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* stored in Little Endian order.
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*/
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#define ISP_NVRAM_SIZE 128
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#define ISPBSMX(c, byte, shift, mask) \
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(((c)[(byte)] >> (shift)) & (mask))
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#define ISP_NVRAM_VERSION(c) (c)[4]
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#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03)
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#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01)
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#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01)
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#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f)
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#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6]
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#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7]
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#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8]
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#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f)
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#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01)
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#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01)
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#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01)
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#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01)
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#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10]
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#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01)
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#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01)
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#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01)
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#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01)
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#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01)
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#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01)
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#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01)
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#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01)
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#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8))
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#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8))
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#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01)
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#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01)
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#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01)
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#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01)
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#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01)
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#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01)
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#define ISP_NVRAM_TARGOFF 28
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#define ISP_NVARM_TARGSIZE 6
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#define _IxT(tgt, tidx) \
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(ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx))
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#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01)
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#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01)
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#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01)
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#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01)
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#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01)
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#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01)
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#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01)
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#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01)
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#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff)
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#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff)
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#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f)
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#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01)
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#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01)
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/*
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* Qlogic 2XXX NVRAM is an array of 256 bytes.
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*
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* Some portion of the front of this is for general RISC engine parameters,
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* mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command.
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*
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* This is followed by some general host adapter parameters, and ends with
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* a checksum xor byte at offset 255. For non-byte entities data is stored
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* in Little Endian order.
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*/
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#define ISP2100_NVRAM_SIZE 256
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/* ISP_NVRAM_VERSION is in same overall place */
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#define ISP2100_NVRAM_RISCVER(c) (c)[6]
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#define ISP2100_NVRAM_ENABLE_HARDLOOPID(c) ISPBSMX(c, 8, 0, 0x01)
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#define ISP2100_NVRAM_ENABLE_FAIRNESS(c) ISPBSMX(c, 8, 1, 0x01)
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#define ISP2100_NVRAM_ENABLE_FULLDUPLEX(c) ISPBSMX(c, 8, 2, 0x01)
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#define ISP2100_NVRAM_ENABLE_FAST_POSTING(c) ISPBSMX(c, 8, 3, 0x01)
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#define ISP2100_NVRAM_ENABLE_TARGET_MODE(c) ISPBSMX(c, 8, 4, 0x01)
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#define ISP2100_NVRAM_ENABLE_INITIATOR_MODE(c) ISPBSMX(c, 8, 5, 0x01)
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#define ISP2100_NVRAM_QFRZ(c) ISPBSMX(c, 8, 6, 0x01)
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#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8))
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#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8))
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#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8))
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#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16]
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#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17]
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#define ISP2100_NVRAM_NODE_NAME(c) ( \
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(((u_int64_t)(c)[18]) << 56) | \
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(((u_int64_t)(c)[19]) << 48) | \
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(((u_int64_t)(c)[20]) << 40) | \
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(((u_int64_t)(c)[21]) << 32) | \
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(((u_int64_t)(c)[22]) << 24) | \
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(((u_int64_t)(c)[23]) << 16) | \
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(((u_int64_t)(c)[24]) << 8) | \
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(((u_int64_t)(c)[25]) << 0))
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#define ISP2100_NVRAM_HARDLOOPID(c) (c)[24]
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#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01)
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#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01)
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#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01)
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#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01)
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#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01)
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#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01)
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#define ISP2100_NVRAM_BOOT_NODE_NAME(c) ( \
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(((u_int64_t)(c)[72]) << 56) | \
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(((u_int64_t)(c)[73]) << 48) | \
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(((u_int64_t)(c)[74]) << 40) | \
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(((u_int64_t)(c)[75]) << 32) | \
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(((u_int64_t)(c)[76]) << 24) | \
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(((u_int64_t)(c)[77]) << 16) | \
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(((u_int64_t)(c)[78]) << 8) | \
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(((u_int64_t)(c)[79]) << 0))
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#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80]
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#endif /* _ISPREG_H */
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