diff --git a/sys/arch/hp700/conf/Makefile.hp700 b/sys/arch/hp700/conf/Makefile.hp700 index 738f90e40e32..b83f30f55b27 100644 --- a/sys/arch/hp700/conf/Makefile.hp700 +++ b/sys/arch/hp700/conf/Makefile.hp700 @@ -1,4 +1,4 @@ -# $NetBSD: Makefile.hp700,v 1.1 2002/06/06 19:48:02 fredette Exp $ +# $NetBSD: Makefile.hp700,v 1.2 2002/08/05 20:58:35 fredette Exp $ # Makefile for NetBSD # @@ -85,7 +85,7 @@ locore.o: ${HP700}/hp700/locore.S ## (5) link settings ## LINKFORMAT= -T ${HP700}/conf/ld.script -TEXTADDR?= 00080000 +TEXTADDR?= 00200000 EXTRA_LINKFLAGS= -Map $@.map ## diff --git a/sys/arch/hp700/conf/ld.script b/sys/arch/hp700/conf/ld.script index 518eeabbfacb..048595191bf5 100644 --- a/sys/arch/hp700/conf/ld.script +++ b/sys/arch/hp700/conf/ld.script @@ -1,10 +1,10 @@ -/* $NetBSD: ld.script,v 1.1 2002/06/06 19:48:02 fredette Exp $ */ +/* $NetBSD: ld.script,v 1.2 2002/08/05 20:58:36 fredette Exp $ */ /* $OpenBSD: ld.script,v 1.7 1999/12/17 07:02:38 mickey Exp $ */ OUTPUT_FORMAT("elf32-hppa") OUTPUT_ARCH(hppa) -ENTRY($start) +ENTRY(start) SECTIONS { /* Read-only sections, merged into text segment: */ @@ -24,8 +24,8 @@ SECTIONS __unwind_end = .; . = ALIGN(4096); } = 0 /* 0x08000240 nop filled, does not work */ - . = ALIGN(524288); etext = ABSOLUTE(.); + . = ALIGN(0x200000); .data : { diff --git a/sys/arch/hp700/dev/cpu.c b/sys/arch/hp700/dev/cpu.c index b0653d97da8b..8aeed7b3f50b 100644 --- a/sys/arch/hp700/dev/cpu.c +++ b/sys/arch/hp700/dev/cpu.c @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.c,v 1.1 2002/06/06 19:48:03 fredette Exp $ */ +/* $NetBSD: cpu.c,v 1.2 2002/08/05 20:58:36 fredette Exp $ */ /* $OpenBSD: cpu.c,v 1.8 2000/08/15 20:38:24 mickey Exp $ */ @@ -87,47 +87,31 @@ cpuattach(parent, self, aux) /* machdep.c */ extern struct pdc_cache pdc_cache; extern struct pdc_btlb pdc_btlb; + extern struct pdc_model pdc_model; extern u_int cpu_ticksnum, cpu_ticksdenom; - struct pdc_model pdc_model PDC_ALIGNMENT; - struct pdc_cpuid pdc_cpuid PDC_ALIGNMENT; - u_int pdc_cversion[32] PDC_ALIGNMENT; register struct cpu_softc *sc = (struct cpu_softc *)self; register struct confargs *ca = aux; - const char *p = NULL; + char c; + const char lvls[4][4] = { "0", "1", "1.5", "2" }; u_int mhz = 100 * cpu_ticksnum / cpu_ticksdenom; - int err; - bzero (&pdc_cpuid, sizeof(pdc_cpuid)); - if (pdc_call((iodcio_t)pdc, 0, PDC_MODEL, PDC_MODEL_CPUID, - &pdc_cpuid, sc->sc_dev.dv_unit, 0, 0, 0) >= 0) { + /* Print the CPU chip name, nickname, and rev. */ + printf(": %s", hppa_cpu_info->hppa_cpu_info_chip_name); + if (hppa_cpu_info->hppa_cpu_info_chip_nickname != NULL) + printf(" (%s)", hppa_cpu_info->hppa_cpu_info_chip_nickname); + printf(" rev %d", (*hppa_cpu_info->desidhash)()); - /* patch for old 8200 */ - if (pdc_cpuid.version == HPPA_CPU_PCXUP && - pdc_cpuid.revision > 0x0d) - pdc_cpuid.version = HPPA_CPU_PCXUP1; - - p = hppa_mod_info(HPPA_TYPE_CPU, pdc_cpuid.version); - } - /* otherwise try to guess on component version numbers */ - else if (pdc_call((iodcio_t)pdc, 0, PDC_MODEL, PDC_MODEL_COMP, - &pdc_cversion, sc->sc_dev.dv_unit) >= 0) { - /* XXX p = hppa_mod_info(HPPA_TYPE_CPU,pdc_cversion[0]); */ - } - - printf (": %s rev %d, ", p? p : cpu_typename, (*cpu_desidhash)()); - - if ((err = pdc_call((iodcio_t)pdc, 0, PDC_MODEL, PDC_MODEL_INFO, - &pdc_model)) < 0) { -#ifdef DEBUG - printf("WARNING: PDC_MODEL failed (%d)\n", err); -#endif - } else { - static const char lvls[4][4] = { "0", "1", "1.5", "2" }; - - printf("lev %s, cat %c, ", - lvls[pdc_model.pa_lvl], "AB"[pdc_model.mc]); - } + /* Print the CPU type, spec, level, category, and speed. */ + printf("\n%s: %s, PA-RISC %d.%d", + self->dv_xname, + hppa_cpu_info->hppa_cpu_info_chip_type, + HPPA_PA_SPEC_MAJOR(hppa_cpu_info->hppa_cpu_info_pa_spec), + HPPA_PA_SPEC_MINOR(hppa_cpu_info->hppa_cpu_info_pa_spec)); + c = HPPA_PA_SPEC_LETTER(hppa_cpu_info->hppa_cpu_info_pa_spec); + if (c != '\0') printf("%c", c); + printf(", lev %s, cat %c, ", + lvls[pdc_model.pa_lvl], "AB"[pdc_model.mc]); printf ("%d", mhz / 100); if (mhz % 100 > 9) diff --git a/sys/arch/hp700/dev/cpudevs b/sys/arch/hp700/dev/cpudevs index f3fc38dd013c..cd5ffbbce33c 100644 --- a/sys/arch/hp700/dev/cpudevs +++ b/sys/arch/hp700/dev/cpudevs @@ -1,4 +1,4 @@ -$NetBSD: cpudevs,v 1.1 2002/06/06 19:48:03 fredette Exp $ +$NetBSD: cpudevs,v 1.2 2002/08/05 20:58:36 fredette Exp $ $OpenBSD: cpudevs,v 1.18 2001/03/20 08:15:22 mickey Exp $ @@ -56,233 +56,251 @@ type cpu 0x81 CPU chips type fpu 0x82 FPU chips type bus 0x83 Main Busses +/* + * NB: the device name for a board begins with an encoding of the + * type of CPU it contains. This is decoded by hppa_init() to + * figure out what kind of CPU it is likely dealing with. + * + * Key: + * X = PA7000 (PCX) + * S = PA7000 (PCX-S) + * 0T = PA7100 (PCX-T) + * 5T = PA7150 (PCX-T) + * L = PA7100LC (PCX-L) + * T' = PA7200 (PCX-T') + * L2 = PA7300LC (PCX-L2) + * U = PA8000 (PCX-U) + * U+ = PA8200 (PCX-U+) + * W = PA8500 (PCX-W) + * W+ = PA8600 (PCX-W+) + */ +board x 0x004 X 840/930 (Indigo) +board x 0x008 X 825/925 (FireFox) +board x 0x00a X 83[45]/[69]35 (TopGun) +board x 0x00b X 845/645 (Technical ShoGun) +board x 0x00c X 850/950 (Cheetah) +board x 0x00f X 949 (Commercial ShoGun) -board HP840 0x004 840/930 (Indigo) -board HP825 0x008 825/925 (FireFox) -board HP835 0x00a 83[45]/[69]35 (TopGun) -board HP845 0x00b 845/645 (Technical ShoGun) -board HP850 0x00C 850/950 (Cheetah) -board HP949 0x00f 949 (Commercial ShoGun) +board x 0x080 X 950S (Cheetah) +board x 0x081 X 855/955 (Jaguar) +board x 0x082 X 860/960 (Cougar) +board x 0x083 X 865/870/980 (Panther) -board HP950S 0x080 950S (Cheetah) -board HP855 0x081 855/955 (Jaguar) -board HP860 0x082 860/960 (Cougar) -board HP870 0x083 865/870/980 (Panther) +board x 0x100 X 810 (Burgundy) +board x 0x101 X 822/922 (SilverFox Low) +board x 0x102 X 832/932 (SilverFox High) +board x 0x103 X 808/815/920 (Lego, SilverLite) +board x 0x104 X 842/948 (SilverBullet Low) +board x 0x105 X 852/958 (SilverBullet High) +board x 0x106 X (Oboe) -board HP810 0x100 810 (Burgundy) -board HP822 0x101 822/922 (SilverFox Low) -board HP832 0x102 832/932 (SilverFox High) -board HP808 0x103 808/815/920 (Lego, SilverLite) -board HP842 0x104 842/948 (SilverBullet Low) -board HP852 0x105 852/958 (SilverBullet High) -board HPOBOE 0x106 (Oboe) +board x 0x180 X (Dragon) +board x 0x181 X 890/990/992 (Chimera) +board x 0x182 0T 891/T500 (TNT 100) +board x 0x183 0T 892/T520 (TNT 120) +board x 0x184 U 893/T540 (Jade 180 U) -board HPDRAGON 0x180 (Dragon) -board HP890 0x181 890/990/992 (Chimera) -board HP891 0x182 891/T500 (TNT 100) -board HP892 0x183 892/T520 (TNT 120) -board HP893_T540 0x184 893/T540 (Jade 180 U) +board x 0x1ff ? Hitachi X Processor -board HPHXPROC 0x1ff Hitachi X Processor +board x 0x200 S 720 (Cobra) +board x 0x201 S 750/66 (Coral) +board x 0x202 S 730/66 (King Cobra) +board x 0x203 0T 735/99 (Hardball) +board x 0x204 0T 755/99 (Coral II) +board HP755_125 0x205 0T 755/125 (Coral II) +#board HP755_125 0x205 0T 755/125 (Snake Eagle, opt 91) +board x 0x206 0T 735/130 (Snake Cheetah) -board HP720 0x200 720 (Cobra) -board HP750_66 0x201 750/66 (Coral) -board HP730_66 0x202 730/66 (King Cobra) -board HP735_99 0x203 735/99 (Hardball) -board HP755_99 0x204 755/99 (Coral II) -board HP755_125 0x205 755/125 (Coral II) -#board HP755_125E 0x205 755/125 (Snake Eagle, opt 91) -board HP735_130 0x206 735/130 (Snake Cheetah) +board x 0x280 S 817/827/957/957LX/FH20 (Nova Low) +board x 0x281 S 837/847/857/967/967LX/FGHI30 (Nova High) +board x 0x282 S 807/917/917LX/927/927LX/937/937LX/947/947LX/F10 (Nova8) +board x 0x283 S 867/877/977/GHI40 (Nova64) +board x 0x284 0T 887/897/987/GHI50 (TNova) +board x 0x285 0T (TNova64) +board x 0x286 0T (Hydra64 (Nova)) +board x 0x287 0T 887/897/GHI70 (Hydra96 (Nova)) +board x 0x288 0T 887/897/GHI60 (TNova96) -board HP817 0x280 817/827/957/957LX/FH20 (Nova Low) -board HP837 0x281 837/847/857/967/967LX/FGHI30 (Nova High) -board HP807 0x282 807/917/917LX/927/927LX/937/937LX/947/947LX/F10 (Nova8) -board HP867 0x283 867/877/977/GHI40 (Nova64) -board HP887T 0x284 887/897/987/GHI50 (TNova) -#board HP 0x285 (TNova64) -#board HP 0x286 (Hydra64 (Nova)) -board HP887 0x287 887/897/GHI70 (Hydra96 (Nova)) -board HP887T96 0x288 887/897/GHI60 (TNova96) +board x 0x300 S 710/50 (Bushmaster) +board x 0x302 S 705/35 (Flounder) -board HP710 0x300 710/50 (Bushmaster) -board HP705 0x302 705/35 (Flounder) +board x 0x310 0T 715/50 (Scorpio) +board x 0x311 0T 715/33 (Scorpio Jr.) +board x 0x312 0T 715S/50 (Spider-50) +board x 0x313 0T 715S/33 (Spider-33) +board x 0x314 0T 715T/50 (Trailways-50) +board x 0x315 0T 715T/33 (Trailways-33) +board x 0x316 0T 715/75 (Scorpio Sr.) +board x 0x317 0T 715/99 (Scorpio 100) +board x 0x318 0T 725/50 (Spectra) +board x 0x319 0T 725/75 (Spectra) -board HP715_50 0x310 715/50 (Scorpio) -board HP715_33 0x311 715/33 (Scorpio Jr.) -board HP715S_50 0x312 715S/50 (Spider-50) -board HP715S_33 0x313 715S/33 (Spider-33) -board HP715T_50 0x314 715T/50 (Trailways-50) -board HP715T_33 0x315 715T/33 (Trailways-33) -board HP715_75 0x316 715/75 (Scorpio Sr.) -board HP715_99 0x317 715/99 (Scorpio 100) -board HP725_50 0x318 725/50 (Spectra) -board HP725_75 0x319 725/75 (Spectra) +board x 0x320 0T 725/100 (Spectra) -#board HP725_100 0x320 725/100 (Spectra) +board x 0x401 0T 745i/747i/50 (Pace) +board x 0x402 0T 742i/50 (Sidewinder) +board x 0x403 0T 745i/747i/100 (Fast Pace) -board HP745i_50 0x401 745i/747i/50 (Pace) -board HP742i_50 0x402 742i/50 (Sidewinder) -board HP747i_100 0x403 745i/747i/100 (Fast Pace) +board x 0x480 L 806/E23 (Orville) +board x 0x481 L E25 (Wilbur) +board x 0x482 L 816/E35 (Wright Brothers 80) +board x 0x483 L 826/E45 (Wright Brothers 96) +board x 0x484 L 811/D210/D310 (UltraLight Proc L-100) +board x 0x485 L 801/D200/D300 (UltraLight Proc L-75) -board HPE23 0x480 806/E23 (Orville) -board HPE25 0x481 E25 (Wilbur) -board HPE35 0x482 816/E35 (Wright Brothers 80) -board HPE45 0x483 826/E45 (Wright Brothers 96) -board HPD210 0x484 811/D210/D310 (UltraLight Proc L-100) -board HPD200 0x485 801/D200/D300 (UltraLight Proc L-75) +board x 0x501 L2 778/B132L (Merlin L2 132) +board x 0x502 L2 778/B160L (Merlin L2 160) +board x 0x503 L2 778/B132L (Merlin L2+ 132) +board x 0x504 L2 778/B180L (Merlin L2+ 180) +board x 0x505 L2 779/C132L (Raven L2 132) +board x 0x506 L2 779/C160L (Raven L2 160) +board x 0x507 L2 779/C160L (Raven L2 180) +board x 0x508 L2 779/C160L (Raven L2 160) +board x 0x509 L2 712/132 (L2 Upgrade) +board x 0x50a L2 712/160 (L2 Upgrade) +board x 0x50b L2 712/132 (L2 Upgrade) +board x 0x50c L2 712/160 (L2 Upgrade) +board x 0x50d L2 (Rocky2 L2 120) +board x 0x50e L2 (Rocky2 L2 150) +board x 0x50f L2 744/132L (Anole-132L) +board x 0x510 L2 744/165L (Anole-165L) +board x 0x511 L2 (Kiji L2 132) +board x 0x512 L2 803/D220/D320 (UltraLight L2 132) +board x 0x513 L2 813/D220/D320 (UltraLight L2 160) +board x 0x514 L2 (Merlin Jr. L2 132) +board x 0x515 L2 (Staccato L2 132) +board x 0x516 L2 800/A180 (Staccato L2 180) -board HP778_B132L 0x501 778/B132L (Merlin L2 132) -board HP778_B160L 0x502 778/B160L (Merlin L2 160) -board HP778_B132LP 0x503 778/B132L (Merlin L2+ 132) -board HP778_B180L 0x504 778/B180L (Merlin L2+ 180) -board HP779_C132L 0x505 779/C132L (Raven L2 132) -board HP779_C160L 0x506 779/C160L (Raven L2 160) -board HP779_C180L 0x507 779/C160L (Raven L2 180) -board HP779_C160L1 0x508 779/C160L (Raven L2 160) -board HP712_132L2 0x509 712/132 (L2 Upgrade) -board HP712_160L2 0x50a 712/160 (L2 Upgrade) -board HP712_132L21 0x50b 712/132 (L2 Upgrade) -board HP712_160L21 0x50c 712/160 (L2 Upgrade) -#board HP 0x50d (Rocky2 L2 120) -#board HP 0x50e (Rocky2 L2 150) -board HP744_132L 0x50f 744/132L (Anole-132L) -board HP744_165L 0x510 744/165L (Anole-165L) -#board HPKIJI132 0x511 (Kiji L2 132) -board HP803 0x512 803/D220/D320 (UltraLight L2 132) -board HP813 0x513 813/D220/D320 (UltraLight L2 160) -#board HP 0x514 (Merlin Jr. L2 132) -#board HP 0x515 (Staccato L2 132) -board HP800 0x516 800/A180 (Staccato L2 180) +board x 0x580 T' 809/K100 (KittyHawk DC2-100) +board x 0x581 T' 839/K210 (KittyHawk DC3-120) +board x 0x582 T' 829/K400 (KittyHawk DC3-100) +board x 0x583 T' 849/K410 (KittyHawk DC3-120) +board x 0x584 T' T120 (LighteningHawk) +board x 0x585 T' 770/J200 (SkyHawk 100) +board x 0x586 T' 770/J210 (SkyHawk 120) +board x 0x587 T' 841/D210/D410 (UltraLight Proc 1-way T'120) +board x 0x588 T' 851/D210-2/D410-2 (UltraLight Proc 2-way T'120) +board x 0x589 T' 821/D200/D400 (UltraLight Proc 1-way T'100) +board x 0x58a T' 831/D200-2/D400-2 (UltraLight Proc 2-way T'100) +board x 0x58b T' 819/K200 (KittyHawk DC2 100) +board x 0x58c T' 859/K220 (ThunderHawk DC3- 120 1M) +board x 0x58d T' 869/K420 (ThunderHawk DC3 120 1M) +board x 0x58e T' (Raven 120 T') -board HP809 0x580 809/K100 (KittyHawk DC2-100) -board HP839 0x581 839/K210 (KittyHawk DC3-120) -board HP829 0x582 829/K400 (KittyHawk DC3-100) -board HP849 0x583 849/K410 (KittyHawk DC3-120) -board HPT120 0x584 T120 (LighteningHawk) -board HP770_J200 0x585 770/J200 (SkyHawk 100) -board HP770_J210 0x586 770/J210 (SkyHawk 120) -board HP841 0x587 841/D210/D410 (UltraLight Proc 1-way T'120) -board HP851 0x588 851/D210-2/D410-2 (UltraLight Proc 2-way T'120) -board HP821_1 0x589 821/D200/D400 (UltraLight Proc 1-way T'100) -board HP831 0x58a 831/D200-2/D400-2 (UltraLight Proc 2-way T'100) -board HP819 0x58b 819/K200 (KittyHawk DC2 100) -board HP859 0x58c 859/K220 (ThunderHawk DC3- 120 1M) -board HP869 0x58d 869/K420 (ThunderHawk DC3 120 1M) -#board HP 0x58E (Raven 120 T') -board HP889 0x58f 889/K450 (Mohawk 160 U 1M DC3) -board HP889_1 0x590 889/K460 (Mohawk 180 U 1M DC3) -#board HP 0x591 (Mohawk 200 U 1M DC3) -#board HP 0x592 (Raven 100 T') -#board HP 0x593 (FireHawk 160 U) -board HP780 0x594 780/J282 (FireHawk 180 U) -#board HP 0x595 (FireHawk 220 U) -#board HP 0x596 (FireHawk 240 U) -board HP800V 0x597 800/V2200/V2500 (SPP2000) -board HP780_C230 0x598 780/C230 (Raven U 230) -board HP780_C240 0x599 780/C240 (Raven U 240) +board x 0x58f U 889/K450 (Mohawk 160 U 1M DC3) +board x 0x590 U 889/K460 (Mohawk 180 U 1M DC3) +board x 0x591 U (Mohawk 200 U 1M DC3) +board x 0x592 T' (Raven 100 T') +board x 0x593 U (FireHawk 160 U) +board x 0x594 U 780/J282 (FireHawk 180 U) +board x 0x595 U (FireHawk 220 U) +board x 0x596 U (FireHawk 240 U) +board x 0x597 U 800/V2200/V2500 (SPP2000) +board x 0x598 U 780/C230 (Raven U 230) +board x 0x599 U+ 780/C240 (Raven U 240) # 0x59a -board HP780_C160 0x59b 780/C160 (Raven U 160) -board HP780_C180 0x59c 780/C180 (Raven U 180) -board HP780_C200 0x59d 780/C200 (Raven U 200) -#board HP 0x59e (ThunderHawk T' 120) -board HP780_C180P 0x59f 780/C180+ (Raven U 180+) -board HP841_1 0x5a0 841/D260/D360 (UltraLight 1-way T120 1MB) -board HP851_1 0x5a1 851/D260/D360 (UltraLight 2-way T120 1MB) -board HP861 0x5a2 861/D270/D370 (UltraLight 1-way U160 512K) -board HP871 0x5a3 871/D270/D370 (UltraLight 2-way U160 512K) -board HP802 0x5a4 802/K250 (MoHawk U160 1M DC3-) -board HP879 0x5a5 879/K260 (MoHawk U180 1M DC3-) -#board HP 0x5a6 (MoHawk U200 1M DC3-) -#board HP 0x5a7 (UltraLight 1-way U160 1M) -#board HP 0x5a8 (UltraLight 2-way U160 1M) -board HP810D 0x5a9 810/D380/R380 (UltraLight 1-way U180 1M) -board HP820 0x5aa 820/D280 (UltraLight 2-way U180 1M) +board x 0x59b U 780/C160 (Raven U 160) +board x 0x59c U 780/C180 (Raven U 180) +board x 0x59d U+ 780/C200 (Raven U 200) +board x 0x59e T' (ThunderHawk T' 120) +board x 0x59f U 780/C180+ (Raven U 180+) +board x 0x5a0 T' 841/D260/D360 (UltraLight 1-way T120 1MB) +board x 0x5a1 T' 851/D260/D360 (UltraLight 2-way T120 1MB) +board x 0x5a2 U 861/D270/D370 (UltraLight 1-way U160 512K) +board x 0x5a3 U 871/D270/D370 (UltraLight 2-way U160 512K) +board x 0x5a4 U 802/K250 (MoHawk U160 1M DC3-) +board x 0x5a5 U 879/K260 (MoHawk U180 1M DC3-) +board x 0x5a6 U (MoHawk U200 1M DC3-) +board x 0x5a7 U (UltraLight 1-way U160 1M) +board x 0x5a8 U (UltraLight 2-way U160 1M) +board x 0x5a9 U 810/D380/R380 (UltraLight 1-way U180 1M) +board x 0x5aa U 820/D280 (UltraLight 2-way U180 1M) # 0x5ab obsolete # 0x5ac obsolete -#board HP 0x5ad (BraveHawk 180 DC3-) -board HP898 0x5ae 898/K370 (BraveHawk 200 DC3-) -#board HP 0x5af (BraveHawk 220 DC3-) -#board HP 0x5b0 (BraveHawk 180 DC3) -board HP899 0x5b1 899/K570 (BraveHawk 200 DC3) -#board HP 0x5b2 (BraveHawk 220 DC3) -#board HP 0x5b3 (FireHawk 200) -board HP800V2 0x5b4 800/V2500 (SPP2500) -board HP782 0x5b5 782/J2240 (SummitHawk U+) -board HP800K 0x5b6 800/K380 (DragonHawk U+ 240 DC3) -#board HP 0x5b7 (DragonHawk U+ 240 DC3-) -#board 0x5b8 SPP2250 240MHz processor -board HP821 0x5b9 821/D350/R350 (UltraLight 1w U+/240) -board HP800D 0x5ba 800/D390/R390 (UltraLight 2w U+/240) -board HP785C 0x5bb 785/C3000 (AllegroHigh W) -board HP785B 0x5bc 785/B1000 (AllegroLow W) -board HP785J 0x5bd 785/J5000 (Forte W 2w) -board HP800N 0x5be 800/N4000-36 (Prelude W) -#board 0x5bf (Forte W 4w) -#board 0x5c0 (M2250) -#board 0x5c1 (M2500) -#board 0x5c2 (Sonata 440) -#board 0x5c3 (Sonata 360) -board HP800L2 0x5c4 800/L2000-44 (Rhapsody 440) -#board 0x5c5 (Rhapsody 360) -board HP785C_1 0x5c6 780/C360 (Raven W 360) -#board 0x5c7 (Halftone W 440) -#board 0x5c8 (Lego 360) -board HP800L 0x5c9 800/L1000-44 (Rhapsody DC-440) -#board 0x5ca (Rhapsody DC- 360) -#board 0x5cb (Crescendo 440) -#board 0x5cc (Prelude W 440) -#board 0x5cd SPP2600 -#board 0x5ce M2600 -#board 0x5cf 785 (Allegro) -#board 0x5d0 (Kazoo W+) -#board 0x5d1 (Forte W+ 2w) -#board 0x5d2 (Forte W+ 4w) -#board 0x5d3 (Prelude W+ 550) -#board 0x5d4 (Duet W+) -#board 0x5d5 (Crescendo 550) -#board 0x5d6 (Crescendo DC-440) -#board 0x5d7 (Keystone W+) -#board 0x5d8 (Rhapsody wave 2 W+ DC-) -#board 0x5d9 (Rhapsody wave 2 W+) -#board 0x5da (Marcato W+ DC-) -#board 0x5db (Marcato W+) -#board 0x5de (Piccolo W+) +board x 0x5ad U+ (BraveHawk 180 DC3-) +board x 0x5ae U+ 898/K370 (BraveHawk 200 DC3-) +board x 0x5af U+ (BraveHawk 220 DC3-) +board x 0x5b0 U+ (BraveHawk 180 DC3) +board x 0x5b1 U+ 899/K570 (BraveHawk 200 DC3) +board x 0x5b2 U+ (BraveHawk 220 DC3) +board x 0x5b3 U (FireHawk 200) +board x 0x5b4 W 800/V2500 (SPP2500) +board x 0x5b5 U+ 782/J2240 (SummitHawk U+) +board x 0x5b6 U+ 800/K380 (DragonHawk U+ 240 DC3) +board x 0x5b7 U+ (DragonHawk U+ 240 DC3-) +board x 0x5b8 U+ SPP2250 240MHz processor +board x 0x5b9 U+ 821/D350/R350 (UltraLight 1w U+/240) +board x 0x5ba U+ 800/D390/R390 (UltraLight 2w U+/240) +board x 0x5bb W 785/C3000 (AllegroHigh W) +board x 0x5bc W 785/B1000 (AllegroLow W) +board x 0x5bd W 785/J5000 (Forte W 2w) +board x 0x5be W 800/N4000-36 (Prelude W) +board x 0x5bf W (Forte W 4w) +board x 0x5c0 W (M2250) +board x 0x5c1 W (M2500) +board x 0x5c2 W (Sonata 440) +board x 0x5c3 W (Sonata 360) +board x 0x5c4 W 800/L2000-44 (Rhapsody 440) +board x 0x5c5 W (Rhapsody 360) +board x 0x5c6 W 780/C360 (Raven W 360) +board x 0x5c7 W+ (Halftone W 440) +board x 0x5c8 W (Lego 360) +board x 0x5c9 W 800/L1000-44 (Rhapsody DC-440) +board x 0x5ca W (Rhapsody DC- 360) +board x 0x5cb W (Crescendo 440) +board x 0x5cc W (Prelude W 440) +board x 0x5cd W SPP2600 +board x 0x5ce W+ M2600 +board x 0x5cf W+ 785 (Allegro) +board x 0x5d0 W+ (Kazoo W+) +board x 0x5d1 W+ (Forte W+ 2w) +board x 0x5d2 W+ (Forte W+ 4w) +board x 0x5d3 W+ (Prelude W+ 550) +board x 0x5d4 W+ (Duet W+) +board x 0x5d5 W+ (Crescendo 550) +board x 0x5d6 W (Crescendo DC-440) +board x 0x5d7 W+ (Keystone W+) +board x 0x5d8 W+ (Rhapsody wave 2 W+ DC-) +board x 0x5d9 W+ (Rhapsody wave 2 W+) +board x 0x5da W+ (Marcato W+ DC-) +board x 0x5db W+ (Marcato W+) +board x 0x5de W+ (Piccolo W+) -board HITACHIW 0x5ff (Hitachi W) +board x 0x5ff W+ (Hitachi W) -board HP712_60 0x600 712/60 (Gecko) -board HP712_80 0x601 712/80 (King Gecko) -board HP712_100 0x602 712/100 (King Gecko) -board HP743i_64 0x603 743i/64 (Anole-64) -board HP743i_100 0x604 743i/100 (Anole-100) -board HP712_120 0x605 712/120 (King Gecko) -#board HP 0x606 (Gila 80) -#board HP 0x607 (Gila 100) -#board HP 0x608 (Gila 120) -board HP715_80 0x609 715/80 (Scorpio-L) -board HP715_64 0x60A 715/64 (Mirage Jr.) -board HP715_100 0x60B 715/100 (Mirage Sr.) -board HP715_100XC 0x60C 715/100XC (Mirage Sr.) -board HP725_100 0x60D 725/100 (Electra) -board HP725_120 0x60E 725/120 (Electra) -board HP715_100L 0x610 715/100L (Scorpio-L) -board HP715_120L 0x611 715/120L (Scorpio-L) -board HP725_80L 0x612 725/80L (Spectra-L) -board HP725_100L 0x613 725/100L (Spectra-L) -board HP725_120L 0x614 725/120L (Spectra-L) -#board HP 0x615 /100 (Piranha) -#board HP 0x616 /120 (Piranha) -board HP743_50 0x617 743/50 (Jason) -board HP743_100 0x618 743/100 (Jason) -board HP715_80M 0x619 715/80 (Mirage) -board HP811 0x61a 811/DX5 (SAIC L-80) -board HP801 0x61b 801/DX0 (Rocky1 L-80) -board HP743T 0x61c 743T (Anole T) +board x 0x600 L 712/60 (Gecko) +board x 0x601 L 712/80 (King Gecko) +board x 0x602 L 712/100 (King Gecko) +board x 0x603 L 743i/64 (Anole-64) +board x 0x604 L 743i/100 (Anole-100) +board x 0x605 L 712/120 (King Gecko) +board x 0x606 L (Gila 80) +board x 0x607 L (Gila 100) +board x 0x608 L (Gila 120) +board x 0x609 L 715/80 (Scorpio-L) +board x 0x60A L 715/64 (Mirage Jr.) +board x 0x60B L 715/100 (Mirage Sr.) +board x 0x60C L 715/100XC (Mirage Sr.) +board x 0x60D L 725/100 (Electra) +board x 0x60E L 725/120 (Electra) +board x 0x610 L 715/100L (Scorpio-L) +board x 0x611 L 715/120L (Scorpio-L) +board x 0x612 L 725/80L (Spectra-L) +board x 0x613 L 725/100L (Spectra-L) +board x 0x614 L 725/120L (Spectra-L) +board x 0x615 L Piranha 100 +board x 0x616 L Piranha 120 +board x 0x617 L 743/50 (Jason) +board x 0x618 L 743/100 (Jason) +board x 0x619 L 715/80 (Mirage) +board x 0x61a L 811/DX5 (SAIC L-80) +board x 0x61b L 801/DX0 (Rocky1 L-80) +board x 0x61c L 743T (Anole T) -#board HITACHIT80 0x67e (Hitachi Tiny 80) -#board HITACHIT64 0x67f (Hitachi Tiny 64) +board x 0x67e L (Hitachi Tiny 80) +board x 0x67f L (Hitachi Tiny 64) -#board NEC 0x700 (NEC Aska) +#board x 0x700 (NEC Aska) # IODC_HVERSION[0..4] bus MID_BUS 0 MID_BUS @@ -304,11 +322,11 @@ bus ROPES 15 Ropes bus MERCED 16 Merced cpu SOFTEMU 0x01 Software Emulation -cpu PCXT 0x0b Tornado +cpu TORNADO 0x0b Tornado cpu PCXL 0x0d PA7100LC -cpu PCXUP 0x0e PA8000 +cpu PCXU 0x0e PA8000 cpu PCXL2 0x0f PA7300LC -cpu PCXUP1 0x10 PA8200 +cpu PCXUP 0x10 PA8200 cpu PCXW 0x11 PA8500 fpu SOFTEMU 0x01 Software Emulation diff --git a/sys/arch/hp700/dev/cpudevs.h b/sys/arch/hp700/dev/cpudevs.h index 8973575c4ace..e666ce5628b4 100644 --- a/sys/arch/hp700/dev/cpudevs.h +++ b/sys/arch/hp700/dev/cpudevs.h @@ -1,10 +1,10 @@ -/* $NetBSD: cpudevs.h,v 1.1 2002/06/06 19:48:03 fredette Exp $ */ +/* $NetBSD: cpudevs.h,v 1.2 2002/08/05 20:58:36 fredette Exp $ */ -/* - * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. - * generated from: - * OpenBSD: cpudevs,v 1.18 2001/03/20 08:15:22 mickey Exp - */ +/* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. */ + +/* generated from: NetBSD: cpudevs,v 1.1 2002/06/06 19:48:03 fredette Exp */ + +/* generated from: OpenBSD: cpudevs,v 1.18 2001/03/20 08:15:22 mickey Exp */ #define HPPA_TYPE_NPROC 0x00 #define HPPA_TYPE_MEMORY 0x01 @@ -26,151 +26,7 @@ #define HPPA_TYPE_CPU 0x81 #define HPPA_TYPE_FPU 0x82 #define HPPA_TYPE_BUS 0x83 -#define HPPA_BOARD_HP840 0x004 -#define HPPA_BOARD_HP825 0x008 -#define HPPA_BOARD_HP835 0x00a -#define HPPA_BOARD_HP845 0x00b -#define HPPA_BOARD_HP850 0x00C -#define HPPA_BOARD_HP949 0x00f -#define HPPA_BOARD_HP950S 0x080 -#define HPPA_BOARD_HP855 0x081 -#define HPPA_BOARD_HP860 0x082 -#define HPPA_BOARD_HP870 0x083 -#define HPPA_BOARD_HP810 0x100 -#define HPPA_BOARD_HP822 0x101 -#define HPPA_BOARD_HP832 0x102 -#define HPPA_BOARD_HP808 0x103 -#define HPPA_BOARD_HP842 0x104 -#define HPPA_BOARD_HP852 0x105 -#define HPPA_BOARD_HPOBOE 0x106 -#define HPPA_BOARD_HPDRAGON 0x180 -#define HPPA_BOARD_HP890 0x181 -#define HPPA_BOARD_HP891 0x182 -#define HPPA_BOARD_HP892 0x183 -#define HPPA_BOARD_HP893_T540 0x184 -#define HPPA_BOARD_HPHXPROC 0x1ff -#define HPPA_BOARD_HP720 0x200 -#define HPPA_BOARD_HP750_66 0x201 -#define HPPA_BOARD_HP730_66 0x202 -#define HPPA_BOARD_HP735_99 0x203 -#define HPPA_BOARD_HP755_99 0x204 #define HPPA_BOARD_HP755_125 0x205 -#define HPPA_BOARD_HP735_130 0x206 -#define HPPA_BOARD_HP817 0x280 -#define HPPA_BOARD_HP837 0x281 -#define HPPA_BOARD_HP807 0x282 -#define HPPA_BOARD_HP867 0x283 -#define HPPA_BOARD_HP887T 0x284 -#define HPPA_BOARD_HP887 0x287 -#define HPPA_BOARD_HP887T96 0x288 -#define HPPA_BOARD_HP710 0x300 -#define HPPA_BOARD_HP705 0x302 -#define HPPA_BOARD_HP715_50 0x310 -#define HPPA_BOARD_HP715_33 0x311 -#define HPPA_BOARD_HP715S_50 0x312 -#define HPPA_BOARD_HP715S_33 0x313 -#define HPPA_BOARD_HP715T_50 0x314 -#define HPPA_BOARD_HP715T_33 0x315 -#define HPPA_BOARD_HP715_75 0x316 -#define HPPA_BOARD_HP715_99 0x317 -#define HPPA_BOARD_HP725_50 0x318 -#define HPPA_BOARD_HP725_75 0x319 -#define HPPA_BOARD_HP745I_50 0x401 -#define HPPA_BOARD_HP742I_50 0x402 -#define HPPA_BOARD_HP747I_100 0x403 -#define HPPA_BOARD_HPE23 0x480 -#define HPPA_BOARD_HPE25 0x481 -#define HPPA_BOARD_HPE35 0x482 -#define HPPA_BOARD_HPE45 0x483 -#define HPPA_BOARD_HPD210 0x484 -#define HPPA_BOARD_HPD200 0x485 -#define HPPA_BOARD_HP778_B132L 0x501 -#define HPPA_BOARD_HP778_B160L 0x502 -#define HPPA_BOARD_HP778_B132LP 0x503 -#define HPPA_BOARD_HP778_B180L 0x504 -#define HPPA_BOARD_HP779_C132L 0x505 -#define HPPA_BOARD_HP779_C160L 0x506 -#define HPPA_BOARD_HP779_C180L 0x507 -#define HPPA_BOARD_HP779_C160L1 0x508 -#define HPPA_BOARD_HP712_132L2 0x509 -#define HPPA_BOARD_HP712_160L2 0x50a -#define HPPA_BOARD_HP712_132L21 0x50b -#define HPPA_BOARD_HP712_160L21 0x50c -#define HPPA_BOARD_HP744_132L 0x50f -#define HPPA_BOARD_HP744_165L 0x510 -#define HPPA_BOARD_HP803 0x512 -#define HPPA_BOARD_HP813 0x513 -#define HPPA_BOARD_HP800 0x516 -#define HPPA_BOARD_HP809 0x580 -#define HPPA_BOARD_HP839 0x581 -#define HPPA_BOARD_HP829 0x582 -#define HPPA_BOARD_HP849 0x583 -#define HPPA_BOARD_HPT120 0x584 -#define HPPA_BOARD_HP770_J200 0x585 -#define HPPA_BOARD_HP770_J210 0x586 -#define HPPA_BOARD_HP841 0x587 -#define HPPA_BOARD_HP851 0x588 -#define HPPA_BOARD_HP821_1 0x589 -#define HPPA_BOARD_HP831 0x58a -#define HPPA_BOARD_HP819 0x58b -#define HPPA_BOARD_HP859 0x58c -#define HPPA_BOARD_HP869 0x58d -#define HPPA_BOARD_HP889 0x58f -#define HPPA_BOARD_HP889_1 0x590 -#define HPPA_BOARD_HP780 0x594 -#define HPPA_BOARD_HP800V 0x597 -#define HPPA_BOARD_HP780_C230 0x598 -#define HPPA_BOARD_HP780_C240 0x599 -#define HPPA_BOARD_HP780_C160 0x59b -#define HPPA_BOARD_HP780_C180 0x59c -#define HPPA_BOARD_HP780_C200 0x59d -#define HPPA_BOARD_HP780_C180P 0x59f -#define HPPA_BOARD_HP841_1 0x5a0 -#define HPPA_BOARD_HP851_1 0x5a1 -#define HPPA_BOARD_HP861 0x5a2 -#define HPPA_BOARD_HP871 0x5a3 -#define HPPA_BOARD_HP802 0x5a4 -#define HPPA_BOARD_HP879 0x5a5 -#define HPPA_BOARD_HP810D 0x5a9 -#define HPPA_BOARD_HP820 0x5aa -#define HPPA_BOARD_HP898 0x5ae -#define HPPA_BOARD_HP899 0x5b1 -#define HPPA_BOARD_HP800V2 0x5b4 -#define HPPA_BOARD_HP782 0x5b5 -#define HPPA_BOARD_HP800K 0x5b6 -#define HPPA_BOARD_HP821 0x5b9 -#define HPPA_BOARD_HP800D 0x5ba -#define HPPA_BOARD_HP785C 0x5bb -#define HPPA_BOARD_HP785B 0x5bc -#define HPPA_BOARD_HP785J 0x5bd -#define HPPA_BOARD_HP800N 0x5be -#define HPPA_BOARD_HP800L2 0x5c4 -#define HPPA_BOARD_HP785C_1 0x5c6 -#define HPPA_BOARD_HP800L 0x5c9 -#define HPPA_BOARD_HITACHIW 0x5ff -#define HPPA_BOARD_HP712_60 0x600 -#define HPPA_BOARD_HP712_80 0x601 -#define HPPA_BOARD_HP712_100 0x602 -#define HPPA_BOARD_HP743I_64 0x603 -#define HPPA_BOARD_HP743I_100 0x604 -#define HPPA_BOARD_HP712_120 0x605 -#define HPPA_BOARD_HP715_80 0x609 -#define HPPA_BOARD_HP715_64 0x60A -#define HPPA_BOARD_HP715_100 0x60B -#define HPPA_BOARD_HP715_100XC 0x60C -#define HPPA_BOARD_HP725_100 0x60D -#define HPPA_BOARD_HP725_120 0x60E -#define HPPA_BOARD_HP715_100L 0x610 -#define HPPA_BOARD_HP715_120L 0x611 -#define HPPA_BOARD_HP725_80L 0x612 -#define HPPA_BOARD_HP725_100L 0x613 -#define HPPA_BOARD_HP725_120L 0x614 -#define HPPA_BOARD_HP743_50 0x617 -#define HPPA_BOARD_HP743_100 0x618 -#define HPPA_BOARD_HP715_80M 0x619 -#define HPPA_BOARD_HP811 0x61a -#define HPPA_BOARD_HP801 0x61b -#define HPPA_BOARD_HP743T 0x61c #define HPPA_BUS_MID_BUS 0 #define HPPA_BUS_SMB 1 #define HPPA_BUS_HPPB 2 @@ -189,11 +45,11 @@ #define HPPA_BUS_ROPES 15 #define HPPA_BUS_MERCED 16 #define HPPA_CPU_SOFTEMU 0x01 -#define HPPA_CPU_PCXT 0x0b +#define HPPA_CPU_TORNADO 0x0b #define HPPA_CPU_PCXL 0x0d -#define HPPA_CPU_PCXUP 0x0e +#define HPPA_CPU_PCXU 0x0e #define HPPA_CPU_PCXL2 0x0f -#define HPPA_CPU_PCXUP1 0x10 +#define HPPA_CPU_PCXUP 0x10 #define HPPA_CPU_PCXW 0x11 #define HPPA_FPU_SOFTEMU 0x01 #define HPPA_FPU_INDIGO 0x02 diff --git a/sys/arch/hp700/dev/cpudevs_data.h b/sys/arch/hp700/dev/cpudevs_data.h index db66a453aed9..9e5ccfe9d79d 100644 --- a/sys/arch/hp700/dev/cpudevs_data.h +++ b/sys/arch/hp700/dev/cpudevs_data.h @@ -1,156 +1,215 @@ -/* $NetBSD: cpudevs_data.h,v 1.1 2002/06/06 19:48:03 fredette Exp $ */ +/* $NetBSD: cpudevs_data.h,v 1.2 2002/08/05 20:58:36 fredette Exp $ */ -/* - * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. - * generated from: - * OpenBSD: cpudevs,v 1.18 2001/03/20 08:15:22 mickey Exp - */ +/* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. */ -{HPPA_TYPE_BOARD, HPPA_BOARD_HP840, "840/930 (Indigo)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP825, "825/925 (FireFox)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP835, "83[45]/[69]35 (TopGun)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP845, "845/645 (Technical ShoGun)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP850, "850/950 (Cheetah)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP949, "949 (Commercial ShoGun)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP950S, "950S (Cheetah)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP855, "855/955 (Jaguar)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP860, "860/960 (Cougar)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP870, "865/870/980 (Panther)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP810, "810 (Burgundy)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP822, "822/922 (SilverFox Low)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP832, "832/932 (SilverFox High)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP808, "808/815/920 (Lego, SilverLite)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP842, "842/948 (SilverBullet Low)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP852, "852/958 (SilverBullet High)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HPOBOE, "(Oboe)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HPDRAGON, "(Dragon)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP890, "890/990/992 (Chimera)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP891, "891/T500 (TNT 100)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP892, "892/T520 (TNT 120)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP893_T540, "893/T540 (Jade 180 U)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HPHXPROC, "Hitachi X Processor" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP720, "720 (Cobra)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP750_66, "750/66 (Coral)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP730_66, "730/66 (King Cobra)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP735_99, "735/99 (Hardball)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP755_99, "755/99 (Coral II)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP755_125, "755/125 (Coral II)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP735_130, "735/130 (Snake Cheetah)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP817, "817/827/957/957LX/FH20 (Nova Low)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP837, "837/847/857/967/967LX/FGHI30 (Nova High)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP807, "807/917/917LX/927/927LX/937/937LX/947/947LX/F10 (Nova8)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP867, "867/877/977/GHI40 (Nova64)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP887T, "887/897/987/GHI50 (TNova)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP887, "887/897/GHI70 (Hydra96 (Nova))" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP887T96, "887/897/GHI60 (TNova96)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP710, "710/50 (Bushmaster)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP705, "705/35 (Flounder)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715_50, "715/50 (Scorpio)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715_33, "715/33 (Scorpio Jr.)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715S_50, "715S/50 (Spider-50)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715S_33, "715S/33 (Spider-33)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715T_50, "715T/50 (Trailways-50)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715T_33, "715T/33 (Trailways-33)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715_75, "715/75 (Scorpio Sr.)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715_99, "715/99 (Scorpio 100)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP725_50, "725/50 (Spectra)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP725_75, "725/75 (Spectra)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP745I_50, "745i/747i/50 (Pace)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP742I_50, "742i/50 (Sidewinder)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP747I_100, "745i/747i/100 (Fast Pace)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HPE23, "806/E23 (Orville)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HPE25, "E25 (Wilbur)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HPE35, "816/E35 (Wright Brothers 80)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HPE45, "826/E45 (Wright Brothers 96)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HPD210, "811/D210/D310 (UltraLight Proc L-100)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HPD200, "801/D200/D300 (UltraLight Proc L-75)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP778_B132L, "778/B132L (Merlin L2 132)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP778_B160L, "778/B160L (Merlin L2 160)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP778_B132LP, "778/B132L (Merlin L2+ 132)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP778_B180L, "778/B180L (Merlin L2+ 180)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP779_C132L, "779/C132L (Raven L2 132)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP779_C160L, "779/C160L (Raven L2 160)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP779_C180L, "779/C160L (Raven L2 180)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP779_C160L1, "779/C160L (Raven L2 160)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP712_132L2, "712/132 (L2 Upgrade)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP712_160L2, "712/160 (L2 Upgrade)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP712_132L21, "712/132 (L2 Upgrade)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP712_160L21, "712/160 (L2 Upgrade)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP744_132L, "744/132L (Anole-132L)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP744_165L, "744/165L (Anole-165L)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP803, "803/D220/D320 (UltraLight L2 132)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP813, "813/D220/D320 (UltraLight L2 160)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP800, "800/A180 (Staccato L2 180)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP809, "809/K100 (KittyHawk DC2-100)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP839, "839/K210 (KittyHawk DC3-120)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP829, "829/K400 (KittyHawk DC3-100)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP849, "849/K410 (KittyHawk DC3-120)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HPT120, "T120 (LighteningHawk)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP770_J200, "770/J200 (SkyHawk 100)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP770_J210, "770/J210 (SkyHawk 120)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP841, "841/D210/D410 (UltraLight Proc 1-way T'120)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP851, "851/D210-2/D410-2 (UltraLight Proc 2-way T'120)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP821_1, "821/D200/D400 (UltraLight Proc 1-way T'100)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP831, "831/D200-2/D400-2 (UltraLight Proc 2-way T'100)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP819, "819/K200 (KittyHawk DC2 100)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP859, "859/K220 (ThunderHawk DC3- 120 1M)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP869, "869/K420 (ThunderHawk DC3 120 1M)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP889, "889/K450 (Mohawk 160 U 1M DC3)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP889_1, "889/K460 (Mohawk 180 U 1M DC3)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP780, "780/J282 (FireHawk 180 U)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP800V, "800/V2200/V2500 (SPP2000)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP780_C230, "780/C230 (Raven U 230)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP780_C240, "780/C240 (Raven U 240)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP780_C160, "780/C160 (Raven U 160)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP780_C180, "780/C180 (Raven U 180)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP780_C200, "780/C200 (Raven U 200)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP780_C180P, "780/C180+ (Raven U 180+)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP841_1, "841/D260/D360 (UltraLight 1-way T120 1MB)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP851_1, "851/D260/D360 (UltraLight 2-way T120 1MB)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP861, "861/D270/D370 (UltraLight 1-way U160 512K)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP871, "871/D270/D370 (UltraLight 2-way U160 512K)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP802, "802/K250 (MoHawk U160 1M DC3-)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP879, "879/K260 (MoHawk U180 1M DC3-)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP810D, "810/D380/R380 (UltraLight 1-way U180 1M)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP820, "820/D280 (UltraLight 2-way U180 1M)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP898, "898/K370 (BraveHawk 200 DC3-)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP899, "899/K570 (BraveHawk 200 DC3)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP800V2, "800/V2500 (SPP2500)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP782, "782/J2240 (SummitHawk U+)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP800K, "800/K380 (DragonHawk U+ 240 DC3)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP821, "821/D350/R350 (UltraLight 1w U+/240)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP800D, "800/D390/R390 (UltraLight 2w U+/240)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP785C, "785/C3000 (AllegroHigh W)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP785B, "785/B1000 (AllegroLow W)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP785J, "785/J5000 (Forte W 2w)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP800N, "800/N4000-36 (Prelude W)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP800L2, "800/L2000-44 (Rhapsody 440)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP785C_1, "780/C360 (Raven W 360)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP800L, "800/L1000-44 (Rhapsody DC-440)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HITACHIW, "(Hitachi W)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP712_60, "712/60 (Gecko)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP712_80, "712/80 (King Gecko)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP712_100, "712/100 (King Gecko)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP743I_64, "743i/64 (Anole-64)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP743I_100, "743i/100 (Anole-100)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP712_120, "712/120 (King Gecko)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715_80, "715/80 (Scorpio-L)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715_64, "715/64 (Mirage Jr.)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715_100, "715/100 (Mirage Sr.)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715_100XC, "715/100XC (Mirage Sr.)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP725_100, "725/100 (Electra)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP725_120, "725/120 (Electra)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715_100L, "715/100L (Scorpio-L)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715_120L, "715/120L (Scorpio-L)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP725_80L, "725/80L (Spectra-L)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP725_100L, "725/100L (Spectra-L)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP725_120L, "725/120L (Spectra-L)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP743_50, "743/50 (Jason)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP743_100, "743/100 (Jason)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP715_80M, "715/80 (Mirage)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP811, "811/DX5 (SAIC L-80)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP801, "801/DX0 (Rocky1 L-80)" }, -{HPPA_TYPE_BOARD, HPPA_BOARD_HP743T, "743T (Anole T)" }, +/* generated from: NetBSD: cpudevs,v 1.1 2002/06/06 19:48:03 fredette Exp */ + +/* generated from: OpenBSD: cpudevs,v 1.18 2001/03/20 08:15:22 mickey Exp */ + +{HPPA_TYPE_BOARD, 0x004, "X 840/930 (Indigo)" }, +{HPPA_TYPE_BOARD, 0x008, "X 825/925 (FireFox)" }, +{HPPA_TYPE_BOARD, 0x00a, "X 83[45]/[69]35 (TopGun)" }, +{HPPA_TYPE_BOARD, 0x00b, "X 845/645 (Technical ShoGun)" }, +{HPPA_TYPE_BOARD, 0x00c, "X 850/950 (Cheetah)" }, +{HPPA_TYPE_BOARD, 0x00f, "X 949 (Commercial ShoGun)" }, +{HPPA_TYPE_BOARD, 0x080, "X 950S (Cheetah)" }, +{HPPA_TYPE_BOARD, 0x081, "X 855/955 (Jaguar)" }, +{HPPA_TYPE_BOARD, 0x082, "X 860/960 (Cougar)" }, +{HPPA_TYPE_BOARD, 0x083, "X 865/870/980 (Panther)" }, +{HPPA_TYPE_BOARD, 0x100, "X 810 (Burgundy)" }, +{HPPA_TYPE_BOARD, 0x101, "X 822/922 (SilverFox Low)" }, +{HPPA_TYPE_BOARD, 0x102, "X 832/932 (SilverFox High)" }, +{HPPA_TYPE_BOARD, 0x103, "X 808/815/920 (Lego, SilverLite)" }, +{HPPA_TYPE_BOARD, 0x104, "X 842/948 (SilverBullet Low)" }, +{HPPA_TYPE_BOARD, 0x105, "X 852/958 (SilverBullet High)" }, +{HPPA_TYPE_BOARD, 0x106, "X (Oboe)" }, +{HPPA_TYPE_BOARD, 0x180, "X (Dragon)" }, +{HPPA_TYPE_BOARD, 0x181, "X 890/990/992 (Chimera)" }, +{HPPA_TYPE_BOARD, 0x182, "0T 891/T500 (TNT 100)" }, +{HPPA_TYPE_BOARD, 0x183, "0T 892/T520 (TNT 120)" }, +{HPPA_TYPE_BOARD, 0x184, "U 893/T540 (Jade 180 U)" }, +{HPPA_TYPE_BOARD, 0x1ff, "? Hitachi X Processor" }, +{HPPA_TYPE_BOARD, 0x200, "S 720 (Cobra)" }, +{HPPA_TYPE_BOARD, 0x201, "S 750/66 (Coral)" }, +{HPPA_TYPE_BOARD, 0x202, "S 730/66 (King Cobra)" }, +{HPPA_TYPE_BOARD, 0x203, "0T 735/99 (Hardball)" }, +{HPPA_TYPE_BOARD, 0x204, "0T 755/99 (Coral II)" }, +{HPPA_TYPE_BOARD, HPPA_BOARD_HP755_125, "0T 755/125 (Coral II)" }, +{HPPA_TYPE_BOARD, 0x206, "0T 735/130 (Snake Cheetah)" }, +{HPPA_TYPE_BOARD, 0x280, "S 817/827/957/957LX/FH20 (Nova Low)" }, +{HPPA_TYPE_BOARD, 0x281, "S 837/847/857/967/967LX/FGHI30 (Nova High)" }, +{HPPA_TYPE_BOARD, 0x282, "S 807/917/917LX/927/927LX/937/937LX/947/947LX/F10 (Nova8)" }, +{HPPA_TYPE_BOARD, 0x283, "S 867/877/977/GHI40 (Nova64)" }, +{HPPA_TYPE_BOARD, 0x284, "0T 887/897/987/GHI50 (TNova)" }, +{HPPA_TYPE_BOARD, 0x285, "0T (TNova64)" }, +{HPPA_TYPE_BOARD, 0x286, "0T (Hydra64 (Nova))" }, +{HPPA_TYPE_BOARD, 0x287, "0T 887/897/GHI70 (Hydra96 (Nova))" }, +{HPPA_TYPE_BOARD, 0x288, "0T 887/897/GHI60 (TNova96)" }, +{HPPA_TYPE_BOARD, 0x300, "S 710/50 (Bushmaster)" }, +{HPPA_TYPE_BOARD, 0x302, "S 705/35 (Flounder)" }, +{HPPA_TYPE_BOARD, 0x310, "0T 715/50 (Scorpio)" }, +{HPPA_TYPE_BOARD, 0x311, "0T 715/33 (Scorpio Jr.)" }, +{HPPA_TYPE_BOARD, 0x312, "0T 715S/50 (Spider-50)" }, +{HPPA_TYPE_BOARD, 0x313, "0T 715S/33 (Spider-33)" }, +{HPPA_TYPE_BOARD, 0x314, "0T 715T/50 (Trailways-50)" }, +{HPPA_TYPE_BOARD, 0x315, "0T 715T/33 (Trailways-33)" }, +{HPPA_TYPE_BOARD, 0x316, "0T 715/75 (Scorpio Sr.)" }, +{HPPA_TYPE_BOARD, 0x317, "0T 715/99 (Scorpio 100)" }, +{HPPA_TYPE_BOARD, 0x318, "0T 725/50 (Spectra)" }, +{HPPA_TYPE_BOARD, 0x319, "0T 725/75 (Spectra)" }, +{HPPA_TYPE_BOARD, 0x320, "0T 725/100 (Spectra)" }, +{HPPA_TYPE_BOARD, 0x401, "0T 745i/747i/50 (Pace)" }, +{HPPA_TYPE_BOARD, 0x402, "0T 742i/50 (Sidewinder)" }, +{HPPA_TYPE_BOARD, 0x403, "0T 745i/747i/100 (Fast Pace)" }, +{HPPA_TYPE_BOARD, 0x480, "L 806/E23 (Orville)" }, +{HPPA_TYPE_BOARD, 0x481, "L E25 (Wilbur)" }, +{HPPA_TYPE_BOARD, 0x482, "L 816/E35 (Wright Brothers 80)" }, +{HPPA_TYPE_BOARD, 0x483, "L 826/E45 (Wright Brothers 96)" }, +{HPPA_TYPE_BOARD, 0x484, "L 811/D210/D310 (UltraLight Proc L-100)" }, +{HPPA_TYPE_BOARD, 0x485, "L 801/D200/D300 (UltraLight Proc L-75)" }, +{HPPA_TYPE_BOARD, 0x501, "L2 778/B132L (Merlin L2 132)" }, +{HPPA_TYPE_BOARD, 0x502, "L2 778/B160L (Merlin L2 160)" }, +{HPPA_TYPE_BOARD, 0x503, "L2 778/B132L (Merlin L2+ 132)" }, +{HPPA_TYPE_BOARD, 0x504, "L2 778/B180L (Merlin L2+ 180)" }, +{HPPA_TYPE_BOARD, 0x505, "L2 779/C132L (Raven L2 132)" }, +{HPPA_TYPE_BOARD, 0x506, "L2 779/C160L (Raven L2 160)" }, +{HPPA_TYPE_BOARD, 0x507, "L2 779/C160L (Raven L2 180)" }, +{HPPA_TYPE_BOARD, 0x508, "L2 779/C160L (Raven L2 160)" }, +{HPPA_TYPE_BOARD, 0x509, "L2 712/132 (L2 Upgrade)" }, +{HPPA_TYPE_BOARD, 0x50a, "L2 712/160 (L2 Upgrade)" }, +{HPPA_TYPE_BOARD, 0x50b, "L2 712/132 (L2 Upgrade)" }, +{HPPA_TYPE_BOARD, 0x50c, "L2 712/160 (L2 Upgrade)" }, +{HPPA_TYPE_BOARD, 0x50d, "L2 (Rocky2 L2 120)" }, +{HPPA_TYPE_BOARD, 0x50e, "L2 (Rocky2 L2 150)" }, +{HPPA_TYPE_BOARD, 0x50f, "L2 744/132L (Anole-132L)" }, +{HPPA_TYPE_BOARD, 0x510, "L2 744/165L (Anole-165L)" }, +{HPPA_TYPE_BOARD, 0x511, "L2 (Kiji L2 132)" }, +{HPPA_TYPE_BOARD, 0x512, "L2 803/D220/D320 (UltraLight L2 132)" }, +{HPPA_TYPE_BOARD, 0x513, "L2 813/D220/D320 (UltraLight L2 160)" }, +{HPPA_TYPE_BOARD, 0x514, "L2 (Merlin Jr. L2 132)" }, +{HPPA_TYPE_BOARD, 0x515, "L2 (Staccato L2 132)" }, +{HPPA_TYPE_BOARD, 0x516, "L2 800/A180 (Staccato L2 180)" }, +{HPPA_TYPE_BOARD, 0x580, "T' 809/K100 (KittyHawk DC2-100)" }, +{HPPA_TYPE_BOARD, 0x581, "T' 839/K210 (KittyHawk DC3-120)" }, +{HPPA_TYPE_BOARD, 0x582, "T' 829/K400 (KittyHawk DC3-100)" }, +{HPPA_TYPE_BOARD, 0x583, "T' 849/K410 (KittyHawk DC3-120)" }, +{HPPA_TYPE_BOARD, 0x584, "T' T120 (LighteningHawk)" }, +{HPPA_TYPE_BOARD, 0x585, "T' 770/J200 (SkyHawk 100)" }, +{HPPA_TYPE_BOARD, 0x586, "T' 770/J210 (SkyHawk 120)" }, +{HPPA_TYPE_BOARD, 0x587, "T' 841/D210/D410 (UltraLight Proc 1-way T'120)" }, +{HPPA_TYPE_BOARD, 0x588, "T' 851/D210-2/D410-2 (UltraLight Proc 2-way T'120)" }, +{HPPA_TYPE_BOARD, 0x589, "T' 821/D200/D400 (UltraLight Proc 1-way T'100)" }, +{HPPA_TYPE_BOARD, 0x58a, "T' 831/D200-2/D400-2 (UltraLight Proc 2-way T'100)" }, +{HPPA_TYPE_BOARD, 0x58b, "T' 819/K200 (KittyHawk DC2 100)" }, +{HPPA_TYPE_BOARD, 0x58c, "T' 859/K220 (ThunderHawk DC3- 120 1M)" }, +{HPPA_TYPE_BOARD, 0x58d, "T' 869/K420 (ThunderHawk DC3 120 1M)" }, +{HPPA_TYPE_BOARD, 0x58e, "T' (Raven 120 T')" }, +{HPPA_TYPE_BOARD, 0x58f, "U 889/K450 (Mohawk 160 U 1M DC3)" }, +{HPPA_TYPE_BOARD, 0x590, "U 889/K460 (Mohawk 180 U 1M DC3)" }, +{HPPA_TYPE_BOARD, 0x591, "U (Mohawk 200 U 1M DC3)" }, +{HPPA_TYPE_BOARD, 0x592, "T' (Raven 100 T')" }, +{HPPA_TYPE_BOARD, 0x593, "U (FireHawk 160 U)" }, +{HPPA_TYPE_BOARD, 0x594, "U 780/J282 (FireHawk 180 U)" }, +{HPPA_TYPE_BOARD, 0x595, "U (FireHawk 220 U)" }, +{HPPA_TYPE_BOARD, 0x596, "U (FireHawk 240 U)" }, +{HPPA_TYPE_BOARD, 0x597, "U 800/V2200/V2500 (SPP2000)" }, +{HPPA_TYPE_BOARD, 0x598, "U 780/C230 (Raven U 230)" }, +{HPPA_TYPE_BOARD, 0x599, "U+ 780/C240 (Raven U 240)" }, +{HPPA_TYPE_BOARD, 0x59b, "U 780/C160 (Raven U 160)" }, +{HPPA_TYPE_BOARD, 0x59c, "U 780/C180 (Raven U 180)" }, +{HPPA_TYPE_BOARD, 0x59d, "U+ 780/C200 (Raven U 200)" }, +{HPPA_TYPE_BOARD, 0x59e, "T' (ThunderHawk T' 120)" }, +{HPPA_TYPE_BOARD, 0x59f, "U 780/C180+ (Raven U 180+)" }, +{HPPA_TYPE_BOARD, 0x5a0, "T' 841/D260/D360 (UltraLight 1-way T120 1MB)" }, +{HPPA_TYPE_BOARD, 0x5a1, "T' 851/D260/D360 (UltraLight 2-way T120 1MB)" }, +{HPPA_TYPE_BOARD, 0x5a2, "U 861/D270/D370 (UltraLight 1-way U160 512K)" }, +{HPPA_TYPE_BOARD, 0x5a3, "U 871/D270/D370 (UltraLight 2-way U160 512K)" }, +{HPPA_TYPE_BOARD, 0x5a4, "U 802/K250 (MoHawk U160 1M DC3-)" }, +{HPPA_TYPE_BOARD, 0x5a5, "U 879/K260 (MoHawk U180 1M DC3-)" }, +{HPPA_TYPE_BOARD, 0x5a6, "U (MoHawk U200 1M DC3-)" }, +{HPPA_TYPE_BOARD, 0x5a7, "U (UltraLight 1-way U160 1M)" }, +{HPPA_TYPE_BOARD, 0x5a8, "U (UltraLight 2-way U160 1M)" }, +{HPPA_TYPE_BOARD, 0x5a9, "U 810/D380/R380 (UltraLight 1-way U180 1M)" }, +{HPPA_TYPE_BOARD, 0x5aa, "U 820/D280 (UltraLight 2-way U180 1M)" }, +{HPPA_TYPE_BOARD, 0x5ad, "U+ (BraveHawk 180 DC3-)" }, +{HPPA_TYPE_BOARD, 0x5ae, "U+ 898/K370 (BraveHawk 200 DC3-)" }, +{HPPA_TYPE_BOARD, 0x5af, "U+ (BraveHawk 220 DC3-)" }, +{HPPA_TYPE_BOARD, 0x5b0, "U+ (BraveHawk 180 DC3)" }, +{HPPA_TYPE_BOARD, 0x5b1, "U+ 899/K570 (BraveHawk 200 DC3)" }, +{HPPA_TYPE_BOARD, 0x5b2, "U+ (BraveHawk 220 DC3)" }, +{HPPA_TYPE_BOARD, 0x5b3, "U (FireHawk 200)" }, +{HPPA_TYPE_BOARD, 0x5b4, "W 800/V2500 (SPP2500)" }, +{HPPA_TYPE_BOARD, 0x5b5, "U+ 782/J2240 (SummitHawk U+)" }, +{HPPA_TYPE_BOARD, 0x5b6, "U+ 800/K380 (DragonHawk U+ 240 DC3)" }, +{HPPA_TYPE_BOARD, 0x5b7, "U+ (DragonHawk U+ 240 DC3-)" }, +{HPPA_TYPE_BOARD, 0x5b8, "U+ SPP2250 240MHz processor" }, +{HPPA_TYPE_BOARD, 0x5b9, "U+ 821/D350/R350 (UltraLight 1w U+/240)" }, +{HPPA_TYPE_BOARD, 0x5ba, "U+ 800/D390/R390 (UltraLight 2w U+/240)" }, +{HPPA_TYPE_BOARD, 0x5bb, "W 785/C3000 (AllegroHigh W)" }, +{HPPA_TYPE_BOARD, 0x5bc, "W 785/B1000 (AllegroLow W)" }, +{HPPA_TYPE_BOARD, 0x5bd, "W 785/J5000 (Forte W 2w)" }, +{HPPA_TYPE_BOARD, 0x5be, "W 800/N4000-36 (Prelude W)" }, +{HPPA_TYPE_BOARD, 0x5bf, "W (Forte W 4w)" }, +{HPPA_TYPE_BOARD, 0x5c0, "W (M2250)" }, +{HPPA_TYPE_BOARD, 0x5c1, "W (M2500)" }, +{HPPA_TYPE_BOARD, 0x5c2, "W (Sonata 440)" }, +{HPPA_TYPE_BOARD, 0x5c3, "W (Sonata 360)" }, +{HPPA_TYPE_BOARD, 0x5c4, "W 800/L2000-44 (Rhapsody 440)" }, +{HPPA_TYPE_BOARD, 0x5c5, "W (Rhapsody 360)" }, +{HPPA_TYPE_BOARD, 0x5c6, "W 780/C360 (Raven W 360)" }, +{HPPA_TYPE_BOARD, 0x5c7, "W+ (Halftone W 440)" }, +{HPPA_TYPE_BOARD, 0x5c8, "W (Lego 360)" }, +{HPPA_TYPE_BOARD, 0x5c9, "W 800/L1000-44 (Rhapsody DC-440)" }, +{HPPA_TYPE_BOARD, 0x5ca, "W (Rhapsody DC- 360)" }, +{HPPA_TYPE_BOARD, 0x5cb, "W (Crescendo 440)" }, +{HPPA_TYPE_BOARD, 0x5cc, "W (Prelude W 440)" }, +{HPPA_TYPE_BOARD, 0x5cd, "W SPP2600" }, +{HPPA_TYPE_BOARD, 0x5ce, "W+ M2600" }, +{HPPA_TYPE_BOARD, 0x5cf, "W+ 785 (Allegro)" }, +{HPPA_TYPE_BOARD, 0x5d0, "W+ (Kazoo W+)" }, +{HPPA_TYPE_BOARD, 0x5d1, "W+ (Forte W+ 2w)" }, +{HPPA_TYPE_BOARD, 0x5d2, "W+ (Forte W+ 4w)" }, +{HPPA_TYPE_BOARD, 0x5d3, "W+ (Prelude W+ 550)" }, +{HPPA_TYPE_BOARD, 0x5d4, "W+ (Duet W+)" }, +{HPPA_TYPE_BOARD, 0x5d5, "W+ (Crescendo 550)" }, +{HPPA_TYPE_BOARD, 0x5d6, "W (Crescendo DC-440)" }, +{HPPA_TYPE_BOARD, 0x5d7, "W+ (Keystone W+)" }, +{HPPA_TYPE_BOARD, 0x5d8, "W+ (Rhapsody wave 2 W+ DC-)" }, +{HPPA_TYPE_BOARD, 0x5d9, "W+ (Rhapsody wave 2 W+)" }, +{HPPA_TYPE_BOARD, 0x5da, "W+ (Marcato W+ DC-)" }, +{HPPA_TYPE_BOARD, 0x5db, "W+ (Marcato W+)" }, +{HPPA_TYPE_BOARD, 0x5de, "W+ (Piccolo W+)" }, +{HPPA_TYPE_BOARD, 0x5ff, "W+ (Hitachi W)" }, +{HPPA_TYPE_BOARD, 0x600, "L 712/60 (Gecko)" }, +{HPPA_TYPE_BOARD, 0x601, "L 712/80 (King Gecko)" }, +{HPPA_TYPE_BOARD, 0x602, "L 712/100 (King Gecko)" }, +{HPPA_TYPE_BOARD, 0x603, "L 743i/64 (Anole-64)" }, +{HPPA_TYPE_BOARD, 0x604, "L 743i/100 (Anole-100)" }, +{HPPA_TYPE_BOARD, 0x605, "L 712/120 (King Gecko)" }, +{HPPA_TYPE_BOARD, 0x606, "L (Gila 80)" }, +{HPPA_TYPE_BOARD, 0x607, "L (Gila 100)" }, +{HPPA_TYPE_BOARD, 0x608, "L (Gila 120)" }, +{HPPA_TYPE_BOARD, 0x609, "L 715/80 (Scorpio-L)" }, +{HPPA_TYPE_BOARD, 0x60A, "L 715/64 (Mirage Jr.)" }, +{HPPA_TYPE_BOARD, 0x60B, "L 715/100 (Mirage Sr.)" }, +{HPPA_TYPE_BOARD, 0x60C, "L 715/100XC (Mirage Sr.)" }, +{HPPA_TYPE_BOARD, 0x60D, "L 725/100 (Electra)" }, +{HPPA_TYPE_BOARD, 0x60E, "L 725/120 (Electra)" }, +{HPPA_TYPE_BOARD, 0x610, "L 715/100L (Scorpio-L)" }, +{HPPA_TYPE_BOARD, 0x611, "L 715/120L (Scorpio-L)" }, +{HPPA_TYPE_BOARD, 0x612, "L 725/80L (Spectra-L)" }, +{HPPA_TYPE_BOARD, 0x613, "L 725/100L (Spectra-L)" }, +{HPPA_TYPE_BOARD, 0x614, "L 725/120L (Spectra-L)" }, +{HPPA_TYPE_BOARD, 0x615, "L Piranha 100" }, +{HPPA_TYPE_BOARD, 0x616, "L Piranha 120" }, +{HPPA_TYPE_BOARD, 0x617, "L 743/50 (Jason)" }, +{HPPA_TYPE_BOARD, 0x618, "L 743/100 (Jason)" }, +{HPPA_TYPE_BOARD, 0x619, "L 715/80 (Mirage)" }, +{HPPA_TYPE_BOARD, 0x61a, "L 811/DX5 (SAIC L-80)" }, +{HPPA_TYPE_BOARD, 0x61b, "L 801/DX0 (Rocky1 L-80)" }, +{HPPA_TYPE_BOARD, 0x61c, "L 743T (Anole T)" }, +{HPPA_TYPE_BOARD, 0x67e, "L (Hitachi Tiny 80)" }, +{HPPA_TYPE_BOARD, 0x67f, "L (Hitachi Tiny 64)" }, {HPPA_TYPE_BUS, HPPA_BUS_MID_BUS, "MID_BUS" }, {HPPA_TYPE_BUS, HPPA_BUS_SMB, "SMB" }, {HPPA_TYPE_BUS, HPPA_BUS_HPPB, "HP-PB" }, @@ -169,11 +228,11 @@ {HPPA_TYPE_BUS, HPPA_BUS_ROPES, "Ropes" }, {HPPA_TYPE_BUS, HPPA_BUS_MERCED, "Merced" }, {HPPA_TYPE_CPU, HPPA_CPU_SOFTEMU, "Software Emulation" }, -{HPPA_TYPE_CPU, HPPA_CPU_PCXT, "Tornado" }, +{HPPA_TYPE_CPU, HPPA_CPU_TORNADO, "Tornado" }, {HPPA_TYPE_CPU, HPPA_CPU_PCXL, "PA7100LC" }, -{HPPA_TYPE_CPU, HPPA_CPU_PCXUP, "PA8000" }, +{HPPA_TYPE_CPU, HPPA_CPU_PCXU, "PA8000" }, {HPPA_TYPE_CPU, HPPA_CPU_PCXL2, "PA7300LC" }, -{HPPA_TYPE_CPU, HPPA_CPU_PCXUP1, "PA8200" }, +{HPPA_TYPE_CPU, HPPA_CPU_PCXUP, "PA8200" }, {HPPA_TYPE_CPU, HPPA_CPU_PCXW, "PA8500" }, {HPPA_TYPE_FPU, HPPA_FPU_SOFTEMU, "Software Emulation" }, {HPPA_TYPE_FPU, HPPA_FPU_INDIGO, "Indigo" }, diff --git a/sys/arch/hp700/dev/devlist2h.awk b/sys/arch/hp700/dev/devlist2h.awk index 269d203e2835..129c73125995 100644 --- a/sys/arch/hp700/dev/devlist2h.awk +++ b/sys/arch/hp700/dev/devlist2h.awk @@ -1,4 +1,4 @@ -# $NetBSD: devlist2h.awk,v 1.1 2002/06/06 19:48:03 fredette Exp $ +# $NetBSD: devlist2h.awk,v 1.2 2002/08/05 20:58:36 fredette Exp $ # $OpenBSD: devlist2h.awk,v 1.4 2001/03/29 00:43:00 mickey Exp $ @@ -58,15 +58,22 @@ busted { } } -# first line is rcsid, beware NR == 1 { + printf("/*\t$NetBSD: devlist2h.awk,v 1.2 2002/08/05 20:58:36 fredette Exp $\t*/\n\n") > cpud; + printf("/* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. */\n\n") \ + > cpud; + printf("/*\t$NetBSD: devlist2h.awk,v 1.2 2002/08/05 20:58:36 fredette Exp $\t*/\n\n") > cpuh; + printf("/* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. */\n\n") \ + > cpuh; +} + +/^\$/ { VERSION = $0; gsub("\\$", "", VERSION); - printf("/*\n * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.\n" \ - " * generated from:\n *\t%s\n */\n\n", VERSION) > cpud; - printf("/*\n * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.\n" \ - " * generated from:\n *\t%s\n */\n\n", VERSION) > cpuh; + printf("/* generated from: %s */\n\n", VERSION) > cpud; + printf("/* generated from: %s */\n\n", VERSION) > cpuh; + next; } $1 == "type" { @@ -77,10 +84,15 @@ $1 == "type" { NR > 1 { if (tolower($1) in types) { - printf("#define\tHPPA_%s_%s\t%s\n", toupper($1), - toupper($2), $3) > cpuh; - printf("{HPPA_TYPE_%s,\tHPPA_%s_%s,\t\"", toupper($1), - toupper($1), toupper($2), $3) > cpud; + printf("{HPPA_TYPE_%s,\t", toupper($1)) > cpud; + if ($2 != "x") { + printf("#define\tHPPA_%s_%s\t%s\n", toupper($1), + toupper($2), $3) > cpuh; + printf("HPPA_%s_%s", toupper($1), toupper($2)) > cpud; + } else { + printf("%s", $3) > cpud; + } + printf(",\t\"") > cpud; f = 4; while (f <= NF) { sub(/[ \t]*/, "", $f); diff --git a/sys/arch/hp700/hp700/locore.S b/sys/arch/hp700/hp700/locore.S index bb7c2909dd7d..cdb2ad2419d9 100644 --- a/sys/arch/hp700/hp700/locore.S +++ b/sys/arch/hp700/hp700/locore.S @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.1 2002/06/06 19:48:06 fredette Exp $ */ +/* $NetBSD: locore.S,v 1.2 2002/08/05 20:58:36 fredette Exp $ */ /* $OpenBSD: locore.S,v 1.46 2001/09/20 18:33:03 mickey Exp $ */ @@ -154,7 +154,7 @@ kernelmapped /* set when kernel is mapped */ /* * This is the starting location for the kernel */ -ENTRY($start,0) +ENTRY(start,0) /* * start(pdc, boothowto, bootdev, esym, bootapiver, argv, argc) * @@ -354,7 +354,7 @@ $callmain /* should never return... */ bv (rp) nop -EXIT($start) +EXIT(start) /* int * pdc_call(func, pdc_flag, ...) diff --git a/sys/arch/hp700/hp700/machdep.c b/sys/arch/hp700/hp700/machdep.c index 9e6530e23986..0157602e2d39 100644 --- a/sys/arch/hp700/hp700/machdep.c +++ b/sys/arch/hp700/hp700/machdep.c @@ -1,4 +1,4 @@ -/* $NetBSD: machdep.c,v 1.1 2002/06/06 19:48:06 fredette Exp $ */ +/* $NetBSD: machdep.c,v 1.2 2002/08/05 20:58:36 fredette Exp $ */ /*- * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. @@ -179,8 +179,7 @@ u_int cpu_ticksnum, cpu_ticksdenom, cpu_hzticks; /* exported info */ char machine[] = MACHINE; char cpu_model[128]; -enum hppa_cpu_type cpu_type; -const char *cpu_typename; +const struct hppa_cpu_info *hppa_cpu_info; #ifdef COMPAT_HPUX int cpu_model_hpux; /* contains HPUX_SYSCONF_CPU* kind of value */ #endif @@ -196,7 +195,19 @@ int (*cpu_dbtlb_ins) __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa, vsize_t sz, u_int prot)); dev_t bootdev; -int totalphysmem, resvmem, physmem, esym; +int totalphysmem, physmem, esym; +/* + * XXX note that 0x12000 is the old kernel text start + * address. Memory below this are assumed to belong + * to the firmware. This value is converted into pages + * by hppa_init and used as pages in pmap_bootstrap(). + */ +int resvmem = 0x12000; + +/* + * BTLB parameters, broken out for the MI hppa code. + */ +u_int hppa_btlb_size_min, hppa_btlb_size_max; /* * Things for MI glue to stick on. @@ -209,12 +220,9 @@ struct extent *hppa_ex; vaddr_t vmmap; /* - * XXX fredette - a bus_dma hack, brought on by our use of a - * BTLB entry to map the kernel, I think. + * Certain devices need DMA'able memory below the 16MB boundary. */ -#define DMA24_SIZE_MAX (128 * 1024) -#define DMA24_SIZE_MIN (32 * 1024) -#define DMA24_SIZE_STEP (4 * 1024) +#define DMA24_SIZE (128 * 1024) struct extent *dma24_ex; long dma24_ex_storage[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; @@ -238,6 +246,7 @@ struct pdc_coproc pdc_coproc PDC_ALIGNMENT; struct pdc_coherence pdc_coherence PDC_ALIGNMENT; struct pdc_spidb pdc_spidbits PDC_ALIGNMENT; struct pdc_pim pdc_pim PDC_ALIGNMENT; +struct pdc_model pdc_model PDC_ALIGNMENT; /* * Whatever CPU types we support @@ -264,83 +273,146 @@ int desidhash_s __P((void)); int desidhash_t __P((void)); int desidhash_l __P((void)); int desidhash_g __P((void)); -const struct hppa_cpu_typed { - char name[8]; - enum hppa_cpu_type type; - int arch; - int features; - int (*desidhash) __P((void)); - const u_int *itlbh, *dtlbh, *dtlbnah, *tlbdh; - int (*dbtlbins) __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa, - vsize_t sz, u_int prot)); - int (*ibtlbins) __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa, - vsize_t sz, u_int prot)); - int (*btlbprg) __P((int i)); - int (*hptinit) __P((vaddr_t hpt, vsize_t hptsize)); -} cpu_types[] = { +#define _HPPA_CPU_UNSUPP \ + NULL, \ + NULL, 0, \ + NULL, NULL, NULL, NULL, NULL, \ + NULL, NULL, NULL +const struct hppa_cpu_info hppa_cpu_pa7000_pcx = { + "PA7000", #ifdef HP7000_CPU - { "PCX", hpcx, 0x10, 0, + NULL, + "PCX", HPPA_PA_SPEC_MAKE(1, 0, '\0'), desidhash_x, itlb_x, dtlb_x, dtlbna_x, tlbd_x, - ibtlb_g, NULL, pbtlb_g}, - { "PCXS", hpcxs, 0x11, HPPA_FTRS_BTLBS, + ibtlb_g, NULL, pbtlb_g +#else /* !HP7000_CPU */ + _HPPA_CPU_UNSUPP +#endif /* !HP7000_CPU */ +}; +const struct hppa_cpu_info hppa_cpu_pa7000_pcxs = { + "PA7000", +#ifdef HP7000_CPU + NULL, + "PCX-S", HPPA_PA_SPEC_MAKE(1, 1, 'a'), desidhash_s, itlb_s, dtlb_s, dtlbna_s, tlbd_s, - ibtlb_g, NULL, pbtlb_g}, -#endif + ibtlb_g, NULL, pbtlb_g +#else /* !HP7000_CPU */ + _HPPA_CPU_UNSUPP +#endif /* !HP7000_CPU */ +}; +const struct hppa_cpu_info hppa_cpu_pa7100 = { + "PA7100", #ifdef HP7100_CPU - { "PCXT", hpcxt, 0x11, HPPA_FTRS_BTLBU, + "T-Bird", + "PCX-T", HPPA_PA_SPEC_MAKE(1, 1, 'b'), desidhash_t, itlb_t, dtlb_t, dtlbna_t, tlbd_t, - ibtlb_g, NULL, pbtlb_g}, -#endif + ibtlb_g, NULL, pbtlb_g, + hpti_g +#else /* !HP7100_CPU */ + _HPPA_CPU_UNSUPP +#endif /* !HP7100_CPU */ +}; +const struct hppa_cpu_info hppa_cpu_pa7150 = { + "PA7150", +#ifdef HP7100_CPU + "T-Bird", + "PCX-T", HPPA_PA_SPEC_MAKE(1, 1, 'b'), + desidhash_t, itlb_t, dtlb_t, dtlbna_t, tlbd_t, + ibtlb_g, NULL, pbtlb_g, + hpti_g +#else /* !HP7100_CPU */ + _HPPA_CPU_UNSUPP +#endif /* !HP7100_CPU */ +}; +const struct hppa_cpu_info hppa_cpu_pa7200 = { + "PA7200", #ifdef HP7200_CPU -/* HOW? { "PCXT'", hpcxta,0x11, HPPA_FTRS_BTLBU, + "T-Bird", + "PCX-T'", HPPA_PA_SPEC_MAKE(1, 1, 'd'), desidhash_t, itlb_t, dtlb_t, dtlbna_t, tlbd_t, - ibtlb_g, NULL, pbtlb_g}, */ -#endif + ibtlb_g, NULL, pbtlb_g +#else /* !HP7200_CPU */ + _HPPA_CPU_UNSUPP +#endif /* !HP7200_CPU */ +}; +const struct hppa_cpu_info hppa_cpu_pa7100lc = { + "PA7100LC", #ifdef HP7100LC_CPU - { "PCXL", hpcxl, 0x11, HPPA_FTRS_BTLBU|HPPA_FTRS_HVT, + "Hummingbird", + "PCX-L", HPPA_PA_SPEC_MAKE(1, 1, 'c'), desidhash_l, itlb_l, dtlb_l, dtlbna_l, tlbd_l, - ibtlb_g, NULL, pbtlb_g, hpti_g}, -#endif + ibtlb_g, NULL, pbtlb_g, hpti_g +#else /* !HP7100LC_CPU */ + _HPPA_CPU_UNSUPP +#endif /* !HP7100LC_CPU */ +}; +const struct hppa_cpu_info hppa_cpu_pa7300lc = { + "PA7300LC", #ifdef HP7300LC_CPU -/* HOW? { "PCXL2", hpcxl2,0x11, HPPA_FTRS_BTLBU|HPPA_FTRS_HVT, + "Velociraptor", + "PCX-L2", HPPA_PA_SPEC_MAKE(1, 1, 'e'), desidhash_l, itlb_l, dtlb_l, dtlbna_l, tlbd_l, - ibtlb_g, NULL, pbtlb_g, hpti_g}, */ -#endif + ibtlb_g, NULL, pbtlb_g, hpti_g +#else /* !HP7300LC_CPU */ + _HPPA_CPU_UNSUPP +#endif /* !HP7300LC_CPU */ +}; +const struct hppa_cpu_info hppa_cpu_pa8000 = { + "PA8000", #ifdef HP8000_CPU - { "PCXU", hpcxu, 0x20, HPPA_FTRS_W32B|HPPA_FTRS_BTLBU|HPPA_FTRS_HVT, + "Onyx", + "PCX-U", HPPA_PA_SPEC_MAKE(2, 0, '\0'), desidhash_g, itlb_l, dtlb_l, dtlbna_l, tlbd_l, - ibtlb_g, NULL, pbtlb_g, hpti_g}, -#endif + ibtlb_g, NULL, pbtlb_g, hpti_g +#else /* !HP8000_CPU */ + _HPPA_CPU_UNSUPP +#endif /* !HP8000_CPU */ +}; +const struct hppa_cpu_info hppa_cpu_pa8200 = { + "PA8200", #ifdef HP8200_CPU -/* HOW? { "PCXU2", hpcxu2,0x20, HPPA_FTRS_W32B|HPPA_FTRS_BTLBU|HPPA_FTRS_HVT, + NULL, + "PCX-W", HPPA_PA_SPEC_MAKE(2, 0, '\0'), desidhash_g, itlb_l, dtlb_l, dtlbna_l, tlbd_l, - ibtlb_g, NULL, pbtlb_g, hpti_g}, */ -#endif + ibtlb_g, NULL, pbtlb_g, hpti_g +#else /* !HP8200_CPU */ + _HPPA_CPU_UNSUPP +#endif /* !HP8200_CPU */ +}; +const struct hppa_cpu_info hppa_cpu_pa8500 = { + "PA8500", #ifdef HP8500_CPU -/* HOW? { "PCXW", hpcxw, 0x20, HPPA_FTRS_W32B|HPPA_FTRS_BTLBU|HPPA_FTRS_HVT, + "Barra'Cuda", + "PCX-W", HPPA_PA_SPEC_MAKE(2, 0, '\0'), desidhash_g, itlb_l, dtlb_l, dtlbna_l, tlbd_l, - ibtlb_g, NULL, pbtlb_g, hpti_g}, */ -#endif + ibtlb_g, NULL, pbtlb_g, hpti_g +#else /* !HP8500_CPU */ + _HPPA_CPU_UNSUPP +#endif /* !HP8500_CPU */ +}; +const struct hppa_cpu_info hppa_cpu_pa8600 = { + "PA8600", #ifdef HP8600_CPU -/* HOW? { "PCXW+", hpcxw, 0x20, HPPA_FTRS_W32B|HPPA_FTRS_BTLBU|HPPA_FTRS_HVT, + NULL, + "PCX-W+", HPPA_PA_SPEC_MAKE(2, 0, '\0'), desidhash_g, itlb_l, dtlb_l, dtlbna_l, tlbd_l, - ibtlb_g, NULL, pbtlb_g, hpti_g}, */ -#endif - { "", 0 } + ibtlb_g, NULL, pbtlb_g, hpti_g +#else /* !HP8600_CPU */ + _HPPA_CPU_UNSUPP +#endif /* !HP8600_CPU */ }; void hppa_init(start) paddr_t start; { - extern int kernel_text; - vaddr_t v, vstart, vend; + vaddr_t vstart, vend; register int error; int hptsize; /* size of HPT table if supported */ - int cpu_features = 0; - int dma24size; int sz; u_int *p, *q; + struct pdc_cpuid pdc_cpuid PDC_ALIGNMENT; + const char *model; #ifdef KGDB boothowto |= RB_KDB; /* go to kgdb early if compiled in. */ @@ -411,15 +483,15 @@ hppa_init(start) PDC_BTLB_PURGE_ALL) < 0) printf("WARNING: BTLB purge failed\n"); - cpu_features = pdc_btlb.finfo.num_c? - HPPA_FTRS_BTLBU : HPPA_FTRS_BTLBS; + hppa_btlb_size_min = pdc_btlb.min_size; + hppa_btlb_size_max = pdc_btlb.max_size; } ptlball(); fcacheall(); totalphysmem = PAGE0->imm_max_mem / NBPG; - resvmem = ((vaddr_t)&kernel_text) / NBPG; + resvmem = resvmem / NBPG; /* calculate HPT size */ /* for (hptsize = 256; hptsize < totalphysmem; hptsize *= 2); */ @@ -432,8 +504,6 @@ hptsize=256; /* XXX one page for now */ mtctl(hptsize - 1, CR_HPTMASK); hptsize = 0; } else { - cpu_features |= HPPA_FTRS_HVT; - if (hptsize > pdc_hwtlb.max_size) hptsize = pdc_hwtlb.max_size; else if (hptsize < pdc_hwtlb.min_size) @@ -448,45 +518,160 @@ hptsize=256; /* XXX one page for now */ */ /* - * Deal w/ CPU now + * Figure out what kind of CPU we are dealing with. Generally, + * we do this by consulting the hp700/dev/cpudevs model string + * for this model's board number. These model strings begin + * with an encoding of the expected CPU type. + * + * Being somewhat paranoid, when we get reliable information + * from a PDC_MODEL(6)/PDC_MODEL_CPUID(6) call, we let it + * override the expected CPU type. + * */ - { - const struct hppa_cpu_typed *p; + if ((error = pdc_call((iodcio_t)pdc, 0, PDC_MODEL, PDC_MODEL_INFO, + &pdc_model)) < 0) { +#ifdef DEBUG + printf("WARNING: PDC_MODEL error %d\n", error); +#endif + pdc_model.hvers = 0; + } + model = hppa_mod_info(HPPA_TYPE_BOARD, pdc_model.hvers >> 4); + hppa_cpu_info = NULL; + switch (*(model++)) { - for (p = cpu_types; - p->arch && p->features != cpu_features; p++); + case 'X': + hppa_cpu_info = &hppa_cpu_pa7000_pcx; + break; - if (!p->arch) - printf("WARNING: UNKNOWN CPU TYPE; GOOD LUCK (%x)\n", - cpu_features); - else { - /* - * Ptrs to various tlb handlers, to be filled - * based on cpu features. - * from locore.S - */ - extern u_int trap_ep_T_TLB_DIRTY[]; - extern u_int trap_ep_T_DTLBMISS[]; - extern u_int trap_ep_T_DTLBMISSNA[]; - extern u_int trap_ep_T_ITLBMISS[]; - extern u_int trap_ep_T_ITLBMISSNA[]; + case 'S': + hppa_cpu_info = &hppa_cpu_pa7000_pcxs; + break; - cpu_type = p->type; - cpu_typename = p->name; - cpu_ibtlb_ins = p->ibtlbins; - cpu_dbtlb_ins = p->dbtlbins; - cpu_hpt_init = p->hptinit; - cpu_desidhash = p->desidhash; + case '0': + case '5': + if (*model == 'T') { + hppa_cpu_info = (*(model - 1) == '0' ? + &hppa_cpu_pa7100 : &hppa_cpu_pa7150); + model++; + } + break; -#define LDILDO(t,f) ((t)[0] = (f)[0], (t)[1] = (f)[1]) - LDILDO(trap_ep_T_TLB_DIRTY , p->tlbdh); - LDILDO(trap_ep_T_DTLBMISS , p->dtlbh); - LDILDO(trap_ep_T_DTLBMISSNA, p->dtlbnah); - LDILDO(trap_ep_T_ITLBMISS , p->itlbh); - LDILDO(trap_ep_T_ITLBMISSNA, p->itlbh); -#undef LDILDO + case 'L': + if (*model == '2') { + hppa_cpu_info = &hppa_cpu_pa7300lc; + model++; + } else if (*model == ' ') + hppa_cpu_info = &hppa_cpu_pa7100lc; + break; + + case 'T': + if (*model == '\'') { + hppa_cpu_info = &hppa_cpu_pa7200; + model++; + } + break; + + case 'U': + if (*model == '+') { + hppa_cpu_info = &hppa_cpu_pa8200; + model++; + } else if (*model == ' ') + hppa_cpu_info = &hppa_cpu_pa8000; + break; + + case 'W': + if (*model == '+') { + hppa_cpu_info = &hppa_cpu_pa8600; + model++; + } else if (*model == ' ') + hppa_cpu_info = &hppa_cpu_pa8500; + break; + } + if (*model == ' ') + model++; + else + hppa_cpu_info = NULL; + memset (&pdc_cpuid, 0, sizeof(pdc_cpuid)); + if (pdc_call((iodcio_t)pdc, 0, PDC_MODEL, PDC_MODEL_CPUID, + &pdc_cpuid, 0, 0, 0, 0) >= 0) { + + /* patch for old 8200 */ + if (pdc_cpuid.version == HPPA_CPU_PCXU && + pdc_cpuid.revision > 0x0d) + pdc_cpuid.version = HPPA_CPU_PCXUP; + switch (pdc_cpuid.version) { + case HPPA_CPU_PCXL: + hppa_cpu_info = &hppa_cpu_pa7100lc; + break; + case HPPA_CPU_PCXU: + hppa_cpu_info = &hppa_cpu_pa8000; + break; + case HPPA_CPU_PCXL2: + hppa_cpu_info = &hppa_cpu_pa7300lc; + break; + case HPPA_CPU_PCXUP: + hppa_cpu_info = &hppa_cpu_pa8200; + break; + case HPPA_CPU_PCXW: + hppa_cpu_info = &hppa_cpu_pa8500; + break; } } + if (hppa_cpu_info == NULL) + panic("bad model string for 0x%x", pdc_model.hvers >> 4); + if (hppa_cpu_info->desidhash == NULL) + panic("no kernel support for %s", + hppa_cpu_info->hppa_cpu_info_chip_name); + + /* + * The remainder of the hp700/dev/cpudevs model string is + * the real name of the model. Some models only have + * nicknames, and not true model numbers. + */ + if (*model != '(') + snprintf(cpu_model, sizeof(cpu_model), "HP9000/%s", model); + else { + strncpy(cpu_model, model, sizeof(cpu_model)); + cpu_model[strlen(cpu_model) - 1] = '\0'; + } +#ifdef DEBUG + printf("%s, %s\n", cpu_model, hppa_cpu_info->hppa_cpu_info_chip_name); +#endif + + /* + * Ptrs to various tlb handlers, to be filled + * based on cpu features. + * from locore.S + */ + extern u_int trap_ep_T_TLB_DIRTY[]; + extern u_int trap_ep_T_DTLBMISS[]; + extern u_int trap_ep_T_DTLBMISSNA[]; + extern u_int trap_ep_T_ITLBMISS[]; + extern u_int trap_ep_T_ITLBMISSNA[]; + + cpu_ibtlb_ins = hppa_cpu_info->ibtlbins; + cpu_dbtlb_ins = hppa_cpu_info->dbtlbins; + cpu_hpt_init = hppa_cpu_info->hptinit; + cpu_desidhash = hppa_cpu_info->desidhash; + +#define LDILDO(t,f) ((t)[0] = (f)[0], (t)[1] = (f)[1]) + LDILDO(trap_ep_T_TLB_DIRTY , hppa_cpu_info->tlbdh); + LDILDO(trap_ep_T_DTLBMISS , hppa_cpu_info->dtlbh); + LDILDO(trap_ep_T_DTLBMISSNA, hppa_cpu_info->dtlbnah); + LDILDO(trap_ep_T_ITLBMISS , hppa_cpu_info->itlbh); + LDILDO(trap_ep_T_ITLBMISSNA, hppa_cpu_info->itlbh); +#undef LDILDO + +#ifdef COMPAT_HPUX + if (hppa_cpu_info->hppa_cpu_info_pa_spec >= + HPPA_PA_SPEC_MAKE(2, 0, ' ')) + cpu_model_hpux = HPUX_SYSCONF_CPUPA20; + else if (hppa_cpu_info->hppa_cpu_info_pa_spec >= + HPPA_PA_SPEC_MAKE(1, 1, ' ')) + cpu_model_hpux = HPUX_SYSCONF_CPUPA11; + else + cpu_model_hpux = HPUX_SYSCONF_CPUPA10; +#endif /* we hope this won't fail */ hppa_ex = extent_create("mem", 0x0, 0xffffffff, M_DEVBUF, @@ -511,6 +696,18 @@ hptsize=256; /* XXX one page for now */ vstart += sz; vstart = hppa_round_page(vstart); + /* Allocate the msgbuf. */ + msgbufaddr = (caddr_t) vstart; + vstart += MSGBUFSIZE; + vstart = hppa_round_page(vstart); + + /* Allocate the 24-bit DMA region. */ + dma24_ex = extent_create("dma24", vstart, vstart + DMA24_SIZE, M_DEVBUF, + (caddr_t)dma24_ex_storage, sizeof(dma24_ex_storage), + EX_NOCOALESCE|EX_NOWAIT); + vstart += DMA24_SIZE; + vstart = hppa_round_page(vstart); + /* Calculate the OS_TOC handler checksum. */ p = (u_int *) &os_toc; q = (&os_toc_end - 1); @@ -521,36 +718,13 @@ hptsize=256; /* XXX one page for now */ PAGE0->ivec_toclen = ((caddr_t) &os_toc_end) - ((caddr_t) &os_toc); pmap_bootstrap(&vstart, &vend); - physmem = totalphysmem - btoc(vstart); /* * BELOW THIS LINE REFERENCING PAGE0 AND OTHER LOW MEMORY - * LOCATIONS, AND WRITING THE KERNEL TEXT IS PROHIBITED + * LOCATIONS, AND WRITING THE KERNEL TEXT ARE PROHIBITED * WITHOUT TAKING SPECIAL MEASURES. */ - /* alloc msgbuf */ - if (!(msgbufaddr = (void *)pmap_steal_memory(MSGBUFSIZE, NULL, NULL))) - panic("cannot allocate msgbuf"); - - /* allocate the 24-bit DMA region. */ - v = NULL; - dma24size = DMA24_SIZE_MAX; - while (dma24size >= DMA24_SIZE_MIN) { - v = pmap_steal_memory(dma24size, NULL, NULL); - if (v != NULL) - break; - dma24size -= DMA24_SIZE_STEP; - } - if (v == NULL) { - printf("WARNING: could not allocate 24-bit DMA memory\n"); - dma24_ex = NULL; - } else { - dma24_ex = extent_create("dma24", v, v + dma24size, M_DEVBUF, - (caddr_t)dma24_ex_storage, sizeof(dma24_ex_storage), - EX_NOCOALESCE|EX_NOWAIT); - } - /* Turn on the HW TLB assist */ if (hptsize) { u_int hpt; @@ -606,11 +780,10 @@ hptsize=256; /* XXX one page for now */ void cpu_startup() { - struct pdc_model pdc_model PDC_ALIGNMENT; vaddr_t minaddr, maxaddr; vsize_t size; int base, residual; - int err, i; + int i; char pbuf[3][9]; #ifdef PMAPDEBUG extern int pmapdebug; @@ -631,45 +804,9 @@ cpu_startup() printf(version); /* identify system type */ - if ((err = pdc_call((iodcio_t)pdc, 0, PDC_MODEL, PDC_MODEL_INFO, - &pdc_model)) < 0) { -#ifdef DEBUG - printf("WARNING: PDC_MODEL error %d\n", err); -#endif - } else { - const char *p, *q; - i = pdc_model.hvers >> 4; - p = hppa_mod_info(HPPA_TYPE_BOARD, i); - switch (pdc_model.arch_rev) { - default: - case 0: - q = "1.0"; -#ifdef COMPAT_HPUX - cpu_model_hpux = HPUX_SYSCONF_CPUPA10; -#endif - break; - case 4: - q = "1.1"; -#ifdef COMPAT_HPUX - cpu_model_hpux = HPUX_SYSCONF_CPUPA11; -#endif - break; - case 8: - q = "2.0"; -#ifdef COMPAT_HPUX - cpu_model_hpux = HPUX_SYSCONF_CPUPA20; -#endif - break; - } - - if (p) - sprintf(cpu_model, "HP9000/%s PA-RISC %s", p, q); - else - sprintf(cpu_model, "HP9000/(UNKNOWN %x) PA-RISC %s", - i, q); - printf("%s\n", cpu_model); - } + printf("%s\n", cpu_model); + /* Display some memory usage information. */ format_bytes(pbuf[0], sizeof(pbuf[0]), ptoa(totalphysmem)); format_bytes(pbuf[1], sizeof(pbuf[1]), ptoa(resvmem)); format_bytes(pbuf[2], sizeof(pbuf[2]), ptoa(physmem)); @@ -1357,6 +1494,7 @@ dumpsys() if (!(error = cpu_dump())) { + /* XXX fredette - this is way broken: */ bytes = ctob(physmem); maddr = NULL; blkno = dumplo + cpu_dumpsize(); diff --git a/sys/arch/hp700/include/cpu.h b/sys/arch/hp700/include/cpu.h index 3d5db8e481cd..3cc3f3510e10 100644 --- a/sys/arch/hp700/include/cpu.h +++ b/sys/arch/hp700/include/cpu.h @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.h,v 1.1 2002/06/06 19:48:07 fredette Exp $ */ +/* $NetBSD: cpu.h,v 1.2 2002/08/05 20:58:37 fredette Exp $ */ /* $OpenBSD: cpu.h,v 1.20 2001/01/29 00:01:58 mickey Exp $ */ @@ -70,12 +70,40 @@ #define HPPA_FTRS_W32B 0x00000008 #ifndef _LOCORE -/* types */ -enum hppa_cpu_type { - hpcx, hpcxs, hpcxt, hpcxta, hpcxl, hpcxl2, hpcxu, hpcxu2, hpcxw + +/* + * A CPU description. + */ +struct hppa_cpu_info { + + /* The official name of the chip. */ + const char *hppa_cpu_info_chip_name; + + /* The nickname for the chip. */ + const char *hppa_cpu_info_chip_nickname; + + /* The type and PA-RISC specification of the chip. */ + const char *hppa_cpu_info_chip_type; + unsigned short hppa_cpu_info_pa_spec; +#define HPPA_PA_SPEC_MAKE(major, minor, letter) \ + (((major) << 8) | \ + ((minor) << 4) | \ + ((letter) == '\0' ? 0 : ((letter) + 0xa - 'a'))) +#define HPPA_PA_SPEC_MAJOR(x) (((x) >> 8) & 0xf) +#define HPPA_PA_SPEC_MINOR(x) (((x) >> 4) & 0xf) +#define HPPA_PA_SPEC_LETTER(x) \ + (((x) & 0xf) == 0 ? '\0' : 'a' + ((x) & 0xf) - 0xa) + + int (*desidhash) __P((void)); + const u_int *itlbh, *dtlbh, *dtlbnah, *tlbdh; + int (*dbtlbins) __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa, + vsize_t sz, u_int prot)); + int (*ibtlbins) __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa, + vsize_t sz, u_int prot)); + int (*btlbprg) __P((int i)); + int (*hptinit) __P((vaddr_t hpt, vsize_t hptsize)); }; -extern enum hppa_cpu_type cpu_type; -extern const char *cpu_typename; +extern const struct hppa_cpu_info *hppa_cpu_info; #endif /* diff --git a/sys/arch/hppa/hppa/machdep.h b/sys/arch/hppa/hppa/machdep.h index bc70ab55d74c..b9b187baddc5 100644 --- a/sys/arch/hppa/hppa/machdep.h +++ b/sys/arch/hppa/hppa/machdep.h @@ -1,4 +1,4 @@ -/* $NetBSD: machdep.h,v 1.1 2002/06/05 01:04:20 fredette Exp $ */ +/* $NetBSD: machdep.h,v 1.2 2002/08/05 20:58:35 fredette Exp $ */ /* * Copyright (c) 2002 The NetBSD Foundation, Inc. @@ -64,8 +64,13 @@ extern vaddr_t vmmap; /* XXX - See mem.c */ /* Kernel virtual address space available: */ extern vaddr_t virtual_start, virtual_end; -/* Physical pages available. */ +/* Total physical pages, and low reserved physical pages. */ extern int totalphysmem; +extern int resvmem; + +/* BTLB minimum and maximum sizes, in pages. */ +extern u_int hppa_btlb_size_min; +extern u_int hppa_btlb_size_max; /* FPU variables and functions. */ extern int fpu_present; diff --git a/sys/arch/hppa/hppa/pmap.c b/sys/arch/hppa/hppa/pmap.c index 00e8e9305a0d..5c8f246cc2d6 100644 --- a/sys/arch/hppa/hppa/pmap.c +++ b/sys/arch/hppa/hppa/pmap.c @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.c,v 1.1 2002/06/05 01:04:20 fredette Exp $ */ +/* $NetBSD: pmap.c,v 1.2 2002/08/05 20:58:35 fredette Exp $ */ /*- * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. @@ -186,8 +186,6 @@ #include #include #include -#include -#include #include #include @@ -238,7 +236,7 @@ int pmapdebug = 0 #endif #define PMAP_PRINTF(v,x) PMAP_PRINTF_MASK(v,v,x) -vaddr_t virtual_steal, virtual_stolen, virtual_start, virtual_end; +vaddr_t virtual_steal, virtual_start, virtual_end; /* These two virtual pages are available for copying and zeroing. */ static vaddr_t tmp_vpages[2]; @@ -298,6 +296,9 @@ vsize_t hpt_mask; */ #define BADALIAS(sp1, va1, pr1, sp2, va2, pr2) (TRUE) +/* Prototypes. */ +static __inline void pmap_pv_remove __P((struct pv_entry *)); + /* * Given a directly-mapped region, this makes pv_entries out of it and * adds them to the free list. @@ -327,22 +328,69 @@ pmap_pv_add(vaddr_t pv_start, vaddr_t pv_end) /* * This allocates and returns a new struct pv_entry. * - * If we run out of preallocated struct pv_entries, we have to panic. - * malloc() isn't an option, because a) we'll probably end up back - * here anyways when malloc() maps what it's trying to return to us, - * and b) even if malloc() did succeed, the TLB fault handlers run in - * physical mode and thus require that all pv_entries be directly + * If we run out of preallocated struct pv_entries, we have to forcibly + * free one. malloc() isn't an option, because a) we'll probably end + * up back here anyways when malloc() maps what it's trying to return to + * us, and b) even if malloc() did succeed, the TLB fault handlers run + * in physical mode and thus require that all pv_entries be directly * mapped, a quality unlikely for malloc()-returned memory. */ static __inline struct pv_entry *pmap_pv_alloc __P((void)); static __inline struct pv_entry * pmap_pv_alloc(void) { - struct pv_entry *pv; + struct pv_entry *pv, *pv_fallback; + u_int hpt_index_first, hpt_index, hpt_size; + struct hpt_entry *hpt; pv = pv_free_list; - if (pv == NULL) - panic("out of pv_entries"); + if (pv == NULL) { + /* + * We need to find a struct pv_entry to forcibly + * free. It cannot be wired or unmanaged. We + * prefer to free mappings that aren't marked as + * referenced. We search the HPT for an entry + * to free, starting at a semirandom HPT index + * determined by the current value of the interval + * timer. + */ + hpt_size = hpt_mask / sizeof(*hpt); + mfctl(CR_ITMR, hpt_index_first); + hpt_index = hpt_index_first = hpt_index_first & hpt_size; + pv_fallback = NULL; + do { + hpt = ((struct hpt_entry *) hpt_base) + hpt_index; + for (pv = hpt->hpt_entry; + pv != NULL; + pv = pv->pv_hash) { + if (!(pv->pv_tlbprot & TLB_WIRED) && + !(pv->pv_flags & HPPA_PV_UNMANAGED)) { + if (!(pv->pv_tlbprot & TLB_REF)) + break; + pv_fallback = pv; + } + } + if (pv != NULL) + break; + if (pv_fallback != NULL) { + pv = pv_fallback; + break; + } + hpt_index = (hpt_index + 1) & hpt_size; + } while (hpt_index != hpt_index_first); + + /* Remove the mapping. */ + if (pv != NULL) { + KASSERT(pv->pv_pmap->pmap_stats.resident_count > 0); + pv->pv_pmap->pmap_stats.resident_count--; + pmap_pv_remove(pv); + pv = pv_free_list; + } + + if (pv == NULL) + panic("out of pv_entries"); + + } pv_free_list = pv->pv_next; pv->pv_next = NULL; @@ -450,15 +498,10 @@ static __inline int pmap_table_find_pa __P((paddr_t)); static __inline int pmap_table_find_pa(paddr_t pa) { - int bank, off; + int off; - if (pa < virtual_start) - off = atop(pa); - else if ((bank = vm_physseg_find(atop(pa), &off)) != -1) { - off += vm_physmem[bank].pmseg.pmap_table_off; - } else - return -1; - return off; + off = atop(pa); + return (off < totalphysmem) ? off : -1; } /* @@ -516,13 +559,6 @@ pmap_pv_enter(pmap_t pmap, pa_space_t space, vaddr_t va, } else unmanaged = 0; - KASSERT(!pmap_initialized || - (space == HPPA_SID_KERNEL ? - ((pa == 0 && va == 0) || - (va == tmp_vpages[0]) || - (va == tmp_vpages[1]) || - (pa >= virtual_start && va >= virtual_start)) : - (pa >= virtual_start))); #ifdef DIAGNOSTIC /* Make sure this VA isn't already entered. */ for (pv = hpt->hpt_entry; pv != NULL; pv = pv->pv_hash) @@ -599,7 +635,6 @@ pmap_pv_enter(pmap_t pmap, pa_space_t space, vaddr_t va, /* * Given a particular VA->PA mapping, this removes it. */ -static __inline void pmap_pv_remove __P((struct pv_entry *)); static __inline void pmap_pv_remove(struct pv_entry *pv) { @@ -701,9 +736,10 @@ pmap_bootstrap(vstart, vend) vsize_t btlb_entry_size[BTLB_SET_SIZE]; int btlb_entry_vm_prot[BTLB_SET_SIZE]; int btlb_i, btlb_j; - vsize_t btlb_entry_min, btlb_entry_got; + vsize_t btlb_entry_min, btlb_entry_max, btlb_entry_got; extern int kernel_text, etext; - PMAP_PRINTF(PDB_INIT, ("(%p, %p)\n", vstart, vend)); + vaddr_t kernel_data; + paddr_t phys_start, phys_end; uvm_setpagesize(); @@ -750,7 +786,6 @@ pmap_bootstrap(vstart, vend) */ addr = hppa_round_page(*vstart); virtual_end = *vend; - pv_region = addr; /* * Figure out how big the HPT must be, and align @@ -758,6 +793,7 @@ pmap_bootstrap(vstart, vend) * waste the pages skipped for the alignment; * they become struct pv_entry pages. */ + pv_region = addr; mfctl(CR_HPTMASK, size); addr = (addr + size) & ~(size); pv_free_list = NULL; @@ -786,85 +822,172 @@ pmap_bootstrap(vstart, vend) proc0.p_md.md_regs->tf_vtop = addr; addr += size + 1; + /* Allocate the struct pv_entry lists heads array. */ + addr = ALIGN(addr); + pv_head_tbl = (struct pv_entry **) addr; + memset(pv_head_tbl, 0, sizeof(*pv_head_tbl) * totalphysmem); + addr = (vaddr_t) (pv_head_tbl + totalphysmem); + + /* Allocate the page modified/referenced flags table. */ + addr = ALIGN(addr); + pv_flags_tbl = (u_char *) addr; + memset(pv_flags_tbl, 0, sizeof(*pv_flags_tbl) * totalphysmem); + addr = (vaddr_t) (pv_flags_tbl + totalphysmem); + /* - * we know that btlb_insert() will round it up to the next - * power of two at least anyway + * Allocate the largest struct pv_entry region. The + * 6 is a magic constant, chosen to allow on average + * all physical pages to have 6 simultaneous mappings + * without having to reclaim any struct pv_entry. */ - for (physmem = 1; physmem < btoc(addr); physmem *= 2); - - /* map the kernel space, which will give us virtual_start */ - *vstart = hppa_round_page(addr + (totalphysmem - physmem) * - (sizeof(struct pv_entry) * maxproc / 8 + - sizeof(struct vm_page))); - /* XXX PCXS needs two separate inserts in separate btlbs */ + pv_region = addr; + addr += sizeof(struct pv_entry) * totalphysmem * 6; + pmap_pv_add(pv_region, addr); /* - * We want to offer kernel NULL pointer dereference - * detection, and write protection for the kernel text. - * To keep things simple, we use BTLB entries to directly - * map the kernel text, data, bss, and anything else we've - * allocated (directly-mapped) space for already. The - * region from 0 to the start of the kernel text is unmapped. + * Allocate the steal region. Because pmap_steal_memory + * must panic whenever an allocation cannot be fulfilled, + * we have to guess at the maximum amount of space that + * might be stolen. Overestimating is not really a problem, + * as it only leads to lost virtual space, not lost physical + * pages. + */ + addr = hppa_round_page(addr); + virtual_steal = addr; + addr += totalphysmem * sizeof(struct vm_page); + memset((caddr_t) virtual_steal, 0, addr - virtual_steal); + + /* + * We now have a rough idea of where managed kernel virtual + * space will begin, and we can start mapping everything + * before that. + */ + addr = hppa_round_page(addr); + *vstart = addr; + + /* + * In general, the virtual space below the kernel text is + * left unmapped, to allow detection of NULL dereferences. + * However, these tmp_vpages are two virtual pages right + * before the kernel text that can be mapped for page copying + * and zeroing. + */ + tmp_vpages[1] = hppa_trunc_page((vaddr_t) &kernel_text) - PAGE_SIZE; + tmp_vpages[0] = tmp_vpages[1] - PAGE_SIZE; + + /* + * The kernel text, data, and bss must be direct-mapped, + * because the kernel often runs in physical mode, and + * anyways the loader loaded the kernel into physical + * memory exactly where it was linked. * - * Note that a BTLB entry must be some power-of-two pages - * in size, and must be aligned on that size. This is - * why we insist that the kernel text start no earlier than - * 0x80000 (the minimum BTLB entry eize), why we need - * multiple entries to do the job, and why 100% of the - * kernel text isn't necessarily protected (one BTLB - * entry may need to cover both text and data). + * All memory already allocated after bss, either by + * our caller or by this function itself, must also be + * direct-mapped, because it's completely unmanaged + * and was allocated in physical mode. + * + * BTLB entries are used to do this direct mapping. + * BTLB entries have a minimum and maximum possible size, + * and MD code gives us these sizes in units of pages. */ - - /* XXX fredette - we should get this from machdep.c. */ - btlb_entry_min = (vsize_t) &kernel_text; + btlb_entry_min = (vsize_t) hppa_btlb_size_min * PAGE_SIZE; + btlb_entry_max = (vsize_t) hppa_btlb_size_max * PAGE_SIZE; /* - * The address of the start of the kernel text must - * be some multiple of the minimum BTLB entry size. + * We begin by making BTLB entries for the kernel text. + * To keep things simple, we insist that the kernel text + * be aligned to the minimum BTLB entry size. */ - btlb_entry_start[0] = (vaddr_t) &kernel_text; - if (btlb_entry_start[0] & (btlb_entry_min - 1)) - panic("kernel text start incompatible with BTLB minimum"); - btlb_entry_size[0] = btlb_entry_min; - btlb_entry_vm_prot[0] = VM_PROT_READ | VM_PROT_EXECUTE; - if (btlb_entry_start[0] + btlb_entry_size[0] > (vaddr_t) &etext) - btlb_entry_vm_prot[0] |= VM_PROT_WRITE; - btlb_j = 1; + if (((vaddr_t) &kernel_text) & (btlb_entry_min - 1)) + panic("kernel text not aligned to BTLB minimum size"); /* - * All BTLB entries allow reading. Any BTLB entry - * that maps kernel text also allows execution. Any - * BTLB entry that maps data+bss also allows writing. + * To try to conserve BTLB entries, take a hint from how + * the kernel was linked: take the kernel text start as + * our effective minimum BTLB entry size, assuming that + * the data segment was also aligned to that size. + * + * In practice, linking the kernel at 2MB, and aligning + * the data segment to a 2MB boundary, should control well + * how much of the BTLB the pmap uses. However, this code + * should not rely on this 2MB magic number, nor should + * it rely on the data segment being aligned at all. This + * is to allow (smaller) kernels (linked lower) to work fine. */ - do { + btlb_entry_min = (vaddr_t) &kernel_text; + __asm __volatile ( + " ldil L%%$global$, %0 \n" + " ldo R%%$global$(%0), %0 \n" + : "=r" (kernel_data)); + + /* + * Now make BTLB entries to direct-map the kernel text + * read- and execute-only as much as possible. Note that + * if the data segment isn't nicely aligned, the last + * BTLB entry for the kernel text may also cover some of + * the data segment, meaning it will have to allow writing. + */ + addr = (vaddr_t) &kernel_text; + btlb_j = 0; + while (addr < (vaddr_t) &etext) { /* Set up the next BTLB entry. */ KASSERT(btlb_j < BTLB_SET_SIZE); - btlb_entry_start[btlb_j] = - btlb_entry_start[btlb_j - 1] + - btlb_entry_size[btlb_j - 1]; + btlb_entry_start[btlb_j] = addr; btlb_entry_size[btlb_j] = btlb_entry_min; - btlb_entry_vm_prot[btlb_j] = VM_PROT_READ; - if (btlb_entry_start[btlb_j] < (vaddr_t) &etext) - btlb_entry_vm_prot[btlb_j] |= VM_PROT_EXECUTE; - if ((btlb_entry_start[btlb_j] + btlb_entry_size[btlb_j]) > - (vaddr_t) &etext) + btlb_entry_vm_prot[btlb_j] = VM_PROT_READ | VM_PROT_EXECUTE; + if (addr + btlb_entry_min > kernel_data) btlb_entry_vm_prot[btlb_j] |= VM_PROT_WRITE; - /* As we can, aggregate BTLB entries. */ + /* Coalesce BTLB entries whenever possible. */ while (btlb_j > 0 && btlb_entry_vm_prot[btlb_j] == btlb_entry_vm_prot[btlb_j - 1] && btlb_entry_size[btlb_j] == btlb_entry_size[btlb_j - 1] && !(btlb_entry_start[btlb_j - 1] & - ((btlb_entry_size[btlb_j - 1] << 1) - 1))) + ((btlb_entry_size[btlb_j - 1] << 1) - 1)) && + (btlb_entry_size[btlb_j - 1] << 1) <= + btlb_entry_max) btlb_entry_size[--btlb_j] <<= 1; /* Move on. */ + addr = btlb_entry_start[btlb_j] + btlb_entry_size[btlb_j]; btlb_j++; - } while ((btlb_entry_start[btlb_j - 1] + btlb_entry_size[btlb_j - 1]) < *vstart); - + } + + /* + * Now make BTLB entries to direct-map the kernel data, + * bss, and all of the preallocated space read-write. + * + * Note that, unlike above, we're not concerned with + * making these BTLB entries such that they finish as + * close as possible to the end of the space we need + * them to map. Instead, to minimize the number of BTLB + * entries we need, we make them as large as possible. + * The only thing this wastes is kernel virtual space, + * which is plentiful. + */ + while (addr < *vstart) { + + /* Make the next BTLB entry. */ + KASSERT(btlb_j < BTLB_SET_SIZE); + size = btlb_entry_min; + while ((addr + size) < *vstart && + (size << 1) < btlb_entry_max && + !(addr & ((size << 1) - 1))) + size <<= 1; + btlb_entry_start[btlb_j] = addr; + btlb_entry_size[btlb_j] = size; + btlb_entry_vm_prot[btlb_j] = VM_PROT_READ | VM_PROT_WRITE; + + /* Move on. */ + addr = btlb_entry_start[btlb_j] + btlb_entry_size[btlb_j]; + btlb_j++; + } + + /* XXX PCXS needs two separate inserts in separate btlbs */ + /* Now insert all of the BTLB entries. */ for (btlb_i = 0; btlb_i < btlb_j; btlb_i++) { btlb_entry_got = btlb_entry_size[btlb_i]; @@ -880,50 +1003,54 @@ pmap_bootstrap(vstart, vend) panic("pmap_bootstrap: BTLB entry mapped wrong amount"); } + /* + * We now know the exact beginning of managed kernel + * virtual space. + */ *vstart = btlb_entry_start[btlb_j - 1] + btlb_entry_size[btlb_j - 1]; virtual_start = *vstart; /* - * NOTE: we no longer trash the BTLB w/ unused entries, - * lazy map only needed pieces (see bus_mem_add_mapping() for refs). + * Finally, load physical pages into UVM. There are + * three segments of pages. */ - - /* - * Allocate the struct pv_entry heads table and the flags table - * for the physical pages. - */ - size = hppa_round_page(totalphysmem * - (sizeof(*pv_head_tbl) + - sizeof(struct pv_entry) + - sizeof(*pv_flags_tbl))); - bzero ((caddr_t)addr, size); -#ifdef PMAPDEBUG - if (pmapdebug & PDB_INIT) - printf("pv_array: 0x%x @ %p\n", (u_int)size, (caddr_t)addr); + physmem = 0; + + /* The first segment runs from [resvmem..kernel_text). */ + phys_start = resvmem; + phys_end = atop(hppa_trunc_page(&kernel_text)); +#ifdef DIAGNOSTIC + printf("phys segment: 0x%x 0x%x\n", (u_int)phys_start, (u_int)phys_end); #endif + if (phys_end > phys_start) { + uvm_page_physload(phys_start, phys_end, + phys_start, phys_end, VM_FREELIST_DEFAULT); + physmem += phys_end - phys_start; + } - virtual_steal = addr + size; - virtual_steal = round_page(virtual_steal); - uvm_page_physload(atop(virtual_steal), totalphysmem, - atop(virtual_steal), totalphysmem, VM_FREELIST_DEFAULT); - /* we have only one initial phys memory segment */ - pv_head_tbl = (struct pv_entry **)addr; - pv_region = (vaddr_t)(pv_head_tbl + totalphysmem); - pv_flags_tbl = (u_char *)(pv_region + - totalphysmem * sizeof(struct pv_entry)); - pmap_pv_add(pv_region, (vaddr_t) pv_flags_tbl); - vm_physmem[0].pmseg.pmap_table_off = atop(virtual_start); + /* The second segment runs from [etext..kernel_data). */ + phys_start = atop(hppa_round_page((vaddr_t) &etext)); + phys_end = atop(hppa_trunc_page(kernel_data)); +#ifdef DIAGNOSTIC + printf("phys segment: 0x%x 0x%x\n", (u_int)phys_start, (u_int)phys_end); +#endif + if (phys_end > phys_start) { + uvm_page_physload(phys_start, phys_end, + phys_start, phys_end, VM_FREELIST_DEFAULT); + physmem += phys_end - phys_start; + } - /* here will be a hole due to the kernel memory alignment - and we use it for pmap_steal_memory */ - - /* - * The tmp_vpages are two virtual pages that can be - * mapped for the copying and zeroing operations. - * We use two pages immediately before the kernel text. - */ - tmp_vpages[1] = hppa_trunc_page((vaddr_t) &kernel_text) - PAGE_SIZE; - tmp_vpages[0] = tmp_vpages[1] - PAGE_SIZE; + /* The third segment runs from [virtual_steal..totalphysmem). */ + phys_start = atop(virtual_steal); + phys_end = totalphysmem; +#ifdef DIAGNOSTIC + printf("phys segment: 0x%x 0x%x\n", (u_int)phys_start, (u_int)phys_end); +#endif + if (phys_end > phys_start) { + uvm_page_physload(phys_start, phys_end, + phys_start, phys_end, VM_FREELIST_DEFAULT); + physmem += phys_end - phys_start; + } } /* @@ -939,6 +1066,7 @@ pmap_steal_memory(size, startp, endp) vaddr_t *endp; { vaddr_t va; + int lcv; PMAP_PRINTF(PDB_STEAL, ("(%lx, %p, %p)\n", size, startp, endp)); @@ -958,25 +1086,15 @@ pmap_steal_memory(size, startp, endp) /* Steal the memory. */ va = virtual_steal; virtual_steal += size; - PMAP_PRINTF(PDB_STEAL, (": steal %ld bytes (%x+%x,%x)\n", - size, (u_int)va, (u_int)size, (u_int)virtual_start)); - - /* - * We are an unusual pmap in that we really, really - * want to steal the rest of the directly-mapped - * segment for struct pv_entries, after UVM has done - * all of its stealing. The tricky part is detecting - * when UVM is doing the last of its stealing. - * For now, we key off of uvmexp.ncolors being set - * to 1, which it is by uvm_page_init before it - * does the final stealing. - */ - if (uvmexp.ncolors == 1) { - virtual_stolen = virtual_steal; - virtual_steal = virtual_start; - vm_physmem[0].avail_start = atop(virtual_start); - vm_physmem[0].start = vm_physmem[0].avail_start; - } + PMAP_PRINTF(PDB_STEAL, (": steal %ld bytes @%x\n", size, (u_int)va)); + for (lcv = 0; lcv < vm_nphysseg ; lcv++) + if (vm_physmem[lcv].start == atop(va)) { + vm_physmem[lcv].start = atop(virtual_steal); + vm_physmem[lcv].avail_start = atop(virtual_steal); + break; + } + if (lcv == vm_nphysseg) + panic("pmap_steal_memory inconsistency"); return va; } @@ -1002,34 +1120,6 @@ void pmap_init() { extern void gateway_page __P((void)); -#ifdef notyet - vaddr_t va; -#endif - - /* allocate the rest of the steal area for pv_entries */ - pmap_pv_add(virtual_stolen, virtual_start); - -#ifdef notyet - /* - * Enter direct mappings for many of the physical - * pages below the tmp_vpages, so we can put them - * to good use as pv_entry pages and not waste them. - */ - /* - * XXX this is a poorly named constant. It should - * probably get a better name or maybe its value - * should be VM_MIN_KERNEL_ADDRESS in vmparam.h. - * Note that it is the old kernel text start - * address. Pages below this are assumed to belong - * to the firmware. - */ -#define LOW_MEM_PAGES 0x12000 - for (va = LOW_MEM_PAGES; - (va + NBPG) <= tmp_vpages[0]; - va += NBPG) - pmap_kenter_pa(va, va, VM_PROT_ALL); - pmap_pv_add(LOW_MEM_PAGES, va); -#endif /* notyet */ TAILQ_INIT(&pmap_freelist); pid_counter = HPPA_PID_KERNEL + 2; @@ -1041,7 +1131,7 @@ pmap_init() * * no spls since no interrupts */ - pmap_pv_enter(pmap_kernel(), HPPA_SID_KERNEL, SYSCALLGATE, + pmap_pv_enter(NULL, HPPA_SID_KERNEL, SYSCALLGATE, (paddr_t)&gateway_page, TLB_GATE_PROT); pmap_initialized = TRUE; @@ -1538,8 +1628,6 @@ pmap_zero_page(pa) PMAP_PRINTF(PDB_ZERO, ("(%p)\n", (caddr_t)pa)); - KASSERT(!pmap_initialized || pa >= virtual_start); - s = splvm(); /* XXX are we already that high? */ /* Map the physical page. */ @@ -1573,8 +1661,6 @@ pmap_copy_page(spa, dpa) PMAP_PRINTF(PDB_COPY, ("(%p, %p)\n", (caddr_t)spa, (caddr_t)dpa)); - KASSERT(!pmap_initialized || (spa >= virtual_start && dpa >= virtual_start)); - s = splvm(); /* XXX are we already that high? */ /* Map the two pages. */ diff --git a/sys/arch/hppa/include/vmparam.h b/sys/arch/hppa/include/vmparam.h index 85e9df73f5b5..e7f976774bee 100644 --- a/sys/arch/hppa/include/vmparam.h +++ b/sys/arch/hppa/include/vmparam.h @@ -1,4 +1,4 @@ -/* $NetBSD: vmparam.h,v 1.1 2002/06/05 01:04:23 fredette Exp $ */ +/* $NetBSD: vmparam.h,v 1.2 2002/08/05 20:58:35 fredette Exp $ */ /* $OpenBSD: vmparam.h,v 1.17 2001/09/22 18:00:09 miod Exp $ */ @@ -44,8 +44,6 @@ #define HIGHPAGES UPAGES #define SYSCALLGATE 0xC0000000 /* syscall gateway page */ -#define __HAVE_PMAP_PHYSSEG - /* Alignment requirement for a uspace. */ #define USPACE_ALIGN NBPG @@ -106,15 +104,8 @@ #define VM_PHYSSEG_NOADD /* XXX until uvm code is fixed */ -#define VM_NFREELIST 2 +#define VM_NFREELIST 1 #define VM_FREELIST_DEFAULT 0 -#define VM_FREELIST_FIRST16 1 - -#ifdef _KERNEL -struct pmap_physseg { - int pmap_table_off; -}; -#endif #endif /* _HPPA_VMPARAM_H_ */