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Introduce PMAP_TLBDEBUG option for ibm4xx: clear only TLBHI[V] bit when

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TLB entry is invalidated, instead of clearing entire TLBHI register.
This commit is contained in:
rin 2020-09-10 03:32:46 +00:00
parent d15d990682
commit 169faeb037
2 changed files with 52 additions and 21 deletions
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4
sys/arch/powerpc/conf/files.powerpc
View File

@ -1,11 +1,11 @@
# $NetBSD: files.powerpc,v 1.94 2020/06/30 16:20:01 maxv Exp $
# $NetBSD: files.powerpc,v 1.95 2020/09/10 03:32:46 rin Exp $
defflag opt_altivec.h ALTIVEC K_ALTIVEC PPC_HAVE_SPE
defflag opt_openpic.h OPENPIC_DISTRIBUTE
defparam opt_ppcparam.h L2CR_CONFIG L3CR_CONFIG INTSTK CLOCKBASE VERBOSE_INITPPC
defflag opt_ppcarch.h PPC_OEA PPC_OEA601 PPC_OEA64 PPC_OEA64_BRIDGE PPC_MPC8XX PPC_IBM4XX PPC_IBM403 PPC_IBM440 PPC_BOOKE
defflag opt_ppccache.h CACHE_PROTO_MEI
defflag opt_pmap.h PMAPDEBUG PMAPCHECK PMAPCOUNTERS PMAP_MINIMALTLB
defflag opt_pmap.h PMAPDEBUG PMAPCHECK PMAPCOUNTERS PMAP_MINIMALTLB PMAP_TLBDEBUG
defparam opt_pmap.h PTEGCOUNT PMAP_MEMLIMIT
file arch/powerpc/powerpc/core_machdep.c coredump

69
sys/arch/powerpc/ibm4xx/pmap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.92 2020/09/10 03:23:55 rin Exp $ */
/* $NetBSD: pmap.c,v 1.93 2020/09/10 03:32:46 rin Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -67,10 +67,11 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.92 2020/09/10 03:23:55 rin Exp $");
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.93 2020/09/10 03:32:46 rin Exp $");
#ifdef _KERNEL_OPT
#include "opt_ddb.h"
#include "opt_pmap.h"
#endif
#include <sys/param.h>
@ -193,6 +194,8 @@ static inline int pte_enter(struct pmap *, vaddr_t, u_int);
static inline int pmap_enter_pv(struct pmap *, vaddr_t, paddr_t, int);
static void pmap_remove_pv(struct pmap *, vaddr_t, paddr_t);
static inline void tlb_invalidate_entry(int);
static int ppc4xx_tlb_size_mask(size_t, int *, int *);
@ -1195,6 +1198,43 @@ pmap_procwr(struct proc *p, vaddr_t va, size_t len)
"K" (PSL_IR | PSL_DR));
}
static inline void
tlb_invalidate_entry(int i)
{
#ifdef PMAP_TLBDEBUG
/*
* Clear only TLBHI[V] bit so that we can track invalidated entry.
*/
register_t msr, pid, hi;
KASSERT(mfspr(SPR_PID) == KERNEL_PID);
__asm volatile(
"mfmsr %0;"
"li %1,0;"
"mtmsr %1;"
"mfpid %1;"
"tlbre %2,%3,0;"
"andc %2,%2,%4;"
"tlbwe %2,%3,0;"
"mtpid %1;"
"mtmsr %0;"
"isync;"
: "=&r" (msr), "=&r" (pid), "=&r" (hi)
: "r" (i), "r" (TLB_VALID));
#else
/*
* Just clear entire TLBHI register.
*/
__asm volatile(
"tlbwe %0,%1,0;"
"isync;"
: : "r" (0), "r" (i));
#endif
tlb_info[i].ti_ctx = 0;
tlb_info[i].ti_flags = 0;
}
/* This has to be done in real mode !!! */
void
@ -1228,13 +1268,7 @@ ppc4xx_tlb_flush(vaddr_t va, int pid)
: "r" (va), "r" (pid));
if (found && !TLB_LOCKED(i)) {
/* Now flush translation */
__asm volatile(
"tlbwe %0,%1,0;"
"isync;"
: : "r" (0), "r" (i));
tlb_info[i].ti_ctx = 0;
tlb_info[i].ti_flags = 0;
tlb_invalidate_entry(i);
tlbnext = i;
/* Successful flushes */
tlbflush_ev.ev_count++;
@ -1247,12 +1281,8 @@ ppc4xx_tlb_flush_all(void)
u_long i;
for (i = 0; i < NTLB; i++)
if (!TLB_LOCKED(i)) {
__asm volatile(
"tlbwe %0,%1,0;" : : "r" (0), "r" (i));
tlb_info[i].ti_ctx = 0;
tlb_info[i].ti_flags = 0;
}
if (!TLB_LOCKED(i))
tlb_invalidate_entry(i);
__asm volatile("isync");
}
@ -1526,10 +1556,11 @@ ctx_flush(int cnum)
if (i < tlb_nreserved)
panic("TLB entry %d not locked", i);
#endif
/* Invalidate particular TLB entry regardless of locked status */
__asm volatile("tlbwe %0,%1,0" : :"r"(0),"r"(i));
tlb_info[i].ti_ctx = 0;
tlb_info[i].ti_flags = 0;
/*
* Invalidate particular TLB entry regardless of
* locked status
*/
tlb_invalidate_entry(i);
}
}
return (0);