Introduce PMAP_TLBDEBUG option for ibm4xx: clear only TLBHI[V] bit when
TLB entry is invalidated, instead of clearing entire TLBHI register.
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@ -1,11 +1,11 @@
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# $NetBSD: files.powerpc,v 1.94 2020/06/30 16:20:01 maxv Exp $
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# $NetBSD: files.powerpc,v 1.95 2020/09/10 03:32:46 rin Exp $
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defflag opt_altivec.h ALTIVEC K_ALTIVEC PPC_HAVE_SPE
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defflag opt_openpic.h OPENPIC_DISTRIBUTE
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defparam opt_ppcparam.h L2CR_CONFIG L3CR_CONFIG INTSTK CLOCKBASE VERBOSE_INITPPC
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defflag opt_ppcarch.h PPC_OEA PPC_OEA601 PPC_OEA64 PPC_OEA64_BRIDGE PPC_MPC8XX PPC_IBM4XX PPC_IBM403 PPC_IBM440 PPC_BOOKE
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defflag opt_ppccache.h CACHE_PROTO_MEI
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defflag opt_pmap.h PMAPDEBUG PMAPCHECK PMAPCOUNTERS PMAP_MINIMALTLB
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defflag opt_pmap.h PMAPDEBUG PMAPCHECK PMAPCOUNTERS PMAP_MINIMALTLB PMAP_TLBDEBUG
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defparam opt_pmap.h PTEGCOUNT PMAP_MEMLIMIT
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file arch/powerpc/powerpc/core_machdep.c coredump
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.92 2020/09/10 03:23:55 rin Exp $ */
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/* $NetBSD: pmap.c,v 1.93 2020/09/10 03:32:46 rin Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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@ -67,10 +67,11 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.92 2020/09/10 03:23:55 rin Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.93 2020/09/10 03:32:46 rin Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_ddb.h"
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#include "opt_pmap.h"
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#endif
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#include <sys/param.h>
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@ -193,6 +194,8 @@ static inline int pte_enter(struct pmap *, vaddr_t, u_int);
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static inline int pmap_enter_pv(struct pmap *, vaddr_t, paddr_t, int);
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static void pmap_remove_pv(struct pmap *, vaddr_t, paddr_t);
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static inline void tlb_invalidate_entry(int);
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static int ppc4xx_tlb_size_mask(size_t, int *, int *);
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@ -1195,6 +1198,43 @@ pmap_procwr(struct proc *p, vaddr_t va, size_t len)
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"K" (PSL_IR | PSL_DR));
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}
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static inline void
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tlb_invalidate_entry(int i)
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{
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#ifdef PMAP_TLBDEBUG
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/*
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* Clear only TLBHI[V] bit so that we can track invalidated entry.
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*/
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register_t msr, pid, hi;
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KASSERT(mfspr(SPR_PID) == KERNEL_PID);
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__asm volatile(
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"mfmsr %0;"
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"li %1,0;"
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"mtmsr %1;"
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"mfpid %1;"
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"tlbre %2,%3,0;"
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"andc %2,%2,%4;"
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"tlbwe %2,%3,0;"
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"mtpid %1;"
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"mtmsr %0;"
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"isync;"
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: "=&r" (msr), "=&r" (pid), "=&r" (hi)
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: "r" (i), "r" (TLB_VALID));
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#else
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/*
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* Just clear entire TLBHI register.
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*/
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__asm volatile(
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"tlbwe %0,%1,0;"
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"isync;"
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: : "r" (0), "r" (i));
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#endif
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tlb_info[i].ti_ctx = 0;
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tlb_info[i].ti_flags = 0;
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}
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/* This has to be done in real mode !!! */
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void
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@ -1228,13 +1268,7 @@ ppc4xx_tlb_flush(vaddr_t va, int pid)
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: "r" (va), "r" (pid));
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if (found && !TLB_LOCKED(i)) {
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/* Now flush translation */
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__asm volatile(
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"tlbwe %0,%1,0;"
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"isync;"
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: : "r" (0), "r" (i));
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tlb_info[i].ti_ctx = 0;
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tlb_info[i].ti_flags = 0;
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tlb_invalidate_entry(i);
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tlbnext = i;
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/* Successful flushes */
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tlbflush_ev.ev_count++;
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@ -1247,12 +1281,8 @@ ppc4xx_tlb_flush_all(void)
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u_long i;
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for (i = 0; i < NTLB; i++)
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if (!TLB_LOCKED(i)) {
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__asm volatile(
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"tlbwe %0,%1,0;" : : "r" (0), "r" (i));
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tlb_info[i].ti_ctx = 0;
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tlb_info[i].ti_flags = 0;
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}
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if (!TLB_LOCKED(i))
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tlb_invalidate_entry(i);
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__asm volatile("isync");
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}
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@ -1526,10 +1556,11 @@ ctx_flush(int cnum)
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if (i < tlb_nreserved)
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panic("TLB entry %d not locked", i);
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#endif
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/* Invalidate particular TLB entry regardless of locked status */
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__asm volatile("tlbwe %0,%1,0" : :"r"(0),"r"(i));
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tlb_info[i].ti_ctx = 0;
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tlb_info[i].ti_flags = 0;
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/*
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* Invalidate particular TLB entry regardless of
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* locked status
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*/
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tlb_invalidate_entry(i);
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}
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}
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return (0);
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