Rewrite the ARM mutex implementation to be of the simple-mutex variety.
Because pre-v6 ARM lacks support for an atomic compare-and-swap, we implement _lock_cas() as a restartable atomic squence that is checked in the IRQ handler right before AST processing. (This is safe because, for all practical purposes, there are no SMP pre-v6 ARM systems.) This can serve as a model for other non-MP platforms that lack the necessary atomic operations for mutexes (SuperH, for example). Upshots of this change: - kmutex_t is now down to 8 bytes on ARM; about as good as we can get. - ARM2 systems don't have to trap and emulate SWP or SWPB for mutexes. The acorn26 port is not updated by this commit to do the LOCK_CAS_CHECK. That is left as an exercise for the port maintainer. Reviewed and tested by Matt Thomas.
This commit is contained in:
thorpej
parent
b1c0dd5ffc
commit
165d4e6d83
@ -1,4 +1,4 @@
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/* $NetBSD: arm_machdep.c,v 1.13 2007/02/09 21:55:02 ad Exp $ */
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/* $NetBSD: arm_machdep.c,v 1.14 2007/03/09 19:21:57 thorpej Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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@ -73,10 +73,11 @@
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#include "opt_compat_netbsd.h"
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#include "opt_execfmt.h"
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#include "opt_arm_debug.h"
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#include <sys/param.h>
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__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.13 2007/02/09 21:55:02 ad Exp $");
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__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.14 2007/03/09 19:21:57 thorpej Exp $");
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#include <sys/exec.h>
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#include <sys/proc.h>
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@ -84,6 +85,7 @@ __KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.13 2007/02/09 21:55:02 ad Exp $");
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#include <sys/user.h>
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#include <sys/pool.h>
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#include <sys/ucontext.h>
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#include <sys/evcnt.h>
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#include <arm/cpufunc.h>
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@ -102,6 +104,24 @@ __KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.13 2007/02/09 21:55:02 ad Exp $");
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*/
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vaddr_t vector_page;
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#if defined(ARM_LOCK_CAS_DEBUG)
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/*
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* Event counters for tracking activity of the RAS-based _lock_cas()
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* routine.
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*/
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struct evcnt _lock_cas_restart =
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EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "_lock_cas", "restart");
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EVCNT_ATTACH_STATIC(_lock_cas_restart);
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struct evcnt _lock_cas_success =
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EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "_lock_cas", "success");
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EVCNT_ATTACH_STATIC(_lock_cas_success);
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struct evcnt _lock_cas_fail =
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EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "_lock_cas", "fail");
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EVCNT_ATTACH_STATIC(_lock_cas_fail);
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#endif /* ARM_LOCK_CAS_DEBUG */
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/*
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* Clear registers on exec
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*/
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@ -1,4 +1,4 @@
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# $NetBSD: genassym.cf,v 1.31 2007/02/20 00:05:14 matt Exp $
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# $NetBSD: genassym.cf,v 1.32 2007/03/09 19:21:57 thorpej Exp $
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# Copyright (c) 1982, 1990 The Regents of the University of California.
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# All rights reserved.
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@ -142,6 +142,8 @@ define TF_R0 offsetof(struct trapframe, tf_r0)
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define TF_R10 offsetof(struct trapframe, tf_r10)
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define TF_PC offsetof(struct trapframe, tf_pc)
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define IF_PC offsetof(struct irqframe, if_pc)
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define PROCSIZE sizeof(struct proc)
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define TRAPFRAMESIZE sizeof(struct trapframe)
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@ -1,4 +1,4 @@
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/* $NetBSD: irq_dispatch.S,v 1.7 2005/12/11 12:16:41 christos Exp $ */
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/* $NetBSD: irq_dispatch.S,v 1.8 2007/03/09 19:21:58 thorpej Exp $ */
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/*
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* Copyright (c) 2002 Fujitsu Component Limited
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@ -94,6 +94,8 @@
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.Lcurrent_intr_depth:
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.word _C_LABEL(current_intr_depth)
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LOCK_CAS_CHECK_LOCALS
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AST_ALIGNMENT_FAULT_LOCALS
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ASENTRY_NP(irq_entry)
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@ -125,6 +127,8 @@ ASENTRY_NP(irq_entry)
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*/
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str r6, [r5]
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LOCK_CAS_CHECK
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DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
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PULLFRAMEFROMSVCANDEXIT
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movs pc, lr /* Exit */
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@ -1,4 +1,4 @@
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# $NetBSD: files.arm,v 1.82 2007/01/06 00:50:54 christos Exp $
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# $NetBSD: files.arm,v 1.83 2007/03/09 19:21:58 thorpej Exp $
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# temporary define to allow easy moving to ../arch/arm/arm32
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defflag ARM32
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@ -23,6 +23,9 @@ defflag opt_cpuoptions.h ARM9_CACHE_WRITE_THROUGH
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# Interrupt implementation header definition.
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defparam opt_arm_intr_impl.h ARM_INTR_IMPL
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# ARM-specific debug options
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defflag opt_arm_debug.h ARM_LOCK_CAS_DEBUG
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# Board-specific bus_space(9) definitions
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defflag opt_arm_bus_space.h __BUS_SPACE_HAS_STREAM_METHODS
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@ -115,6 +118,7 @@ file arch/arm/arm/cpufunc_asm_xscale.S cpu_xscale_80200 |
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cpu_xscale_pxa250 |
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cpu_xscale_pxa270
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file arch/arm/arm/cpufunc_asm_ixp12x0.S cpu_ixp12x0
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file arch/arm/arm/lock_cas.S
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file arch/arm/arm/process_machdep.c
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file arch/arm/arm/procfs_machdep.c procfs
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file arch/arm/arm/sig_machdep.c
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@ -1,4 +1,4 @@
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/* $NetBSD: frame.h,v 1.14 2006/09/27 21:42:05 manu Exp $ */
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/* $NetBSD: frame.h,v 1.15 2007/03/09 19:21:58 thorpej Exp $ */
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/*
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* Copyright (c) 1994-1997 Mark Brinicombe.
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@ -111,6 +111,7 @@ void validate_trapframe __P((trapframe_t *, int));
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#include "opt_compat_netbsd.h"
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#include "opt_execfmt.h"
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#include "opt_multiprocessor.h"
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#include "opt_arm_debug.h"
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/*
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* AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS
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@ -267,6 +268,55 @@ void validate_trapframe __P((trapframe_t *, int));
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2:
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#endif /* EXEC_AOUT */
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#ifdef ARM_LOCK_CAS_DEBUG
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#define LOCK_CAS_DEBUG_LOCALS \
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.L_lock_cas_restart: ;\
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.word _C_LABEL(_lock_cas_restart)
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#if defined(__ARMEB__)
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#define LOCK_CAS_DEBUG_COUNT_RESTART \
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ble 99f ;\
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ldr r0, .L_lock_cas_restart ;\
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ldmia r0, {r1-r2} /* load ev_count */ ;\
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adds r2, r2, #1 /* 64-bit incr (lo) */ ;\
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adc r1, r1, #0 /* 64-bit incr (hi) */ ;\
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stmia r0, {r1-r2} /* store ev_count */
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#else /* __ARMEB__ */
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#define LOCK_CAS_DEBUG_COUNT_RESTART \
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ble 99f ;\
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ldr r0, .L_lock_cas_restart ;\
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ldmia r0, {r1-r2} /* load ev_count */ ;\
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adds r1, r1, #1 /* 64-bit incr (lo) */ ;\
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adc r2, r2, #0 /* 64-bit incr (hi) */ ;\
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stmia r0, {r1-r2} /* store ev_count */
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#endif /* __ARMEB__ */
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#else /* ARM_LOCK_CAS_DEBUG */
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#define LOCK_CAS_DEBUG_LOCALS /* nothing */
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#define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */
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#endif /* ARM_LOCK_CAS_DEBUG */
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#define LOCK_CAS_CHECK_LOCALS \
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.L_lock_cas: ;\
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.word _C_LABEL(_lock_cas) ;\
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.L_lock_cas_end: ;\
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.word _C_LABEL(_lock_cas_end) ;\
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LOCK_CAS_DEBUG_LOCALS
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#define LOCK_CAS_CHECK \
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ldr r0, [sp] /* get saved PSR */ ;\
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and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\
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teq r0, #(PSR_SVC32_MODE) ;\
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bne 99f /* nope, get out now */ ;\
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ldr r0, [sp, #(IF_PC)] ;\
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ldr r1, .L_lock_cas_end ;\
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cmp r0, r1 ;\
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bge 99f ;\
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ldr r1, .L_lock_cas ;\
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cmp r0, r1 ;\
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strgt r1, [sp, #(IF_PC)] ;\
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LOCK_CAS_DEBUG_COUNT_RESTART ;\
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99:
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/*
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* ASM macros for pushing and pulling trapframes from the stack
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*
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@ -1,4 +1,4 @@
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/* $NetBSD: mutex.h,v 1.6 2007/03/09 11:30:28 skrll Exp $ */
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/* $NetBSD: mutex.h,v 1.7 2007/03/09 19:21:58 thorpej Exp $ */
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/*-
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* Copyright (c) 2002, 2007 The NetBSD Foundation, Inc.
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@ -41,155 +41,68 @@
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/*
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* The ARM mutex implementation is troublesome, because pre-v6 ARM lacks a
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* compare-and-set operation. However, there aren't any MP pre-v6 ARM
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* compare-and-swap operation. However, there aren't any MP pre-v6 ARM
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* systems to speak of. We are mostly concerned with atomicity with respect
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* to interrupts.
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*
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* SMP for spin mutexes is easy - we don't need to know who owns the lock.
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* For adaptive mutexes, we need an additional interlock.
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* ARMv6, however, does have ldrex/strex, and can thus implement an MP-safe
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* compare-and-swap.
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*
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* Unfortunately, not all ARM kernels are linked at the same address,
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* meaning we cannot safely overlay the interlock with the MSB of the
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* owner field.
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*
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* For a mutex acquisition, we first grab the interlock and then set the
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* owner field.
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*
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* There is room in the owners field for a waiters bit, but we don't do
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* that because it would be hard to synchronize using one without a CAS
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* operation. Because the waiters bit is only needed for adaptive mutexes,
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* we instead use the lock that is normally used by spin mutexes to indicate
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* waiters.
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*
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* Spin mutexes are initialized with the interlock held to cause the
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* assembly stub to go through mutex_vector_enter().
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*
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* When releasing an adaptive mutex, we first clear the owners field, and
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* then check to see if the waiters byte is set. This ensures that there
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* will always be someone to wake any sleeping waiters up (even it the mutex
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* is acquired immediately after we release it, or if we are preempted
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* immediatley after clearing the owners field). The setting or clearing of
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* the waiters byte is serialized by the turnstile chain lock associated
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* with the mutex.
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*
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* See comments in kern_mutex.c about releasing adaptive mutexes without
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* an interlocking step.
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* So, what we have done is impement simple mutexes using a compare-and-swap.
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* We support pre-ARMv6 by implementing _lock_cas() as a restartable atomic
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* sequence that is checked by the IRQ vector. MP-safe ARMv6 support will
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* be added later.
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*/
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#ifndef __MUTEX_PRIVATE
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struct kmutex {
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uintptr_t mtx_pad1;
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uint32_t mtx_pad2[2];
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uint32_t mtx_pad2;
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};
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#else /* __MUTEX_PRIVATE */
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struct kmutex {
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volatile uintptr_t mtx_owner; /* 0-3 */
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__cpu_simple_lock_t mtx_interlock; /* 4 */
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__cpu_simple_lock_t mtx_lock; /* 5 */
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ipl_cookie_t mtx_ipl; /* 6 */
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uint8_t mtx_pad; /* 7 */
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uint32_t mtx_id; /* 8-11 */
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union {
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/* Adaptive mutex */
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volatile uintptr_t mtxa_owner; /* 0-3 */
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/* Spin mutex */
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struct {
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volatile uint8_t mtxs_dummy;
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ipl_cookie_t mtxs_ipl;
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__cpu_simple_lock_t mtxs_lock;
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volatile uint8_t mtxs_unused;
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} s;
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} u;
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volatile uint32_t mtx_id; /* 4-7 */
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};
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#define mtx_owner u.mtxa_owner
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#define mtx_ipl u.s.mtxs_ipl
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#define mtx_lock u.s.mtxs_lock
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#if 0
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#define __HAVE_MUTEX_STUBS 1
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#define __HAVE_SPIN_MUTEX_STUBS 1
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#define __HAVE_MUTEX_STUBS 1
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#define __HAVE_SPIN_MUTEX_STUBS 1
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#endif
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#define __HAVE_SIMPLE_MUTEXES 1
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static inline uintptr_t
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MUTEX_OWNER(uintptr_t owner)
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{
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return owner;
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}
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/*
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* MUTEX_RECEIVE: no memory barrier required; we're synchronizing against
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* interrupts, not multiple processors.
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*/
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#define MUTEX_RECEIVE(mtx) /* nothing */
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static inline int
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MUTEX_OWNED(uintptr_t owner)
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{
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return owner != 0;
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}
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/*
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* MUTEX_GIVE: no memory barrier required; same reason.
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*/
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#define MUTEX_GIVE(mtx) /* nothing */
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static inline int
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MUTEX_SET_WAITERS(kmutex_t *mtx, uintptr_t owner)
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{
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(void)__cpu_simple_lock_try(&mtx->mtx_lock);
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return mtx->mtx_owner != 0;
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}
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bool _lock_cas(volatile uintptr_t *, uintptr_t, uintptr_t);
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static inline void
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MUTEX_CLEAR_WAITERS(kmutex_t *mtx)
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{
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__cpu_simple_unlock(&mtx->mtx_lock);
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}
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static inline int
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MUTEX_HAS_WAITERS(volatile kmutex_t *mtx)
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{
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if (mtx->mtx_owner == 0)
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return 0;
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return mtx->mtx_lock == __SIMPLELOCK_LOCKED;
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}
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static inline void
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MUTEX_INITIALIZE_SPIN(kmutex_t *mtx, u_int id, int ipl)
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{
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mtx->mtx_id = (id << 1) | 1;
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mtx->mtx_ipl = makeiplcookie(ipl);
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mtx->mtx_interlock = __SIMPLELOCK_LOCKED;
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__cpu_simple_lock_init(&mtx->mtx_lock);
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}
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static inline void
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MUTEX_INITIALIZE_ADAPTIVE(kmutex_t *mtx, u_int id)
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{
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mtx->mtx_id = (id << 1) | 0;
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__cpu_simple_lock_init(&mtx->mtx_interlock);
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__cpu_simple_lock_init(&mtx->mtx_lock);
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}
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static inline void
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MUTEX_DESTROY(kmutex_t *mtx)
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{
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mtx->mtx_owner = (uintptr_t)-1L;
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mtx->mtx_id = ~0;
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}
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static inline u_int
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MUTEX_GETID(kmutex_t *mtx)
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{
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return mtx->mtx_id >> 1;
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}
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static inline bool
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MUTEX_SPIN_P(volatile kmutex_t *mtx)
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{
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return (mtx->mtx_id & 1) == 1;
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}
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static inline bool
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MUTEX_ADAPTIVE_P(volatile kmutex_t *mtx)
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{
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return (mtx->mtx_id & 1) == 0;
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}
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static inline int
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MUTEX_ACQUIRE(kmutex_t *mtx, uintptr_t curthread)
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{
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if (!__cpu_simple_lock_try(&mtx->mtx_interlock))
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return 0;
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mtx->mtx_owner = curthread;
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return 1;
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}
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static inline void
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MUTEX_RELEASE(kmutex_t *mtx)
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{
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mtx->mtx_owner = 0;
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__cpu_simple_unlock(&mtx->mtx_lock);
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__cpu_simple_unlock(&mtx->mtx_interlock);
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}
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#define MUTEX_CAS(p, o, n) _lock_cas((p), (o), (n))
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#endif /* __MUTEX_PRIVATE */
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@ -1,4 +1,4 @@
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/* $NetBSD: iomd_irq.S,v 1.5 2005/12/11 12:16:47 christos Exp $ */
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/* $NetBSD: iomd_irq.S,v 1.6 2007/03/09 19:21:58 thorpej Exp $ */
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/*
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* Copyright (c) 1994-1998 Mark Brinicombe.
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@ -96,6 +96,8 @@ Lcurrent_intr_depth:
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Lspl_masks:
|
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.word _C_LABEL(spl_masks)
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|
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LOCK_CAS_CHECK_LOCALS
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AST_ALIGNMENT_FAULT_LOCALS
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|
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/*
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@ -337,6 +339,8 @@ exitirq:
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sub r1, r1, #1
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str r1, [r0]
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|
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LOCK_CAS_CHECK
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|
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DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
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PULLFRAMEFROMSVCANDEXIT
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|
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|
||||
@ -1,4 +1,4 @@
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/* $NetBSD: ofw_irq.S,v 1.6 2007/03/08 20:48:39 matt Exp $ */
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/* $NetBSD: ofw_irq.S,v 1.7 2007/03/09 19:21:59 thorpej Exp $ */
|
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|
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/*
|
||||
* Copyright (c) 1994-1998 Mark Brinicombe.
|
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@ -93,6 +93,8 @@ Lirq_entry:
|
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Lofwirqstk: /* hack */
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.word ofwirqstk + 4096
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|
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LOCK_CAS_CHECK_LOCALS
|
||||
|
||||
AST_ALIGNMENT_FAULT_LOCALS
|
||||
|
||||
/*
|
||||
@ -325,6 +327,8 @@ nextirq:
|
||||
sub r1, r1, #1
|
||||
str r1, [r0]
|
||||
|
||||
LOCK_CAS_CHECK
|
||||
|
||||
DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
|
||||
PULLFRAMEFROMSVCANDEXIT
|
||||
movs pc, lr /* Exit */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: sa11x0_irq.S,v 1.9 2006/03/05 11:30:58 peter Exp $ */
|
||||
/* $NetBSD: sa11x0_irq.S,v 1.10 2007/03/09 19:21:59 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1998 Mark Brinicombe.
|
||||
@ -67,6 +67,8 @@ Ldbg_str:
|
||||
.asciz "irq_entry %x %x\n"
|
||||
#endif
|
||||
|
||||
LOCK_CAS_CHECK_LOCALS
|
||||
|
||||
AST_ALIGNMENT_FAULT_LOCALS
|
||||
|
||||
/*
|
||||
@ -244,6 +246,8 @@ nextirq:
|
||||
sub r1, r1, #1
|
||||
str r1, [r0]
|
||||
|
||||
LOCK_CAS_CHECK
|
||||
|
||||
DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
|
||||
PULLFRAMEFROMSVCANDEXIT
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: i80200_irq.S,v 1.13 2005/12/11 12:16:51 christos Exp $ */
|
||||
/* $NetBSD: i80200_irq.S,v 1.14 2007/03/09 19:21:59 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Wasabi Systems, Inc.
|
||||
@ -65,6 +65,8 @@
|
||||
.word _C_LABEL(xscale_pmc_dispatch)
|
||||
#endif
|
||||
|
||||
LOCK_CAS_CHECK_LOCALS
|
||||
|
||||
AST_ALIGNMENT_FAULT_LOCALS
|
||||
|
||||
ASENTRY_NP(irq_entry)
|
||||
@ -128,6 +130,8 @@ ASENTRY_NP(irq_entry)
|
||||
sub r1, r1, #1
|
||||
str r1, [r0]
|
||||
|
||||
LOCK_CAS_CHECK
|
||||
|
||||
DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
|
||||
PULLFRAMEFROMSVCANDEXIT
|
||||
movs pc, lr /* Exit */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: isa_irq.S,v 1.6 2007/03/08 20:48:39 matt Exp $ */
|
||||
/* $NetBSD: isa_irq.S,v 1.7 2007/03/09 19:21:59 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright 1997
|
||||
@ -289,6 +289,8 @@ nextirq:
|
||||
sub r1, r1, #1
|
||||
str r1, [r0]
|
||||
|
||||
LOCK_CAS_CHECK
|
||||
|
||||
DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
|
||||
PULLFRAMEFROMSVCANDEXIT
|
||||
|
||||
@ -301,6 +303,8 @@ Lspl_mask:
|
||||
Lcurrent_mask:
|
||||
.word _C_LABEL(current_mask) /* irq's that are usable */
|
||||
|
||||
LOCK_CAS_CHECK_LOCALS
|
||||
|
||||
AST_ALIGNMENT_FAULT_LOCALS
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user