Make register definitions compatible with Ultrix
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mellon
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@ -1,4 +1,4 @@
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/* $NetBSD: reg.h,v 1.4 1994/10/26 21:09:57 cgd Exp $ */
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/* $NetBSD: reg.h,v 1.5 1995/01/18 06:40:12 mellon Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -79,51 +79,55 @@
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#define SP 29
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#define S8 30
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#define RA 31
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#define MULLO 32
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#define MULHI 33
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#define PC 34
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#define SR 35
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#define PS 35 /* alias for SR */
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#define F0 36
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#define F1 37
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#define F2 38
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#define F3 39
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#define F4 40
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#define F5 41
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#define F6 42
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#define F7 43
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#define F8 44
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#define F9 45
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#define F10 46
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#define F11 47
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#define F12 48
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#define F13 49
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#define F14 50
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#define F15 51
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#define F16 52
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#define F17 53
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#define F18 54
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#define F19 55
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#define F20 56
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#define F21 57
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#define F22 58
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#define F23 59
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#define F24 60
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#define F25 61
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#define F26 62
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#define F27 63
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#define F28 64
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#define F29 65
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#define F30 66
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#define F31 67
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#define FSR 68
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#define SR 32
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#define PS SR /* alias for SR */
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#define MULLO 33
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#define MULHI 34
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#define BADVADDR 35
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#define CAUSE 36
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#define PC 37
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#define FPBASE 38
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#define F0 (FPBASE+0)
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#define F1 (FPBASE+1)
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#define F2 (FPBASE+2)
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#define F3 (FPBASE+3)
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#define F4 (FPBASE+4)
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#define F5 (FPBASE+5)
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#define F6 (FPBASE+6)
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#define F7 (FPBASE+7)
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#define F8 (FPBASE+8)
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#define F9 (FPBASE+9)
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#define F10 (FPBASE+10)
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#define F11 (FPBASE+11)
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#define F12 (FPBASE+12)
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#define F13 (FPBASE+13)
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#define F14 (FPBASE+14)
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#define F15 (FPBASE+15)
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#define F16 (FPBASE+16)
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#define F17 (FPBASE+17)
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#define F18 (FPBASE+18)
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#define F19 (FPBASE+19)
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#define F20 (FPBASE+20)
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#define F21 (FPBASE+21)
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#define F22 (FPBASE+22)
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#define F23 (FPBASE+23)
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#define F24 (FPBASE+24)
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#define F25 (FPBASE+25)
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#define F26 (FPBASE+26)
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#define F27 (FPBASE+27)
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#define F28 (FPBASE+28)
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#define F29 (FPBASE+29)
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#define F30 (FPBASE+30)
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#define F31 (FPBASE+31)
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#define FSR (FPBASE+32)
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#ifdef IPCREG
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#define NIPCREG 69
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#define NIPCREG (FSR + 1)
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int ipcreg[NIPCREG] = {
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ZERO, AST, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7,
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S0, S1, S2, S3, S4, S5, S6, S7, T8, T9, K0, K1, GP, SP, S8, RA,
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MULLO, MULHI, PC,
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SR, MULLO, MULHI, BADVADDR, CAUSE, PC,
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F0, F1, F2, F3, F4, F5, F6, F7,
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F8, F9, F10, F11, F12, F13, F14, F15,
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F16, F17, F18, F19, F20, F21, F22, F23,
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@ -136,6 +140,6 @@ int ipcreg[NIPCREG] = {
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* Register set accessible via /proc/$pid/reg
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*/
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struct reg {
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int r_regs[69]; /* numbered as above */
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int r_regs[71]; /* numbered as above */
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};
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#endif /* LANGUAGE_C */
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@ -1,4 +1,4 @@
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/* $NetBSD: reg.h,v 1.4 1994/10/26 21:09:57 cgd Exp $ */
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/* $NetBSD: reg.h,v 1.5 1995/01/18 06:40:12 mellon Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -79,51 +79,55 @@
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#define SP 29
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#define S8 30
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#define RA 31
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#define MULLO 32
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#define MULHI 33
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#define PC 34
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#define SR 35
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#define PS 35 /* alias for SR */
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#define F0 36
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#define F1 37
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#define F2 38
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#define F3 39
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#define F4 40
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#define F5 41
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#define F6 42
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#define F7 43
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#define F8 44
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#define F9 45
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#define F10 46
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#define F11 47
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#define F12 48
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#define F13 49
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#define F14 50
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#define F15 51
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#define F16 52
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#define F17 53
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#define F18 54
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#define F19 55
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#define F20 56
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#define F21 57
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#define F22 58
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#define F23 59
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#define F24 60
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#define F25 61
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#define F26 62
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#define F27 63
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#define F28 64
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#define F29 65
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#define F30 66
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#define F31 67
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#define FSR 68
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#define SR 32
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#define PS SR /* alias for SR */
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#define MULLO 33
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#define MULHI 34
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#define BADVADDR 35
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#define CAUSE 36
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#define PC 37
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#define FPBASE 38
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#define F0 (FPBASE+0)
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#define F1 (FPBASE+1)
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#define F2 (FPBASE+2)
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#define F3 (FPBASE+3)
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#define F4 (FPBASE+4)
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#define F5 (FPBASE+5)
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#define F6 (FPBASE+6)
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#define F7 (FPBASE+7)
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#define F8 (FPBASE+8)
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#define F9 (FPBASE+9)
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#define F10 (FPBASE+10)
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#define F11 (FPBASE+11)
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#define F12 (FPBASE+12)
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#define F13 (FPBASE+13)
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#define F14 (FPBASE+14)
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#define F15 (FPBASE+15)
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#define F16 (FPBASE+16)
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#define F17 (FPBASE+17)
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#define F18 (FPBASE+18)
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#define F19 (FPBASE+19)
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#define F20 (FPBASE+20)
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#define F21 (FPBASE+21)
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#define F22 (FPBASE+22)
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#define F23 (FPBASE+23)
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#define F24 (FPBASE+24)
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#define F25 (FPBASE+25)
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#define F26 (FPBASE+26)
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#define F27 (FPBASE+27)
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#define F28 (FPBASE+28)
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#define F29 (FPBASE+29)
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#define F30 (FPBASE+30)
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#define F31 (FPBASE+31)
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#define FSR (FPBASE+32)
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#ifdef IPCREG
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#define NIPCREG 69
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#define NIPCREG (FSR + 1)
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int ipcreg[NIPCREG] = {
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ZERO, AST, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7,
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S0, S1, S2, S3, S4, S5, S6, S7, T8, T9, K0, K1, GP, SP, S8, RA,
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MULLO, MULHI, PC,
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SR, MULLO, MULHI, BADVADDR, CAUSE, PC,
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F0, F1, F2, F3, F4, F5, F6, F7,
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F8, F9, F10, F11, F12, F13, F14, F15,
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F16, F17, F18, F19, F20, F21, F22, F23,
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@ -136,6 +140,6 @@ int ipcreg[NIPCREG] = {
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* Register set accessible via /proc/$pid/reg
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*/
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struct reg {
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int r_regs[69]; /* numbered as above */
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int r_regs[71]; /* numbered as above */
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};
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#endif /* LANGUAGE_C */
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