Add driver for ARM PrimeCell MultiMedia Card Interface (PL181). Not tested
with real hardware, only qemu "integratorcp" configuration.
This commit is contained in:
jmcneill
parent
5f67668838
commit
14e804e4a7
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@ -0,0 +1,423 @@
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/* $NetBSD: pl181.c,v 1.1 2015/01/27 16:33:26 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pl181.c,v 1.1 2015/01/27 16:33:26 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <dev/sdmmc/sdmmcvar.h>
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#include <dev/sdmmc/sdmmcchip.h>
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#include <dev/sdmmc/sdmmc_ioreg.h>
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#include <dev/ic/pl181reg.h>
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#include <dev/ic/pl181var.h>
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static int plmmc_host_reset(sdmmc_chipset_handle_t);
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static uint32_t plmmc_host_ocr(sdmmc_chipset_handle_t);
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static int plmmc_host_maxblklen(sdmmc_chipset_handle_t);
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static int plmmc_card_detect(sdmmc_chipset_handle_t);
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static int plmmc_write_protect(sdmmc_chipset_handle_t);
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static int plmmc_bus_power(sdmmc_chipset_handle_t, uint32_t);
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static int plmmc_bus_clock(sdmmc_chipset_handle_t, int);
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static int plmmc_bus_width(sdmmc_chipset_handle_t, int);
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static int plmmc_bus_rod(sdmmc_chipset_handle_t, int);
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static void plmmc_exec_command(sdmmc_chipset_handle_t,
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struct sdmmc_command *);
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static void plmmc_card_enable_intr(sdmmc_chipset_handle_t, int);
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static void plmmc_card_intr_ack(sdmmc_chipset_handle_t);
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static int plmmc_wait_status(struct plmmc_softc *, uint32_t, int);
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static int plmmc_pio_wait(struct plmmc_softc *,
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struct sdmmc_command *);
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static int plmmc_pio_transfer(struct plmmc_softc *,
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struct sdmmc_command *);
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static struct sdmmc_chip_functions plmmc_chip_functions = {
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.host_reset = plmmc_host_reset,
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.host_ocr = plmmc_host_ocr,
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.host_maxblklen = plmmc_host_maxblklen,
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.card_detect = plmmc_card_detect,
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.write_protect = plmmc_write_protect,
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.bus_power = plmmc_bus_power,
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.bus_clock = plmmc_bus_clock,
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.bus_width = plmmc_bus_width,
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.bus_rod = plmmc_bus_rod,
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.exec_command = plmmc_exec_command,
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.card_enable_intr = plmmc_card_enable_intr,
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.card_intr_ack = plmmc_card_intr_ack,
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};
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#define MMCI_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
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#define MMCI_READ(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
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void
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plmmc_init(struct plmmc_softc *sc)
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{
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struct sdmmcbus_attach_args saa;
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mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO);
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cv_init(&sc->sc_intr_cv, "plmmcirq");
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#ifdef PLMMC_DEBUG
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device_printf(sc->sc_dev, "PeriphID %#x %#x %#x %#x\n",
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MMCI_READ(sc, MMCI_PERIPH_ID0_REG),
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MMCI_READ(sc, MMCI_PERIPH_ID1_REG),
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MMCI_READ(sc, MMCI_PERIPH_ID2_REG),
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MMCI_READ(sc, MMCI_PERIPH_ID3_REG));
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device_printf(sc->sc_dev, "PCellID %#x %#x %#x %#x\n",
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MMCI_READ(sc, MMCI_PCELL_ID0_REG),
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MMCI_READ(sc, MMCI_PCELL_ID1_REG),
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MMCI_READ(sc, MMCI_PCELL_ID2_REG),
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MMCI_READ(sc, MMCI_PCELL_ID3_REG));
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#endif
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plmmc_bus_clock(sc, 400);
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MMCI_WRITE(sc, MMCI_POWER_REG, 0);
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delay(10000);
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MMCI_WRITE(sc, MMCI_POWER_REG, MMCI_POWER_CTRL_POWERUP);
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delay(10000);
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MMCI_WRITE(sc, MMCI_POWER_REG, MMCI_POWER_CTRL_POWERON);
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plmmc_host_reset(sc);
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memset(&saa, 0, sizeof(saa));
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saa.saa_busname = "sdmmc";
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saa.saa_sct = &plmmc_chip_functions;
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saa.saa_sch = sc;
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saa.saa_clkmin = 400;
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saa.saa_clkmax = sc->sc_clock_freq / 1000;
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saa.saa_caps = 0;
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sc->sc_sdmmc_dev = config_found(sc->sc_dev, &saa, NULL);
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}
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int
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plmmc_intr(void *priv)
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{
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struct plmmc_softc *sc = priv;
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uint32_t status;
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mutex_enter(&sc->sc_intr_lock);
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status = MMCI_READ(sc, MMCI_STATUS_REG);
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#ifdef PLMMC_DEBUG
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printf("%s: MMCI_STATUS_REG = %#x\n", __func__, status);
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#endif
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if (!status) {
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mutex_exit(&sc->sc_intr_lock);
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return 0;
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}
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sc->sc_intr_status |= status;
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cv_broadcast(&sc->sc_intr_cv);
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mutex_exit(&sc->sc_intr_lock);
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return 1;
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}
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static int
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plmmc_wait_status(struct plmmc_softc *sc, uint32_t mask, int timeout)
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{
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int retry, error;
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KASSERT(mutex_owned(&sc->sc_intr_lock));
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if (sc->sc_intr_status & mask)
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return 0;
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retry = timeout / hz;
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if (sc->sc_ih == NULL)
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retry *= 1000;
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while (retry > 0) {
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if (sc->sc_ih == NULL) {
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sc->sc_intr_status |= MMCI_READ(sc, MMCI_STATUS_REG);
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if (sc->sc_intr_status & mask)
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return 0;
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delay(10000);
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} else {
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error = cv_timedwait(&sc->sc_intr_cv,
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&sc->sc_intr_lock, hz);
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if (error && error != EWOULDBLOCK) {
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device_printf(sc->sc_dev,
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"cv_timedwait returned %d\n", error);
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return error;
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}
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if (sc->sc_intr_status & mask)
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return 0;
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}
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--retry;
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}
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device_printf(sc->sc_dev, "%s timeout, MMCI_STATUS_REG = %#x\n",
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__func__, MMCI_READ(sc, MMCI_STATUS_REG));
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return ETIMEDOUT;
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}
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static int
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plmmc_pio_wait(struct plmmc_softc *sc, struct sdmmc_command *cmd)
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{
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uint32_t bit = (cmd->c_flags & SCF_CMD_READ) ?
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MMCI_INT_RX_DATA_AVAIL : MMCI_INT_TX_FIFO_EMPTY;
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MMCI_WRITE(sc, MMCI_CLEAR_REG, bit);
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const int error = plmmc_wait_status(sc,
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bit | MMCI_INT_DATA_END | MMCI_INT_DATA_BLOCK_END, hz*2);
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sc->sc_intr_status &= ~bit;
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return error;
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}
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static int
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plmmc_pio_transfer(struct plmmc_softc *sc, struct sdmmc_command *cmd)
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{
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uint32_t *datap = (uint32_t *)cmd->c_data;
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int i;
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cmd->c_resid = cmd->c_datalen;
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for (i = 0; i < (cmd->c_datalen >> 2); i++) {
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if (plmmc_pio_wait(sc, cmd))
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return ETIMEDOUT;
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if (cmd->c_flags & SCF_CMD_READ) {
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datap[i] = MMCI_READ(sc, MMCI_FIFO_REG);
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} else {
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MMCI_WRITE(sc, MMCI_FIFO_REG, datap[i]);
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}
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cmd->c_resid -= 4;
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}
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return 0;
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}
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static int
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plmmc_host_reset(sdmmc_chipset_handle_t sch)
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{
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struct plmmc_softc *sc = sch;
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MMCI_WRITE(sc, MMCI_MASK0_REG, 0);
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MMCI_WRITE(sc, MMCI_MASK1_REG, 0);
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MMCI_WRITE(sc, MMCI_CLEAR_REG, 0xffffffff);
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return 0;
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}
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static uint32_t
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plmmc_host_ocr(sdmmc_chipset_handle_t sch)
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{
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return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V;
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}
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static int
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plmmc_host_maxblklen(sdmmc_chipset_handle_t sch)
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{
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return 2048;
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}
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static int
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plmmc_card_detect(sdmmc_chipset_handle_t sch)
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{
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return 1;
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}
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static int
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plmmc_write_protect(sdmmc_chipset_handle_t sch)
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{
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return 0;
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}
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static int
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plmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
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{
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return 0;
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}
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static int
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plmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
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{
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struct plmmc_softc *sc = sch;
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u_int pll_freq, clk_div;
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uint32_t clock;
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clock = MMCI_CLOCK_PWRSAVE;
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if (freq) {
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pll_freq = sc->sc_clock_freq / 1000;
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clk_div = (howmany(pll_freq, freq) >> 1) - 1;
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clock |= __SHIFTIN(clk_div, MMCI_CLOCK_CLKDIV);
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clock |= MMCI_CLOCK_ENABLE;
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}
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MMCI_WRITE(sc, MMCI_CLOCK_REG, clock);
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return 0;
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}
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static int
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plmmc_bus_width(sdmmc_chipset_handle_t sch, int width)
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{
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return 0;
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}
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static int
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plmmc_bus_rod(sdmmc_chipset_handle_t sch, int on)
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{
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struct plmmc_softc *sc = sch;
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uint32_t power;
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power = MMCI_READ(sc, MMCI_POWER_REG);
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if (on) {
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power |= MMCI_POWER_ROD;
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} else {
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power &= ~MMCI_POWER_ROD;
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}
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MMCI_WRITE(sc, MMCI_POWER_REG, power);
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return 0;
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}
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static void
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plmmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
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{
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struct plmmc_softc *sc = sch;
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uint32_t cmdval = MMCI_COMMAND_ENABLE;
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#ifdef PLMMC_DEBUG
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device_printf(sc->sc_dev, "opcode %d flags %#x datalen %d\n",
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cmd->c_opcode, cmd->c_flags, cmd->c_datalen);
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#endif
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mutex_enter(&sc->sc_intr_lock);
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MMCI_WRITE(sc, MMCI_COMMAND_REG, 0);
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MMCI_WRITE(sc, MMCI_MASK0_REG, 0);
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MMCI_WRITE(sc, MMCI_CLEAR_REG, 0xffffffff);
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MMCI_WRITE(sc, MMCI_MASK0_REG,
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MMCI_INT_CMD_TIMEOUT | MMCI_INT_DATA_TIMEOUT |
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MMCI_INT_RX_DATA_AVAIL | MMCI_INT_TX_FIFO_EMPTY |
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MMCI_INT_DATA_END | MMCI_INT_DATA_BLOCK_END |
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MMCI_INT_CMD_RESP_END | MMCI_INT_CMD_SENT);
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sc->sc_intr_status = 0;
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if (cmd->c_flags & SCF_RSP_PRESENT)
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cmdval |= MMCI_COMMAND_RESPONSE;
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if (cmd->c_flags & SCF_RSP_136)
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cmdval |= MMCI_COMMAND_LONGRSP;
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if (cmd->c_datalen > 0) {
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unsigned int nblks = cmd->c_datalen / cmd->c_blklen;
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if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0)
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++nblks;
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const uint32_t dir = (cmd->c_flags & SCF_CMD_READ) ? 1 : 0;
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const uint32_t blksize = ffs(cmd->c_blklen) - 1;
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MMCI_WRITE(sc, MMCI_DATA_TIMER_REG, 0xffffffff);
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MMCI_WRITE(sc, MMCI_DATA_LENGTH_REG, nblks * cmd->c_blklen);
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MMCI_WRITE(sc, MMCI_DATA_CTRL_REG,
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__SHIFTIN(dir, MMCI_DATA_CTRL_DIRECTION) |
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__SHIFTIN(blksize, MMCI_DATA_CTRL_BLOCKSIZE) |
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MMCI_DATA_CTRL_ENABLE);
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}
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MMCI_WRITE(sc, MMCI_ARGUMENT_REG, cmd->c_arg);
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MMCI_WRITE(sc, MMCI_COMMAND_REG, cmdval | cmd->c_opcode);
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if (cmd->c_datalen > 0) {
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cmd->c_error = plmmc_pio_transfer(sc, cmd);
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if (cmd->c_error) {
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device_printf(sc->sc_dev,
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"error (%d) waiting for xfer\n", cmd->c_error);
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goto done;
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}
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}
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if (cmd->c_flags & SCF_RSP_PRESENT) {
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cmd->c_error = plmmc_wait_status(sc,
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MMCI_INT_CMD_RESP_END|MMCI_INT_CMD_TIMEOUT, hz * 2);
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if (cmd->c_error == 0 &&
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(sc->sc_intr_status & MMCI_INT_CMD_TIMEOUT)) {
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cmd->c_error = ETIMEDOUT;
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}
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if (cmd->c_error) {
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#ifdef PLMMC_DEBUG
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device_printf(sc->sc_dev,
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"error (%d) waiting for resp\n", cmd->c_error);
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#endif
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goto done;
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}
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if (cmd->c_flags & SCF_RSP_136) {
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cmd->c_resp[3] = MMCI_READ(sc, MMCI_RESP0_REG);
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cmd->c_resp[2] = MMCI_READ(sc, MMCI_RESP1_REG);
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cmd->c_resp[1] = MMCI_READ(sc, MMCI_RESP2_REG);
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cmd->c_resp[0] = MMCI_READ(sc, MMCI_RESP3_REG);
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if (cmd->c_flags & SCF_RSP_CRC) {
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cmd->c_resp[0] = (cmd->c_resp[0] >> 8) |
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(cmd->c_resp[1] << 24);
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cmd->c_resp[1] = (cmd->c_resp[1] >> 8) |
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(cmd->c_resp[2] << 24);
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cmd->c_resp[2] = (cmd->c_resp[2] >> 8) |
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(cmd->c_resp[3] << 24);
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cmd->c_resp[3] = (cmd->c_resp[3] >> 8);
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}
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} else {
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cmd->c_resp[0] = MMCI_READ(sc, MMCI_RESP0_REG);
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}
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}
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done:
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cmd->c_flags |= SCF_ITSDONE;
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MMCI_WRITE(sc, MMCI_COMMAND_REG, 0);
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MMCI_WRITE(sc, MMCI_MASK0_REG, 0);
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MMCI_WRITE(sc, MMCI_CLEAR_REG, 0xffffffff);
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MMCI_WRITE(sc, MMCI_DATA_CNT_REG, 0);
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#ifdef PLMMC_DEBUG
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device_printf(sc->sc_dev, "MMCI_STATUS_REG = %#x\n",
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MMCI_READ(sc, MMCI_STATUS_REG));
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#endif
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mutex_exit(&sc->sc_intr_lock);
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}
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static void
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plmmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable)
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{
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}
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static void
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plmmc_card_intr_ack(sdmmc_chipset_handle_t sch)
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{
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}
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@ -0,0 +1,116 @@
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/* $NetBSD: pl181reg.h,v 1.1 2015/01/27 16:33:26 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _PL181REG_H
|
||||
#define _PL181REG_H
|
||||
|
||||
#define MMCI_POWER_REG 0x000
|
||||
#define MMCI_CLOCK_REG 0x004
|
||||
#define MMCI_ARGUMENT_REG 0x008
|
||||
#define MMCI_COMMAND_REG 0x00c
|
||||
#define MMCI_RESP_CMD_REG 0x010
|
||||
#define MMCI_RESP0_REG 0x014
|
||||
#define MMCI_RESP1_REG 0x018
|
||||
#define MMCI_RESP2_REG 0x01c
|
||||
#define MMCI_RESP3_REG 0x020
|
||||
#define MMCI_DATA_TIMER_REG 0x024
|
||||
#define MMCI_DATA_LENGTH_REG 0x028
|
||||
#define MMCI_DATA_CTRL_REG 0x02c
|
||||
#define MMCI_DATA_CNT_REG 0x030
|
||||
#define MMCI_STATUS_REG 0x034
|
||||
#define MMCI_CLEAR_REG 0x038
|
||||
#define MMCI_MASK0_REG 0x03c
|
||||
#define MMCI_MASK1_REG 0x040
|
||||
#define MMCI_FIFO_CNT_REG 0x048
|
||||
#define MMCI_FIFO_REG 0x080
|
||||
#define MMCI_PERIPH_ID0_REG 0xfe0
|
||||
#define MMCI_PERIPH_ID1_REG 0xfe4
|
||||
#define MMCI_PERIPH_ID2_REG 0xfe8
|
||||
#define MMCI_PERIPH_ID3_REG 0xfec
|
||||
#define MMCI_PCELL_ID0_REG 0xff0
|
||||
#define MMCI_PCELL_ID1_REG 0xff4
|
||||
#define MMCI_PCELL_ID2_REG 0xff8
|
||||
#define MMCI_PCELL_ID3_REG 0xffc
|
||||
|
||||
#define MMCI_POWER_CTRL __BITS(1,0)
|
||||
#define MMCI_POWER_CTRL_OFF 0
|
||||
#define MMCI_POWER_CTRL_POWERUP 2
|
||||
#define MMCI_POWER_CTRL_POWERON 3
|
||||
#define MMCI_POWER_VOLTAGE __BITS(5,2)
|
||||
#define MMCI_POWER_OD __BIT(6)
|
||||
#define MMCI_POWER_ROD __BIT(7)
|
||||
|
||||
#define MMCI_CLOCK_CLKDIV __BITS(7,0)
|
||||
#define MMCI_CLOCK_ENABLE __BIT(8)
|
||||
#define MMCI_CLOCK_PWRSAVE __BIT(9)
|
||||
#define MMCI_CLOCK_BYPASS __BIT(10)
|
||||
|
||||
#define MMCI_COMMAND_CMDINDEX __BITS(5,0)
|
||||
#define MMCI_COMMAND_RESPONSE __BIT(6)
|
||||
#define MMCI_COMMAND_LONGRSP __BIT(7)
|
||||
#define MMCI_COMMAND_INTERRUPT __BIT(8)
|
||||
#define MMCI_COMMAND_PENDING __BIT(9)
|
||||
#define MMCI_COMMAND_ENABLE __BIT(10)
|
||||
|
||||
#define MMCI_RESP_CMD __BITS(5,0)
|
||||
|
||||
#define MMCI_DATA_LENGTH __BITS(15,0)
|
||||
|
||||
#define MMCI_DATA_CTRL_ENABLE __BIT(0)
|
||||
#define MMCI_DATA_CTRL_DIRECTION __BIT(1)
|
||||
#define MMCI_DATA_CTRL_MODE __BIT(2)
|
||||
#define MMCI_DATA_CTRL_DMAENABLE __BIT(3)
|
||||
#define MMCI_DATA_CTRL_BLOCKSIZE __BITS(7,4)
|
||||
|
||||
#define MMCI_DATA_CNT __BITS(15,0)
|
||||
|
||||
#define MMCI_INT_CMD_CRC_FAIL __BIT(0)
|
||||
#define MMCI_INT_DATA_CRC_FAIL __BIT(1)
|
||||
#define MMCI_INT_CMD_TIMEOUT __BIT(2)
|
||||
#define MMCI_INT_DATA_TIMEOUT __BIT(3)
|
||||
#define MMCI_INT_TX_UNDERRUN __BIT(4)
|
||||
#define MMCI_INT_RX_OVERRUN __BIT(5)
|
||||
#define MMCI_INT_CMD_RESP_END __BIT(6)
|
||||
#define MMCI_INT_CMD_SENT __BIT(7)
|
||||
#define MMCI_INT_DATA_END __BIT(8)
|
||||
#define MMCI_INT_DATA_BLOCK_END __BIT(10)
|
||||
#define MMCI_INT_CMD_ACTIVE __BIT(11)
|
||||
#define MMCI_INT_TX_ACTIVE __BIT(12)
|
||||
#define MMCI_INT_RX_ACTIVE __BIT(13)
|
||||
#define MMCI_INT_TX_FIFO_HALF_EMPTY __BIT(14)
|
||||
#define MMCI_INT_RX_FIFO_HALF_FULL __BIT(15)
|
||||
#define MMCI_INT_TX_FIFO_FULL __BIT(16)
|
||||
#define MMCI_INT_RX_FIFO_FULL __BIT(17)
|
||||
#define MMCI_INT_TX_FIFO_EMPTY __BIT(18)
|
||||
#define MMCI_INT_RX_FIFO_EMPTY __BIT(19)
|
||||
#define MMCI_INT_TX_DATA_AVAIL __BIT(20)
|
||||
#define MMCI_INT_RX_DATA_AVAIL __BIT(21)
|
||||
|
||||
#define MMCI_FIFO_CNT __BITS(14,0)
|
||||
|
||||
#endif /* !_PL181REG_H */
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/* $NetBSD: pl181var.h,v 1.1 2015/01/27 16:33:26 jmcneill Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _PL181VAR_H
|
||||
#define _PL181VAR_H
|
||||
|
||||
struct plmmc_softc {
|
||||
device_t sc_dev;
|
||||
bus_space_tag_t sc_bst;
|
||||
bus_space_handle_t sc_bsh;
|
||||
void *sc_ih;
|
||||
unsigned int sc_clock_freq;
|
||||
|
||||
device_t sc_sdmmc_dev;
|
||||
kmutex_t sc_intr_lock;
|
||||
kcondvar_t sc_intr_cv;
|
||||
|
||||
uint32_t sc_intr_status;
|
||||
};
|
||||
|
||||
void plmmc_init(struct plmmc_softc *);
|
||||
int plmmc_intr(void *);
|
||||
|
||||
#endif /* !_PL181VAR_H */
|
||||
Loading…
Reference in New Issue