- Make new wm_phy_post_reset() and use this function at all location after
reseting phy. - Move the location of calling wm_get_hw_control. Same as Linux. - Add I219 specific wokaround for legacy interrupt. From OpenBSD. - Move the location of calling wm_lplu_d0_disable(). - Fix latency calculation in wm_platform_pm_pch_lpt(). - Set OBFF water mark and enable OBFF on PCH_LPT and newer.
This commit is contained in:
msaitoh
parent
f99b415579
commit
14a58cc1cc
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@ -1,4 +1,4 @@
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/* $NetBSD: if_wm.c,v 1.516 2017/06/26 04:18:14 msaitoh Exp $ */
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/* $NetBSD: if_wm.c,v 1.517 2017/06/26 04:22:46 msaitoh Exp $ */
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/*
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* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
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@ -84,7 +84,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.516 2017/06/26 04:18:14 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.517 2017/06/26 04:22:46 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_net_mpsafe.h"
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@ -679,6 +679,7 @@ static void wm_set_pcie_completion_timeout(struct wm_softc *);
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static void wm_get_auto_rd_done(struct wm_softc *);
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static void wm_lan_init_done(struct wm_softc *);
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static void wm_get_cfg_done(struct wm_softc *);
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static void wm_phy_post_reset(struct wm_softc *);
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static void wm_initialize_hardware_bits(struct wm_softc *);
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static uint32_t wm_rxpbs_adjust_82580(uint32_t);
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static void wm_reset_phy(struct wm_softc *);
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@ -930,6 +931,7 @@ static bool wm_phy_is_accessible_pchlan(struct wm_softc *);
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static void wm_toggle_lanphypc_pch_lpt(struct wm_softc *);
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static int wm_platform_pm_pch_lpt(struct wm_softc *, bool);
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static void wm_pll_workaround_i210(struct wm_softc *);
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static void wm_legacy_irq_quirk_spt(struct wm_softc *);
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CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc),
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wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
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@ -3659,6 +3661,47 @@ wm_get_cfg_done(struct wm_softc *sc)
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}
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}
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void
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wm_phy_post_reset(struct wm_softc *sc)
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{
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uint32_t reg;
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/* This function is only for ICH8 and newer. */
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if (sc->sc_type < WM_T_ICH8)
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return;
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if (wm_phy_resetisblocked(sc)) {
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/* XXX */
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device_printf(sc->sc_dev, " PHY is blocked\n");
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return;
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}
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/* Allow time for h/w to get to quiescent state after reset */
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delay(10*1000);
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/* Perform any necessary post-reset workarounds */
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if (sc->sc_type == WM_T_PCH)
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wm_hv_phy_workaround_ich8lan(sc);
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if (sc->sc_type == WM_T_PCH2)
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wm_lv_phy_workaround_ich8lan(sc);
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/* Clear the host wakeup bit after lcd reset */
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if (sc->sc_type >= WM_T_PCH) {
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reg = wm_gmii_hv_readreg(sc->sc_dev, 2,
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BM_PORT_GEN_CFG);
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reg &= ~BM_WUC_HOST_WU_BIT;
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wm_gmii_hv_writereg(sc->sc_dev, 2,
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BM_PORT_GEN_CFG, reg);
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}
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/*
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* XXX Configure the LCD with th extended configuration region
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* in NVM
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*/
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/* Configure the LCD with the OEM bits in NVM */
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}
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/* Init hardware bits */
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void
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wm_initialize_hardware_bits(struct wm_softc *sc)
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@ -3938,6 +3981,7 @@ wm_reset_phy(struct wm_softc *sc)
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sc->phy.release(sc);
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wm_get_cfg_done(sc);
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wm_phy_post_reset(sc);
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}
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static void
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@ -4371,6 +4415,9 @@ wm_reset(struct wm_softc *sc)
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break;
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}
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if (phy_reset != 0)
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wm_phy_post_reset(sc);
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if ((sc->sc_type == WM_T_82580)
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|| (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) {
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/* clear global device reset status bit */
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@ -4403,15 +4450,6 @@ wm_reset(struct wm_softc *sc)
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if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211))
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wm_set_eee_i350(sc);
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/* Clear the host wakeup bit after lcd reset */
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if (sc->sc_type >= WM_T_PCH) {
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reg = wm_gmii_hv_readreg(sc->sc_dev, 2,
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BM_PORT_GEN_CFG);
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reg &= ~BM_WUC_HOST_WU_BIT;
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wm_gmii_hv_writereg(sc->sc_dev, 2,
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BM_PORT_GEN_CFG, reg);
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}
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/*
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* For PCH, this write will make sure that any noise will be detected
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* as a CRC error and be dropped rather than show up as a bad packet
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@ -5091,6 +5129,10 @@ wm_init_locked(struct ifnet *ifp)
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ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
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ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
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/* AMT based hardware can now take control from firmware */
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if ((sc->sc_flags & WM_F_HAS_AMT) != 0)
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wm_get_hw_control(sc);
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/* PCH_SPT hardware workaround */
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if (sc->sc_type == WM_T_PCH_SPT)
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wm_flush_desc_rings(sc);
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@ -5098,9 +5140,9 @@ wm_init_locked(struct ifnet *ifp)
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/* Reset the chip to a known state. */
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wm_reset(sc);
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/* AMT based hardware can now take control from firmware */
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if ((sc->sc_flags & WM_F_HAS_AMT) != 0)
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wm_get_hw_control(sc);
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if ((sc->sc_type == WM_T_PCH_SPT) &&
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pci_intr_type(sc->sc_pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_INTX)
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wm_legacy_irq_quirk_spt(sc);
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/* Init hardware bits */
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wm_initialize_hardware_bits(sc);
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@ -8528,7 +8570,7 @@ wm_intr_legacy(void *arg)
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break;
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if (handled == 0) {
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DPRINTF(WM_DEBUG_TX,
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("%s: INTx: got intr\n", device_xname(sc->sc_dev)));
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("%s: INTx: got intr\n",device_xname(sc->sc_dev)));
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}
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if (rndval == 0)
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rndval = icr;
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@ -8934,34 +8976,7 @@ wm_gmii_reset(struct wm_softc *sc)
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case WM_T_PCH2:
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case WM_T_PCH_LPT:
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case WM_T_PCH_SPT:
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/* Allow time for h/w to get to a quiescent state afer reset */
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delay(10*1000);
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if (sc->sc_type == WM_T_PCH)
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wm_hv_phy_workaround_ich8lan(sc);
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if (sc->sc_type == WM_T_PCH2)
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wm_lv_phy_workaround_ich8lan(sc);
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/* Clear the host wakeup bit after lcd reset */
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if (sc->sc_type >= WM_T_PCH) {
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reg = wm_gmii_hv_readreg(sc->sc_dev, 2,
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BM_PORT_GEN_CFG);
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reg &= ~BM_WUC_HOST_WU_BIT;
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wm_gmii_hv_writereg(sc->sc_dev, 2,
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BM_PORT_GEN_CFG, reg);
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}
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/*
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* XXX Configure the LCD with th extended configuration region
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* in NVM
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*/
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/* Disable D0 LPLU. */
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if (sc->sc_type >= WM_T_PCH) /* PCH* */
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wm_lplu_d0_disable_pch(sc);
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else
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wm_lplu_d0_disable(sc); /* ICH* */
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wm_phy_post_reset(sc);
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break;
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default:
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panic("%s: unknown type\n", __func__);
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@ -9422,6 +9437,12 @@ wm_gmii_mediachange(struct ifnet *ifp)
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if ((ifp->if_flags & IFF_UP) == 0)
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return 0;
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/* Disable D0 LPLU. */
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if (sc->sc_type >= WM_T_PCH) /* PCH* */
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wm_lplu_d0_disable_pch(sc);
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else
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wm_lplu_d0_disable(sc); /* ICH* */
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sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
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sc->sc_ctrl |= CTRL_SLU;
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if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
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@ -13764,33 +13785,17 @@ wm_platform_pm_pch_lpt(struct wm_softc *sc, bool link)
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| __SHIFTIN(link, LTRV_SNOOP_REQ) | LTRV_SEND;
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uint32_t rxa;
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uint16_t scale = 0, lat_enc = 0;
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int32_t obff_hwm = 0;
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int64_t lat_ns, value;
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DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
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device_xname(sc->sc_dev), __func__));
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if (link) {
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pcireg_t preg;
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uint16_t max_snoop, max_nosnoop, max_ltr_enc;
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rxa = CSR_READ(sc, WMREG_PBA) & PBA_RXA_MASK;
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/*
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* Determine the maximum latency tolerated by the device.
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*
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* Per the PCIe spec, the tolerated latencies are encoded as
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* a 3-bit encoded scale (only 0-5 are valid) multiplied by
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* a 10-bit value (0-1023) to provide a range from 1 ns to
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* 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
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* 1=2^5ns, 2=2^10ns,...5=2^25ns.
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*/
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lat_ns = ((int64_t)rxa * 1024 -
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(2 * (int64_t)sc->sc_ethercom.ec_if.if_mtu)) * 8 * 1000;
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if (lat_ns < 0)
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lat_ns = 0;
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else {
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uint32_t status;
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uint16_t speed;
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pcireg_t preg;
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status = CSR_READ(sc, WMREG_STATUS);
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switch (__SHIFTOUT(status, STATUS_SPEED)) {
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@ -13804,12 +13809,30 @@ wm_platform_pm_pch_lpt(struct wm_softc *sc, bool link)
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speed = 1000;
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break;
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default:
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printf("%s: Unknown speed (status = %08x)\n",
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device_xname(sc->sc_dev), status);
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device_printf(sc->sc_dev, "Unknown speed "
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"(status = %08x)\n", status);
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return -1;
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}
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/* Rx Packet Buffer Allocation size (KB) */
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rxa = CSR_READ(sc, WMREG_PBA) & PBA_RXA_MASK;
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/*
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* Determine the maximum latency tolerated by the device.
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*
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* Per the PCIe spec, the tolerated latencies are encoded as
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* a 3-bit encoded scale (only 0-5 are valid) multiplied by
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* a 10-bit value (0-1023) to provide a range from 1 ns to
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* 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
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* 1=2^5ns, 2=2^10ns,...5=2^25ns.
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*/
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lat_ns = ((int64_t)rxa * 1024 -
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(2 * ((int64_t)sc->sc_ethercom.ec_if.if_mtu
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+ ETHER_HDR_LEN))) * 8 * 1000;
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if (lat_ns < 0)
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lat_ns = 0;
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else
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lat_ns /= speed;
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}
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value = lat_ns;
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while (value > LTRV_VALUE) {
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@ -13833,12 +13856,39 @@ wm_platform_pm_pch_lpt(struct wm_softc *sc, bool link)
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if (lat_enc > max_ltr_enc) {
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lat_enc = max_ltr_enc;
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lat_ns = __SHIFTOUT(lat_enc, PCI_LTR_MAXSNOOPLAT_VAL)
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* PCI_LTR_SCALETONS(
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__SHIFTOUT(lat_enc,
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PCI_LTR_MAXSNOOPLAT_SCALE));
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}
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if (lat_ns) {
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lat_ns *= speed * 1000;
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lat_ns /= 8;
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lat_ns /= 1000000000;
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obff_hwm = (int32_t)(rxa - lat_ns);
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}
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if ((obff_hwm < 0) || (obff_hwm > SVT_OFF_HWM)) {
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device_printf(sc->sc_dev, "Invalid high water mark %d"
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"(rxa = %d, lat_ns = %d)\n",
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obff_hwm, (int32_t)rxa, (int32_t)lat_ns);
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return -1;
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}
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}
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/* Snoop and No-Snoop latencies the same */
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reg |= lat_enc | __SHIFTIN(lat_enc, LTRV_NONSNOOP);
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CSR_WRITE(sc, WMREG_LTRV, reg);
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/* Set OBFF high water mark */
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reg = CSR_READ(sc, WMREG_SVT) & ~SVT_OFF_HWM;
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reg |= obff_hwm;
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CSR_WRITE(sc, WMREG_SVT, reg);
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/* Enable OBFF */
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reg = CSR_READ(sc, WMREG_SVCR);
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reg |= SVCR_OFF_EN | SVCR_OFF_MASKINT;
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CSR_WRITE(sc, WMREG_SVCR, reg);
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return 0;
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}
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@ -13916,3 +13966,21 @@ wm_pll_workaround_i210(struct wm_softc *sc)
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if (wa_done)
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aprint_verbose_dev(sc->sc_dev, "I210 workaround done\n");
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}
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static void
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wm_legacy_irq_quirk_spt(struct wm_softc *sc)
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{
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uint32_t reg;
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DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
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device_xname(sc->sc_dev), __func__));
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KASSERT(sc->sc_type == WM_T_PCH_SPT);
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reg = CSR_READ(sc, WMREG_FEXTNVM7);
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reg |= FEXTNVM7_SIDE_CLK_UNGATE;
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CSR_WRITE(sc, WMREG_FEXTNVM7, reg);
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reg = CSR_READ(sc, WMREG_FEXTNVM9);
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reg |= FEXTNVM9_IOSFSB_CLKGATE_DIS | FEXTNVM9_IOSFSB_CLKREQ_DIS;
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CSR_WRITE(sc, WMREG_FEXTNVM9, reg);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: if_wmreg.h,v 1.99 2017/06/26 04:09:02 msaitoh Exp $ */
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/* $NetBSD: if_wmreg.h,v 1.100 2017/06/26 04:22:46 msaitoh Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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@ -728,6 +728,13 @@ struct livengood_tcpip_ctxdesc {
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#define IVAR_MISC_TCPTIMER __BITS(0, 7)
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#define IVAR_MISC_OTHER __BITS(8, 15)
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#define WMREG_SVCR 0x00f0
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#define SVCR_OFF_EN __BIT(0)
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#define SVCR_OFF_MASKINT __BIT(12)
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#define WMREG_SVT 0x00f4
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#define SVT_OFF_HWM __BITS(4, 0)
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#define WMREG_LTRV 0x00f8 /* Latency Tolerance Reporting */
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#define LTRV_VALUE __BITS(9, 0)
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#define LTRV_SCALE __BITS(12, 10)
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@ -1302,6 +1309,8 @@ struct livengood_tcpip_ctxdesc {
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#define WMREG_GCR2 0x5b64 /* 3GPIO Control Register 2 */
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#define WMREG_FEXTNVM9 0x5bb4 /* Future Extended NVM 9 */
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#define FEXTNVM9_IOSFSB_CLKGATE_DIS __BIT(11)
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#define FEXTNVM9_IOSFSB_CLKREQ_DIS __BIT(12)
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#define WMREG_FEXTNVM11 0x5bbc /* Future Extended NVM 11 */
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#define FEXTNVM11_DIS_MULRFIX __BIT(13) /* Disable MULR fix */
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