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This commit is contained in:
msaitoh 2019-07-18 08:51:49 +00:00
parent 47cd7b2277
commit 13977e7ff9
2 changed files with 10372 additions and 10365 deletions
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8
sys/dev/pci/pcidevs.h
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@ -1,10 +1,10 @@
/* $NetBSD: pcidevs.h,v 1.1368 2019/07/12 02:39:37 msaitoh Exp $ */
/* $NetBSD: pcidevs.h,v 1.1369 2019/07/18 08:51:49 msaitoh Exp $ */
/*
* THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* NetBSD: pcidevs,v 1.1380 2019/07/12 02:38:35 msaitoh Exp
* NetBSD: pcidevs,v 1.1381 2019/07/18 08:50:50 msaitoh Exp
*/
/*
@ -1029,6 +1029,8 @@
#define PCI_PRODUCT_AMD_F17_DF_8 0x1467 /* Family17h Data Fabric */
#define PCI_PRODUCT_AMD_F17_PCIE_4 0x1470 /* Family17h PCIE */
#define PCI_PRODUCT_AMD_F17_PCIE_5 0x1471 /* Family17h PCIE */
#define PCI_PRODUCT_AMD_F17_7X_RC 0x1480 /* Family17h/7xh Root Complex */
#define PCI_PRODUCT_AMD_F17_7X_IOMMU 0x1481 /* Family17h/7xh IOMMU */
#define PCI_PRODUCT_AMD_F14_RC 0x1510 /* Family14h Root Complex */
#define PCI_PRODUCT_AMD_F16_HT 0x1530 /* Family16h HyperTransport Configuration */
#define PCI_PRODUCT_AMD_F16_ADDR 0x1531 /* Family16h Address Map Configuration */
@ -4611,7 +4613,7 @@
#define PCI_PRODUCT_INTEL_C620_VSWP_1 0x37c3 /* C620 Virtual Switch Port (for QAT 1) */
#define PCI_PRODUCT_INTEL_C620_VSWP_2 0x37c4 /* C620 Virtual Switch Port (for QAT 2) */
#define PCI_PRODUCT_INTEL_C620_VSWP_3 0x37c5 /* C620 Virtual Switch Port (for 10GbE LAN) */
#define PCI_PRODUCT_INTEL_C620_VSWP_4 0x37c6 /* C620 Virtual Switch Port (for Termal Sensor) */
#define PCI_PRODUCT_INTEL_C620_VSWP_5 0x37c7 /* C620 Virtual Switch Port (for Termal Sensor) */
#define PCI_PRODUCT_INTEL_C620_QAT 0x37c8 /* C620 QAT */
#define PCI_PRODUCT_INTEL_C620_QAT_VF 0x37c9 /* C620 QAT Virtual Function */
#define PCI_PRODUCT_INTEL_X722 0x37cc /* X722 10GbE */

20729
sys/dev/pci/pcidevs_data.h
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