Add GPIO driver, and GPIO access functions for other subsystems.
This commit is contained in:
gdamore
parent
cbb0e8c88b
commit
1388c544a6
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@ -1,4 +1,4 @@
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# $NetBSD: DBAU1550,v 1.3 2006/02/09 00:26:39 gdamore Exp $
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# $NetBSD: DBAU1550,v 1.4 2006/02/12 20:49:34 gdamore Exp $
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#
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# Kernel config for the AMD Alchemy DBAu1550 evaluation board.
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@ -19,6 +19,9 @@ options PCI_NETBSD_CONFIGURE
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aupci* at aubus? addr ?
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pci* at aupci?
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augpio* at aubus? addr ?
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gpio* at augpio?
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# Note that this is just fairly random selection of PCI devices.
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# Only the hptide controller is actually on-board.
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@ -1,4 +1,4 @@
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/* $NetBSD: au1550.c,v 1.2 2006/02/09 00:26:40 gdamore Exp $ */
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/* $NetBSD: au1550.c,v 1.3 2006/02/12 20:49:34 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Itronix Inc.
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@ -97,7 +97,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: au1550.c,v 1.2 2006/02/09 00:26:40 gdamore Exp $");
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__KERNEL_RCSID(0, "$NetBSD: au1550.c,v 1.3 2006/02/12 20:49:34 gdamore Exp $");
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#include <sys/param.h>
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#include <machine/bus.h>
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@ -182,14 +182,14 @@ static struct au_dev au1550_devices[] = {
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{ "ohci", { AU1550_USBH_BASE, AU1550_USBH_ENABLE,
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AU1550_USBH_SIZE }, { 26, -1 }},
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{ "aupci", { PCI_BASE }, { -1, -1 }},
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{ "augpio", { SYS_BASE, 27 }, { -1, -1 }},
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{ "augpio", { GPIO2_BASE, 16 }, { -1, -1 }},
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#if 0
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{ "usbd", { USBD_BASE }, { 24, 25 }},
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{ "aupsc", { PSC0_BASE }, { 10, -1 }},
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{ "aupsc", { PSC1_BASE }, { 11, -1 }},
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{ "aupsc", { PSC2_BASE }, { 12, -1 }},
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{ "aupsc", { PSC3_BASE }, { 13, -1 }},
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{ "gpio", { SYS_BASE }, { -1, -1 }},
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{ "gpio", { GPIO2_BASE }, { -1, -1 }},
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{ "aucrypto", { CRYPTO_BASE }, { 4, -1 }},
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#endif
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{ NULL }
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@ -0,0 +1,294 @@
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/* $NetBSD: augpio.c,v 1.1 2006/02/12 20:49:34 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Itronix Inc.
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* All rights reserved.
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*
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* Written by Garrett D'Amore for Itronix Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Itronix Inc. may not be used to endorse
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* or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: augpio.c,v 1.1 2006/02/12 20:49:34 gdamore Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <sys/gpio.h>
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#include <sys/kernel.h>
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#include <dev/gpio/gpiovar.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <mips/alchemy/include/aubusvar.h>
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#include <mips/alchemy/include/aureg.h>
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#include <mips/alchemy/dev/augpioreg.h>
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#include <mips/alchemy/dev/augpiovar.h>
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struct augpio_softc {
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struct device sc_dev;
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struct gpio_chipset_tag sc_gc;
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gpio_pin_t sc_pins[AUGPIO_NPINS];
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int sc_npins;
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int sc_isgpio2;
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};
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static int augpio_pin_read(void *, int);
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static void augpio_pin_write(void *, int, int);
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static void augpio_pin_ctl(void *, int, int);
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static int augpio_match(struct device *, struct cfdata *, void *);
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static void augpio_attach(struct device *, struct device *, void *);
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CFATTACH_DECL(augpio, sizeof(struct augpio_softc),
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augpio_match, augpio_attach, NULL, NULL);
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#define GETREG(x) \
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(*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(x))
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#define PUTREG(x, v) \
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((*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))
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static int augpio_found = 0;
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int
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augpio_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct aubus_attach_args *aa = (struct aubus_attach_args *)aux;
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if (strcmp(aa->aa_name, "augpio") != 0)
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return 0;
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if (augpio_found)
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return 0;
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return 1;
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}
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void
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augpio_attach(struct device *parent, struct device *self, void *aux)
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{
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int pin;
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struct augpio_softc *sc = (struct augpio_softc *)self;
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struct aubus_attach_args *aa = aux;
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struct gpiobus_attach_args gba;
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sc->sc_npins = 0;
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printf(": Alchemy GPIO");
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if (aa->aa_addrs[0] == SYS_BASE) {
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for (pin = 0; pin < aa->aa_addrs[1]; pin++) {
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sc->sc_pins[sc->sc_npins].pin_num = pin;
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sc->sc_pins[sc->sc_npins].pin_caps =
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GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
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GPIO_PIN_TRISTATE;
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sc->sc_pins[sc->sc_npins].pin_flags =
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au_gpio_ctl(pin, 0);
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sc->sc_pins[sc->sc_npins].pin_state =
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au_gpio_read(pin);
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sc->sc_npins++;
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}
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sc->sc_isgpio2 = 0;
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printf(", primary block");
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} else if (aa->aa_addrs[0] == GPIO2_BASE) {
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/* initialize GPIO2 block */
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uint32_t val;
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val = AUGPIO_GPIO2_ENABLE_MR | AUGPIO_GPIO2_ENABLE_CE;
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PUTREG(GPIO2_BASE + AUGPIO_GPIO2_ENABLE, val);
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delay(10);
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val &= ~AUGPIO_GPIO2_ENABLE_MR;
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PUTREG(GPIO2_BASE + AUGPIO_GPIO2_ENABLE, val);
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for (pin = 0; pin < aa->aa_addrs[1]; pin++) {
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sc->sc_pins[sc->sc_npins].pin_num = pin;
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sc->sc_pins[sc->sc_npins].pin_caps =
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GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
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sc->sc_pins[sc->sc_npins].pin_flags =
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au_gpio2_ctl(pin, 0);
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sc->sc_pins[sc->sc_npins].pin_state =
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au_gpio2_read(pin);
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sc->sc_npins++;
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}
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printf(", secondary block");
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sc->sc_isgpio2 = 1;
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} else {
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printf(", unidentified block");
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}
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printf("\n");
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sc->sc_gc.gp_cookie = sc;
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sc->sc_gc.gp_pin_read = augpio_pin_read;
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sc->sc_gc.gp_pin_write = augpio_pin_write;
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sc->sc_gc.gp_pin_ctl = augpio_pin_ctl;
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gba.gba_gc = &sc->sc_gc;
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gba.gba_pins = sc->sc_pins;
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gba.gba_npins = sc->sc_npins;
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config_found_ia(&sc->sc_dev, "gpiobus", &gba, gpiobus_print);
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}
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int
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augpio_pin_read(void *arg, int pin)
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{
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struct augpio_softc *sc = arg;
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return (sc->sc_isgpio2 ? au_gpio2_read(pin) : au_gpio_read(pin));
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}
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void
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augpio_pin_write(void *arg, int pin, int value)
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{
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struct augpio_softc *sc = arg;
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if (sc->sc_isgpio2)
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au_gpio2_write(pin, value);
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else
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au_gpio_write(pin, value);
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}
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void
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augpio_pin_ctl(void *arg, int pin, int flags)
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{
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struct augpio_softc *sc = arg;
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if (sc->sc_isgpio2)
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(void) au_gpio2_ctl(pin, flags);
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else
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(void) au_gpio_ctl(pin, flags);
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}
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int
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au_gpio_read(int pin)
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{
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pin = 1 << pin;
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return ((GETREG(SYS_BASE + AUGPIO_SYS_PINSTATERD) & pin) ?
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GPIO_PIN_HIGH : GPIO_PIN_LOW);
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}
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void
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au_gpio_write(int pin, int value)
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{
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pin = 1 << pin;
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if (value) {
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PUTREG(SYS_BASE + AUGPIO_SYS_OUTPUTSET, pin);
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} else {
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PUTREG(SYS_BASE + AUGPIO_SYS_OUTPUTCLR, pin);
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}
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}
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int
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au_gpio_ctl(int pin, int flags)
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{
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uint32_t tri, out;
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int old;
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old = 0;
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pin = 1 << pin;
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tri = GETREG(SYS_BASE + AUGPIO_SYS_TRIOUTRD);
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out = GETREG(SYS_BASE + AUGPIO_SYS_OUTPUTRD);
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old = 0;
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if (tri & pin) {
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old |= GPIO_PIN_INPUT;
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} else {
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old |= GPIO_PIN_OUTPUT;
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}
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if (flags & (GPIO_PIN_TRISTATE|GPIO_PIN_INPUT)) {
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PUTREG(SYS_BASE + AUGPIO_SYS_TRIOUTCLR, pin);
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} else if (flags & GPIO_PIN_OUTPUT) {
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if (pin & out) {
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PUTREG(SYS_BASE + AUGPIO_SYS_OUTPUTSET, pin);
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} else {
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PUTREG(SYS_BASE + AUGPIO_SYS_OUTPUTCLR, pin);
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}
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}
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return old;
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}
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int
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au_gpio2_read(int pin)
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{
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pin = 1 << pin;
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return ((GETREG(GPIO2_BASE + AUGPIO_GPIO2_PINSTATE) & pin) ?
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GPIO_PIN_HIGH : GPIO_PIN_LOW);
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}
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void
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au_gpio2_write(int pin, int value)
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{
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pin = 1 << pin;
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if (value) {
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PUTREG(GPIO2_BASE + AUGPIO_GPIO2_OUTPUT, (pin | (pin << 16)));
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} else {
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PUTREG(GPIO2_BASE + AUGPIO_GPIO2_OUTPUT, (pin << 16));
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}
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}
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int
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au_gpio2_ctl(int pin, int flags)
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{
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uint32_t dir;
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int old;
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pin = 1 << pin;
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dir = GETREG(GPIO2_BASE + AUGPIO_GPIO2_DIR);
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old = dir;
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if (dir & pin) {
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old |= GPIO_PIN_OUTPUT;
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} else {
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old |= GPIO_PIN_INPUT;
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}
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if (flags & GPIO_PIN_INPUT) {
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dir |= pin;
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PUTREG(GPIO2_BASE + AUGPIO_GPIO2_DIR, pin);
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} else if (flags & GPIO_PIN_OUTPUT) {
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dir &= ~pin;
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PUTREG(GPIO2_BASE + AUGPIO_GPIO2_DIR, pin);
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}
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return old;
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}
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@ -0,0 +1,58 @@
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/* $NetBSD: augpioreg.h,v 1.1 2006/02/12 20:49:34 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Itronix Inc.
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* All rights reserved.
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*
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* Written by Garrett D'Amore for Itronix Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of Itronix Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific
|
||||
* prior written permission.
|
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*
|
||||
* THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
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*/
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#ifndef _MIPS_ALCHEMY_DEV_AUGPIOREG_H
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#define _MIPS_ALCHEMY_DEV_AUGPIOREG_H
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#define AUGPIO_NPINS 64
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/* SYS_GPIO registers -- offset from SYS_BASE */
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#define AUGPIO_SYS_TRIOUTRD 0x100
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#define AUGPIO_SYS_TRIOUTCLR 0x100
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#define AUGPIO_SYS_OUTPUTRD 0x108
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#define AUGPIO_SYS_OUTPUTSET 0x108
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#define AUGPIO_SYS_OUTPUTCLR 0x10C
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#define AUGPIO_SYS_PINSTATERD 0x110
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#define AUGPIO_SYS_PININPUTEN 0x110
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/* GPIO2 registers -- offset from GPIO2_BASE */
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#define AUGPIO_GPIO2_DIR 0x00
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#define AUGPIO_GPIO2_OUTPUT 0x08
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#define AUGPIO_GPIO2_PINSTATE 0x0C
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#define AUGPIO_GPIO2_INTEN 0x10
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#define AUGPIO_GPIO2_ENABLE 0x14
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#define AUGPIO_GPIO2_ENABLE_CE 0x1
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#define AUGPIO_GPIO2_ENABLE_MR 0x2
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#endif /* _MIPS_ALCHEMY_DEV_AUPCIREG_H */
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@ -0,0 +1,52 @@
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/* $NetBSD: augpiovar.h,v 1.1 2006/02/12 20:49:34 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Itronix Inc.
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* All rights reserved.
|
||||
*
|
||||
* Written by Garrett D'Amore for Itronix Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of Itronix Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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#ifndef _MIPS_ALCHEMY_DEV_AUGPIOVAR_H
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#define _MIPS_ALCHEMY_DEV_AUGPIOVAR_H
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#include <sys/gpio.h>
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/*
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* We export these interfaces so that other subsystems can access GPIOs
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* without going thru the GPIO device driver.
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*/
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int au_gpio_read(int);
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void au_gpio_write(int, int);
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int au_gpio_ctl(int, int);
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|
||||
int au_gpio2_read(int);
|
||||
void au_gpio2_write(int, int);
|
||||
int au_gpio2_ctl(int, int);
|
||||
|
||||
#endif /* _MIPS_ALCHEMY_DEV_AUPCIVAR_H */
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
# $NetBSD: files.alchemy,v 1.6 2006/02/09 00:26:40 gdamore Exp $
|
||||
# $NetBSD: files.alchemy,v 1.7 2006/02/12 20:49:34 gdamore Exp $
|
||||
|
||||
defflag opt_alchemy.h ALCHEMY_AU1000
|
||||
ALCHEMY_AU1100
|
||||
|
|
@ -52,3 +52,8 @@ file arch/mips/alchemy/dev/auaudio.c auaudio
|
|||
device aupci: pcibus
|
||||
attach aupci at aubus
|
||||
file arch/mips/alchemy/dev/aupci.c aupci
|
||||
|
||||
# On-chip GPIO
|
||||
device augpio: gpiobus
|
||||
attach augpio at aubus
|
||||
file arch/mips/alchemy/dev/augpio.c augpio
|
||||
|
|
|
|||
Loading…
Reference in New Issue