cardbusvar.h is divided into two files: cardbusvar.h and cardbusreg.h.
This commit is contained in:
haya
parent
88f3192778
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1331bcc296
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/* $NetBSD: cardbusreg.h,v 1.1 2001/06/01 10:30:37 haya Exp $ */
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/*
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* Copyright (c) 2001
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* HAYAKAWA Koichi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_CARDBUS_CARDBUSREG_H_
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#define _DEV_CARDBUS_CARDBUSREG_H_
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#include <dev/pci/pcivar.h> /* for pcitag_t */
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typedef u_int32_t cardbusreg_t;
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typedef pcitag_t cardbustag_t;
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typedef int cardbus_intr_line_t;
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#define CARDBUS_ID_REG 0x00
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typedef u_int16_t cardbus_vendor_id_t;
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typedef u_int16_t cardbus_product_id_t;
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# define CARDBUS_VENDOR_SHIFT 0
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# define CARDBUS_VENDOR_MASK 0xffff
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# define CARDBUS_VENDOR(id) \
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(((id) >> CARDBUS_VENDOR_SHIFT) & CARDBUS_VENDOR_MASK)
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# define CARDBUS_PRODUCT_SHIFT 16
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# define CARDBUS_PRODUCT_MASK 0xffff
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# define CARDBUS_PRODUCT(id) \
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(((id) >> CARDBUS_PRODUCT_SHIFT) & CARDBUS_PRODUCT_MASK)
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#define CARDBUS_COMMAND_STATUS_REG 0x04
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# define CARDBUS_COMMAND_IO_ENABLE 0x00000001
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# define CARDBUS_COMMAND_MEM_ENABLE 0x00000002
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# define CARDBUS_COMMAND_MASTER_ENABLE 0x00000004
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# define CARDBUS_COMMAND_SPECIAL_ENABLE 0x00000008
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# define CARDBUS_COMMAND_INVALIDATE_ENABLE 0x00000010
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# define CARDBUS_COMMAND_PALETTE_ENABLE 0x00000020
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# define CARDBUS_COMMAND_PARITY_ENABLE 0x00000040
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# define CARDBUS_COMMAND_STEPPING_ENABLE 0x00000080
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# define CARDBUS_COMMAND_SERR_ENABLE 0x00000100
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# define CARDBUS_COMMAND_BACKTOBACK_ENABLE 0x00000200
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#define CARDBUS_CLASS_REG 0x08
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#define CARDBUS_CLASS_SHIFT 24
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#define CARDBUS_CLASS_MASK 0xff
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#define CARDBUS_CLASS(cr) \
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(((cr) >> CARDBUS_CLASS_SHIFT) & CARDBUS_CLASS_MASK)
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#define CARDBUS_SUBCLASS_SHIFT 16
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#define CARDBUS_SUBCLASS_MASK 0xff
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#define CARDBUS_SUBCLASS(cr) \
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(((cr) >> CARDBUS_SUBCLASS_SHIFT) & CARDBUS_SUBCLASS_MASK)
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#define CARDBUS_INTERFACE_SHIFT 8
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#define CARDBUS_INTERFACE_MASK 0xff
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#define CARDBUS_INTERFACE(cr) \
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(((cr) >> CARDBUS_INTERFACE_SHIFT) & CARDBUS_INTERFACE_MASK)
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#define CARDBUS_REVISION_SHIFT 0
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#define CARDBUS_REVISION_MASK 0xff
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#define CARDBUS_REVISION(cr) \
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(((cr) >> CARDBUS_REVISION_SHIFT) & CARDBUS_REVISION_MASK)
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/* base classes */
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#define CARDBUS_CLASS_PREHISTORIC 0x00
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#define CARDBUS_CLASS_MASS_STORAGE 0x01
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#define CARDBUS_CLASS_NETWORK 0x02
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#define CARDBUS_CLASS_DISPLAY 0x03
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#define CARDBUS_CLASS_MULTIMEDIA 0x04
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#define CARDBUS_CLASS_MEMORY 0x05
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#define CARDBUS_CLASS_BRIDGE 0x06
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#define CARDBUS_CLASS_COMMUNICATIONS 0x07
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#define CARDBUS_CLASS_SYSTEM 0x08
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#define CARDBUS_CLASS_INPUT 0x09
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#define CARDBUS_CLASS_DOCK 0x0a
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#define CARDBUS_CLASS_PROCESSOR 0x0b
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#define CARDBUS_CLASS_SERIALBUS 0x0c
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#define CARDBUS_CLASS_UNDEFINED 0xff
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/* 0x07 serial bus subclasses */
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#define CARDBUS_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
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/* 0x0c serial bus subclasses */
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#define CARDBUS_SUBCLASS_SERIALBUS_FIREWIRE 0x00
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#define CARDBUS_SUBCLASS_SERIALBUS_ACCESS 0x01
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#define CARDBUS_SUBCLASS_SERIALBUS_SSA 0x02
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#define CARDBUS_SUBCLASS_SERIALBUS_USB 0x03
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#define CARDBUS_SUBCLASS_SERIALBUS_FIBER 0x04
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/* BIST, Header Type, Latency Timer, Cache Line Size */
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#define CARDBUS_BHLC_REG 0x0c
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#define CARDBUS_BIST_SHIFT 24
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#define CARDBUS_BIST_MASK 0xff
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#define CARDBUS_BIST(bhlcr) \
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(((bhlcr) >> CARDBUS_BIST_SHIFT) & CARDBUS_BIST_MASK)
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#define CARDBUS_HDRTYPE_SHIFT 16
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#define CARDBUS_HDRTYPE_MASK 0xff
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#define CARDBUS_HDRTYPE(bhlcr) \
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(((bhlcr) >> CARDBUS_HDRTYPE_SHIFT) & CARDBUS_HDRTYPE_MASK)
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#define CARDBUS_HDRTYPE_TYPE(bhlcr) \
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(CARDBUS_HDRTYPE(bhlcr) & 0x7f)
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#define CARDBUS_HDRTYPE_MULTIFN(bhlcr) \
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((CARDBUS_HDRTYPE(bhlcr) & 0x80) != 0)
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#define CARDBUS_LATTIMER_SHIFT 8
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#define CARDBUS_LATTIMER_MASK 0xff
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#define CARDBUS_LATTIMER(bhlcr) \
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(((bhlcr) >> CARDBUS_LATTIMER_SHIFT) & CARDBUS_LATTIMER_MASK)
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#define CARDBUS_CACHELINE_SHIFT 0
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#define CARDBUS_CACHELINE_MASK 0xff
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#define CARDBUS_CACHELINE(bhlcr) \
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(((bhlcr) >> CARDBUS_CACHELINE_SHIFT) & CARDBUS_CACHELINE_MASK)
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/* Base Resisters */
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#define CARDBUS_BASE0_REG 0x10
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#define CARDBUS_BASE1_REG 0x14
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#define CARDBUS_BASE2_REG 0x18
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#define CARDBUS_BASE3_REG 0x1C
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#define CARDBUS_BASE4_REG 0x20
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#define CARDBUS_BASE5_REG 0x24
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#define CARDBUS_CIS_REG 0x28
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#define CARDBUS_ROM_REG 0x30
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# define CARDBUS_CIS_ASIMASK 0x07
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# define CARDBUS_CIS_ASI(x) (CARDBUS_CIS_ASIMASK & (x))
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# define CARDBUS_CIS_ASI_TUPLE 0x00
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# define CARDBUS_CIS_ASI_BAR0 0x01
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# define CARDBUS_CIS_ASI_BAR1 0x02
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# define CARDBUS_CIS_ASI_BAR2 0x03
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# define CARDBUS_CIS_ASI_BAR3 0x04
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# define CARDBUS_CIS_ASI_BAR4 0x05
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# define CARDBUS_CIS_ASI_BAR5 0x06
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# define CARDBUS_CIS_ASI_ROM 0x07
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# define CARDBUS_CIS_ADDRMASK 0x0ffffff8
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# define CARDBUS_CIS_ADDR(x) (CARDBUS_CIS_ADDRMASK & (x))
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# define CARDBUS_CIS_ASI_BAR(x) (((CARDBUS_CIS_ASIMASK & (x))-1)*4+0x10)
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# define CARDBUS_CIS_ASI_ROM_IMAGE(x) (((x) >> 28) & 0xf)
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#define CARDBUS_INTERRUPT_REG 0x3c
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#define CARDBUS_MAPREG_TYPE_MEM 0x00000000
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#define CARDBUS_MAPREG_TYPE_IO 0x00000001
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#endif /* !_DEV_CARDBUS_CARDBUSREG_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: cardbusvar.h,v 1.21 2001/05/31 08:33:40 haya Exp $ */
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/* $NetBSD: cardbusvar.h,v 1.22 2001/06/01 10:30:37 haya Exp $ */
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/*
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* Copyright (c) 1998, 1999 and 2000
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@ -35,8 +35,7 @@
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#ifndef _DEV_CARDBUS_CARDBUSVAR_H_
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#define _DEV_CARDBUS_CARDBUSVAR_H_
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#include <dev/pci/pcivar.h> /* for pcitag_t */
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#include <dev/cardbus/cardbusreg.h>
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#if 1
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#include <dev/cardbus/rbus.h>
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#endif
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@ -47,149 +46,6 @@ typedef void *cardbus_chipset_tag_t;
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typedef int cardbus_intr_handle_t;
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/* XXX they must be in cardbusreg.h */
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typedef u_int32_t cardbusreg_t;
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typedef pcitag_t cardbustag_t;
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typedef int cardbus_intr_line_t;
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#define CARDBUS_ID_REG 0x00
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typedef u_int16_t cardbus_vendor_id_t;
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typedef u_int16_t cardbus_product_id_t;
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# define CARDBUS_VENDOR_SHIFT 0
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# define CARDBUS_VENDOR_MASK 0xffff
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# define CARDBUS_VENDOR(id) \
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(((id) >> CARDBUS_VENDOR_SHIFT) & CARDBUS_VENDOR_MASK)
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# define CARDBUS_PRODUCT_SHIFT 16
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# define CARDBUS_PRODUCT_MASK 0xffff
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# define CARDBUS_PRODUCT(id) \
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(((id) >> CARDBUS_PRODUCT_SHIFT) & CARDBUS_PRODUCT_MASK)
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#define CARDBUS_COMMAND_STATUS_REG 0x04
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# define CARDBUS_COMMAND_IO_ENABLE 0x00000001
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# define CARDBUS_COMMAND_MEM_ENABLE 0x00000002
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# define CARDBUS_COMMAND_MASTER_ENABLE 0x00000004
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# define CARDBUS_COMMAND_SPECIAL_ENABLE 0x00000008
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# define CARDBUS_COMMAND_INVALIDATE_ENABLE 0x00000010
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# define CARDBUS_COMMAND_PALETTE_ENABLE 0x00000020
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# define CARDBUS_COMMAND_PARITY_ENABLE 0x00000040
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# define CARDBUS_COMMAND_STEPPING_ENABLE 0x00000080
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# define CARDBUS_COMMAND_SERR_ENABLE 0x00000100
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# define CARDBUS_COMMAND_BACKTOBACK_ENABLE 0x00000200
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#define CARDBUS_CLASS_REG 0x08
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#define CARDBUS_CLASS_SHIFT 24
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#define CARDBUS_CLASS_MASK 0xff
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#define CARDBUS_CLASS(cr) \
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(((cr) >> CARDBUS_CLASS_SHIFT) & CARDBUS_CLASS_MASK)
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#define CARDBUS_SUBCLASS_SHIFT 16
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#define CARDBUS_SUBCLASS_MASK 0xff
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#define CARDBUS_SUBCLASS(cr) \
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(((cr) >> CARDBUS_SUBCLASS_SHIFT) & CARDBUS_SUBCLASS_MASK)
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#define CARDBUS_INTERFACE_SHIFT 8
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#define CARDBUS_INTERFACE_MASK 0xff
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#define CARDBUS_INTERFACE(cr) \
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(((cr) >> CARDBUS_INTERFACE_SHIFT) & CARDBUS_INTERFACE_MASK)
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#define CARDBUS_REVISION_SHIFT 0
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#define CARDBUS_REVISION_MASK 0xff
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#define CARDBUS_REVISION(cr) \
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(((cr) >> CARDBUS_REVISION_SHIFT) & CARDBUS_REVISION_MASK)
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/* base classes */
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#define CARDBUS_CLASS_PREHISTORIC 0x00
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#define CARDBUS_CLASS_MASS_STORAGE 0x01
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#define CARDBUS_CLASS_NETWORK 0x02
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#define CARDBUS_CLASS_DISPLAY 0x03
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#define CARDBUS_CLASS_MULTIMEDIA 0x04
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#define CARDBUS_CLASS_MEMORY 0x05
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#define CARDBUS_CLASS_BRIDGE 0x06
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#define CARDBUS_CLASS_COMMUNICATIONS 0x07
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#define CARDBUS_CLASS_SYSTEM 0x08
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#define CARDBUS_CLASS_INPUT 0x09
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#define CARDBUS_CLASS_DOCK 0x0a
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#define CARDBUS_CLASS_PROCESSOR 0x0b
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#define CARDBUS_CLASS_SERIALBUS 0x0c
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#define CARDBUS_CLASS_UNDEFINED 0xff
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/* 0x07 serial bus subclasses */
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#define CARDBUS_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
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/* 0x0c serial bus subclasses */
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#define CARDBUS_SUBCLASS_SERIALBUS_FIREWIRE 0x00
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#define CARDBUS_SUBCLASS_SERIALBUS_ACCESS 0x01
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#define CARDBUS_SUBCLASS_SERIALBUS_SSA 0x02
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#define CARDBUS_SUBCLASS_SERIALBUS_USB 0x03
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#define CARDBUS_SUBCLASS_SERIALBUS_FIBER 0x04
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/* BIST, Header Type, Latency Timer, Cache Line Size */
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#define CARDBUS_BHLC_REG 0x0c
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#define CARDBUS_BIST_SHIFT 24
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#define CARDBUS_BIST_MASK 0xff
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#define CARDBUS_BIST(bhlcr) \
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(((bhlcr) >> CARDBUS_BIST_SHIFT) & CARDBUS_BIST_MASK)
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#define CARDBUS_HDRTYPE_SHIFT 16
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#define CARDBUS_HDRTYPE_MASK 0xff
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#define CARDBUS_HDRTYPE(bhlcr) \
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(((bhlcr) >> CARDBUS_HDRTYPE_SHIFT) & CARDBUS_HDRTYPE_MASK)
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#define CARDBUS_HDRTYPE_TYPE(bhlcr) \
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(CARDBUS_HDRTYPE(bhlcr) & 0x7f)
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#define CARDBUS_HDRTYPE_MULTIFN(bhlcr) \
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((CARDBUS_HDRTYPE(bhlcr) & 0x80) != 0)
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#define CARDBUS_LATTIMER_SHIFT 8
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#define CARDBUS_LATTIMER_MASK 0xff
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#define CARDBUS_LATTIMER(bhlcr) \
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(((bhlcr) >> CARDBUS_LATTIMER_SHIFT) & CARDBUS_LATTIMER_MASK)
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#define CARDBUS_CACHELINE_SHIFT 0
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#define CARDBUS_CACHELINE_MASK 0xff
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#define CARDBUS_CACHELINE(bhlcr) \
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(((bhlcr) >> CARDBUS_CACHELINE_SHIFT) & CARDBUS_CACHELINE_MASK)
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/* Base Resisters */
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#define CARDBUS_BASE0_REG 0x10
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#define CARDBUS_BASE1_REG 0x14
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#define CARDBUS_BASE2_REG 0x18
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#define CARDBUS_BASE3_REG 0x1C
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#define CARDBUS_BASE4_REG 0x20
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#define CARDBUS_BASE5_REG 0x24
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#define CARDBUS_CIS_REG 0x28
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#define CARDBUS_ROM_REG 0x30
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# define CARDBUS_CIS_ASIMASK 0x07
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# define CARDBUS_CIS_ASI(x) (CARDBUS_CIS_ASIMASK & (x))
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# define CARDBUS_CIS_ASI_TUPLE 0x00
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# define CARDBUS_CIS_ASI_BAR0 0x01
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# define CARDBUS_CIS_ASI_BAR1 0x02
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# define CARDBUS_CIS_ASI_BAR2 0x03
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# define CARDBUS_CIS_ASI_BAR3 0x04
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# define CARDBUS_CIS_ASI_BAR4 0x05
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# define CARDBUS_CIS_ASI_BAR5 0x06
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# define CARDBUS_CIS_ASI_ROM 0x07
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# define CARDBUS_CIS_ADDRMASK 0x0ffffff8
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# define CARDBUS_CIS_ADDR(x) (CARDBUS_CIS_ADDRMASK & (x))
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# define CARDBUS_CIS_ASI_BAR(x) (((CARDBUS_CIS_ASIMASK & (x))-1)*4+0x10)
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# define CARDBUS_CIS_ASI_ROM_IMAGE(x) (((x) >> 28) & 0xf)
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#define CARDBUS_INTERRUPT_REG 0x3c
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#define CARDBUS_MAPREG_TYPE_MEM 0x00000000
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#define CARDBUS_MAPREG_TYPE_IO 0x00000001
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/* XXX end */
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#if rbus
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/*
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* struct cardbus_functions contains the pointers for basic cardbus
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