Add a whole slew of registers found in the PCnet-PCI family.
This commit is contained in:
thorpej
parent
6fa8665eeb
commit
132107ce3b
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@ -1,11 +1,11 @@
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/* $NetBSD: lancereg.h,v 1.2 1998/08/15 10:18:14 mycroft Exp $ */
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/* $NetBSD: lancereg.h,v 1.3 2000/02/17 20:18:29 thorpej Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum.
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* by Charles M. Hannum and Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -74,6 +74,56 @@
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* @(#)if_lereg.h 8.1 (Berkeley) 6/10/93
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*/
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/*
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* Register description for the following Advanced Micro Devices
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* Ethernet chips:
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*
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* - Am7990 Local Area Network Controller for Ethernet (LANCE)
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* (and its descendent Am79c90 C-LANCE).
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*
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* - Am79c900 Integrated Local Area Communications Controller (ILACC)
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*
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* - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
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*
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* - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
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* for ISA
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*
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* - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
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* Ethernet Controller for ISA
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*
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* - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
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* (for VESA and 486 local busses)
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*
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* - Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI
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* Local Bus
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*
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* - Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller
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* for PCI Local Bus
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*
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* - Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps
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* Ethernet Controller for PCI Local Bus
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*
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* - Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller
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* with OnNow Support
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*
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* - Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI
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* Ethernet Controller with Integrated PHY
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*
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* - Am79c978 PCnet-Home Single-Chip 1/10 Mbps PCI Home
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* Networking Controller.
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*
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* Initialization block, transmit descriptor, and receive descriptor
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* formats are described in two separate files:
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*
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* 16-bit software model (LANCE) am7990reg.h
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*
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* 32-bit software model (ILACC) am79900reg.h
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*
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* Note that the vast majority of the registers described in this file
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* belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are
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* valid on the LANCE.
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*/
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#define LEBLEN 1536 /* ETHERMTU + header + CRC */
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#define LEMINSIZE 60 /* should be 64 if mode DTCR is set */
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@ -83,11 +133,133 @@
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#define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr[bix])
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#define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr[bix])
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/* register addresses */
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/*
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* Control and Status Register addresses
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*/
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#define LE_CSR0 0x0000 /* Control and status register */
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#define LE_CSR1 0x0001 /* low address of init block */
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#define LE_CSR2 0x0002 /* high address of init block */
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#define LE_CSR3 0x0003 /* Bus master and control */
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#define LE_CSR4 0x0004 /* Test and features control */
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#define LE_CSR5 0x0005 /* Extended control and Interrupt 1 */
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#define LE_CSR6 0x0006 /* Rx/Tx Descriptor table length */
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#define LE_CSR7 0x0007 /* Extended control and interrupt 2 */
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#define LE_CSR8 0x0008 /* Logical Address Filter 0 */
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#define LE_CSR9 0x0009 /* Logical Address Filter 1 */
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#define LE_CSR10 0x000a /* Logical Address Filter 2 */
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#define LE_CSR11 0x000b /* Logical Address Filter 3 */
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#define LE_CSR12 0x000c /* Physical Address 0 */
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#define LE_CSR13 0x000d /* Physical Address 1 */
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#define LE_CSR14 0x000e /* Physical Address 2 */
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#define LE_CSR15 0x000f /* Mode */
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#define LE_CSR16 0x0010 /* Initialization Block addr lower */
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#define LE_CSR17 0x0011 /* Initialization Block addr upper */
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#define LE_CSR18 0x0012 /* Current Rx Buffer addr lower */
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#define LE_CSR19 0x0013 /* Current Rx Buffer addr upper */
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#define LE_CSR20 0x0014 /* Current Tx Buffer addr lower */
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#define LE_CSR21 0x0015 /* Current Tx Buffer addr upper */
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#define LE_CSR22 0x0016 /* Next Rx Buffer addr lower */
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#define LE_CSR23 0x0017 /* Next Rx Buffer addr upper */
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#define LE_CSR24 0x0018 /* Base addr of Rx ring lower */
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#define LE_CSR25 0x0019 /* Base addr of Rx ring upper */
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#define LE_CSR26 0x001a /* Next Rx Desc addr lower */
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#define LE_CSR27 0x001b /* Next Rx Desc addr upper */
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#define LE_CSR28 0x001c /* Current Rx Desc addr lower */
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#define LE_CSR29 0x001d /* Current Rx Desc addr upper */
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#define LE_CSR30 0x001e /* Base addr of Tx ring lower */
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#define LE_CSR31 0x001f /* Base addr of Tx ring upper */
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#define LE_CSR32 0x0020 /* Next Tx Desc addr lower */
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#define LE_CSR33 0x0021 /* Next Tx Desc addr upper */
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#define LE_CSR34 0x0022 /* Current Tx Desc addr lower */
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#define LE_CSR35 0x0023 /* Current Tx Desc addr upper */
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#define LE_CSR36 0x0024 /* Next Next Rx Desc addr lower */
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#define LE_CSR37 0x0025 /* Next Next Rx Desc addr upper */
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#define LE_CSR38 0x0026 /* Next Next Tx Desc addr lower */
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#define LE_CSR39 0x0027 /* Next Next Tx Desc adddr upper */
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#define LE_CSR40 0x0028 /* Current Rx Byte Count */
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#define LE_CSR41 0x0029 /* Current Rx Status */
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#define LE_CSR42 0x002a /* Current Tx Byte Count */
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#define LE_CSR43 0x002b /* Current Tx Status */
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#define LE_CSR44 0x002c /* Next Rx Byte Count */
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#define LE_CSR45 0x002d /* Next Rx Status */
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#define LE_CSR46 0x002e /* Tx Poll Time Counter */
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#define LE_CSR47 0x002f /* Tx Polling Interval */
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#define LE_CSR48 0x0030 /* Rx Poll Time Counter */
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#define LE_CSR49 0x0031 /* Rx Polling Interval */
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#define LE_CSR58 0x003a /* Software Style */
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#define LE_CSR60 0x003c /* Previous Tx Desc addr lower */
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#define LE_CSR61 0x003d /* Previous Tx Desc addr upper */
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#define LE_CSR62 0x003e /* Previous Tx Byte Count */
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#define LE_CSR63 0x003f /* Previous Tx Status */
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#define LE_CSR64 0x0040 /* Next Tx Buffer addr lower */
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#define LE_CSR65 0x0041 /* Next Tx Buffer addr upper */
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#define LE_CSR66 0x0042 /* Next Tx Byte Count */
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#define LE_CSR67 0x0043 /* Next Tx Status */
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#define LE_CSR72 0x0048 /* Receive Ring Counter */
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#define LE_CSR74 0x004a /* Transmit Ring Counter */
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#define LE_CSR76 0x004c /* Receive Ring Length */
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#define LE_CSR78 0x004e /* Transmit Ring Length */
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#define LE_CSR80 0x0050 /* DMA Transfer Counter and FIFO
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Threshold Control */
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#define LE_CSR82 0x0052 /* Tx Desc addr Pointer lower */
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#define LE_CSR84 0x0054 /* DMA addr register lower */
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#define LE_CSR85 0x0055 /* DMA addr register upper */
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#define LE_CSR86 0x0056 /* Buffer Byte Counter */
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#define LE_CSR88 0x0058 /* Chip ID Register lower */
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#define LE_CSR89 0x0059 /* Chip ID Register upper */
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#define LE_CSR92 0x005c /* Ring Length Conversion */
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#define LE_CSR100 0x0064 /* Bus Timeout */
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#define LE_CSR112 0x0070 /* Missed Frame Count */
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#define LE_CSR114 0x0072 /* Receive Collision Count */
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#define LE_CSR116 0x0074 /* OnNow Power Mode Register */
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#define LE_CSR122 0x007a /* Advanced Feature Control */
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#define LE_CSR124 0x007c /* Test Register 1 */
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#define LE_CSR125 0x007d /* MAC Enhanced Configuration Control */
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/*
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* Bus Configuration Register addresses
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*/
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#define LE_BCR0 0x0000 /* Master Mode Read Active */
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#define LE_BCR1 0x0001 /* Master Mode Write Active */
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#define LE_BCR2 0x0002 /* Misc. Configuration */
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#define LE_BCR4 0x0004 /* LED0 Status */
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#define LE_BCR5 0x0005 /* LED1 Status */
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#define LE_BCR6 0x0006 /* LED2 Status */
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#define LE_BCR7 0x0007 /* LED3 Status */
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#define LE_BCR9 0x0009 /* Full-duplex Control */
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#define LE_BCR16 0x0010 /* I/O Base Address lower */
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#define LE_BCR17 0x0011 /* I/O Base Address upper */
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#define LE_BCR18 0x0012 /* Burst and Bus Control Register */
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#define LE_BCR19 0x0013 /* EEPROM Control and Status */
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#define LE_BCR20 0x0014 /* Software Style */
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#define LE_BCR22 0x0016 /* PCI Latency Register */
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#define LE_BCR23 0x0017 /* PCI Subsystem Vendor ID */
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#define LE_BCR24 0x0018 /* PCI Subsystem ID */
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#define LE_BCR25 0x0019 /* SRAM Size Register */
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#define LE_BCR26 0x001a /* SRAM Boundary Register */
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#define LE_BCR27 0x001b /* SRAM Interface Control Register */
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#define LE_BCR28 0x001c /* Exp. Bus Port Addr lower */
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#define LE_BCR29 0x001d /* Exp. Bus Port Addr upper */
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#define LE_BCR30 0x001e /* Exp. Bus Data Port */
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#define LE_BCR31 0x001f /* Software Timer Register */
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#define LE_BCR32 0x0020 /* PHY Control and Status Register */
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#define LE_BCR33 0x0021 /* PHY Address Register */
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#define LE_BCR34 0x0022 /* PHY Management Data Register */
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#define LE_BCR35 0x0023 /* PCI Vendor ID Register */
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#define LE_BCR36 0x0024 /* PCI Power Management Cap. Alias */
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#define LE_BCR37 0x0025 /* PCI DATA0 Alias */
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#define LE_BCR38 0x0026 /* PCI DATA1 Alias */
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#define LE_BCR39 0x0027 /* PCI DATA2 Alias */
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#define LE_BCR40 0x0028 /* PCI DATA3 Alias */
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#define LE_BCR41 0x0029 /* PCI DATA4 Alias */
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#define LE_BCR42 0x002a /* PCI DATA5 Alias */
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#define LE_BCR43 0x002b /* PCI DATA6 Alias */
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#define LE_BCR44 0x002c /* PCI DATA7 Alias */
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#define LE_BCR45 0x002d /* OnNow Pattern Matching 1 */
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#define LE_BCR46 0x002e /* OnNow Pattern Matching 2 */
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#define LE_BCR47 0x002f /* OnNow Pattern Matching 3 */
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#define LE_BCR48 0x0030 /* LED4 Status */
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#define LE_BCR49 0x0031 /* PHY Select */
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/* Control and status register 0 (csr0) */
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#define LE_C0_ERR 0x8000 /* error summary */
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@ -112,10 +284,268 @@
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\12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT"
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/* Control and status register 3 (csr3) */
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#define LE_C3_MISSM 0x1000 /* missed frame mask */
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#define LE_C3_MERRM 0x0800 /* memory error mask */
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#define LE_C3_RINTM 0x0400 /* receive interrupt mask */
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#define LE_C3_TINTM 0x0200 /* transmit interrupt mask */
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#define LE_C3_IDONM 0x0100 /* initialization done mask */
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#define LE_C3_DXSUFLO 0x0040 /* disable tx stop on underflow */
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#define LE_C3_LAPPEN 0x0020 /* look ahead packet processing enbl */
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#define LE_C3_DXMT2PD 0x0010 /* disable tx two part deferral */
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#define LE_C3_EMBA 0x0008 /* enable modified backoff algorithm */
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#define LE_C3_BSWP 0x0004 /* byte swap */
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#define LE_C3_ACON 0x0002 /* ALE control, eh? */
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#define LE_C3_BCON 0x0001 /* byte control */
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/* Control and status register 4 (csr4) */
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#define LE_C4_DMAPLUS 0x4000 /* always set (PCnet-PCI) */
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#define LE_C4_TXDPOLL 0x1000 /* disable transmit polling */
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#define LE_C4_APAD_XMT 0x0800 /* auto pad transmit */
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#define LE_C4_ASTRP_RCV 0x0400 /* auto strip receive */
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#define LE_C4_MFCO 0x0200 /* missed frame counter overflow */
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#define LE_C4_MFCOM 0x0100 /* missed frame coutner overflow mask */
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#define LE_C4_UINTCMD 0x0080 /* user interrupt command */
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#define LE_C4_UINT 0x0040 /* user interrupt */
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#define LE_C4_RCVCCO 0x0020 /* receive collision counter overflow */
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#define LE_C4_RCVCCOM 0x0010 /* receive collision counter overflow
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mask */
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#define LE_C4_TXSTRT 0x0008 /* transmit start status */
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#define LE_C4_TXSTRTM 0x0004 /* transmit start mask */
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/* Control and status register 5 (csr5) */
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#define LE_C5_TOKINTD 0x8000 /* transmit ok interrupt disable */
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#define LE_C5_LTINTEN 0x4000 /* last transmit interrupt enable */
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#define LE_C5_SINT 0x0800 /* system interrupt */
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#define LE_C5_SINTE 0x0400 /* system interrupt enable */
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#define LE_C5_EXDINT 0x0080 /* excessive deferral interrupt */
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#define LE_C5_EXDINTE 0x0040 /* excessive deferral interrupt enbl */
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#define LE_C5_MPPLBA 0x0020 /* magic packet physical logical
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broadcast accept */
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#define LE_C5_MPINT 0x0010 /* magic packet interrupt */
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#define LE_C5_MPINTE 0x0008 /* magic packet interrupt enable */
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#define LE_C5_MPEN 0x0004 /* magic packet enable */
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#define LE_C5_MPMODE 0x0002 /* magic packet mode */
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#define LE_C5_SPND 0x0001 /* suspend */
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/* Control and status register 6 (csr6) */
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#define LE_C6_TLEN 0xf000 /* TLEN from init block */
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#define LE_C6_RLEN 0x0f00 /* RLEN from init block */
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/* Control and status register 7 (csr7) */
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#define LE_C7_FASTSPNDE 0x8000 /* fast suspend enable */
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#define LE_C7_RDMD 0x2000 /* receive demand */
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#define LE_C7_RDXPOLL 0x1000 /* receive disable polling */
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#define LE_C7_STINT 0x0800 /* software timer interrupt */
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#define LE_C7_STINTE 0x0400 /* software timer interrupt enable */
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#define LE_C7_MREINT 0x0200 /* PHY management read error intr */
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#define LE_C7_MREINTE 0x0100 /* PHY management read error intr
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enable */
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#define LE_C7_MAPINT 0x0080 /* PHY management auto-poll intr */
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#define LE_C7_MAPINTE 0x0040 /* PHY management auto-poll intr
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enable */
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#define LE_C7_MCCINT 0x0020 /* PHY management command complete
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interrupt */
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#define LE_C7_MCCINTE 0x0010 /* PHY management command complete
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interrupt enable */
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#define LE_C7_MCCIINT 0x0008 /* PHY management command complete
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internal interrupt */
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#define LE_C7_MCCIINTE 0x0004 /* PHY management command complete
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internal interrupt enable */
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#define LE_C7_MIIPDTINT 0x0002 /* PHY management detect transition
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interrupt */
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#define LE_C7_MIIPDTINTE 0x0001 /* PHY management detect transition
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interrupt enable */
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/* control and status register 80 (csr80) */
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#define LE_C80_RCVFW1 0x2000 /* Receive FIFO Watermark 1 */
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#define LE_C80_RCVFW0 0x1000 /* Receive FIFO Watermark 0 */
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/* 00 16 bytes */
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/* 01 64 bytes */
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/* 10 112 bytes */
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/* 11 reserved */
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#define LE_C80_XMTSP1 0x0800 /* Transmit Start Point 1 */
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#define LE_C80_XMTSP0 0x0400 /* Transmit Start Point 0 */
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/* 00 0 20 bytes */
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/* 01 0 64 bytes */
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/* 10 0 128 bytes */
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/* 11 0 220 max */
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/* 00 >0 36 bytes */
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/* 01 >0 64 bytes */
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/* 10 >0 128 bytes */
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/* 11 >0 store-and-fwd */
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#define LE_C80_XMTFW1 0x0200 /* Transmit FIFO Watermark 1 */
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#define LE_C80_XMTFW0 0x0100 /* Transmit FIFO Watermark 0 */
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/* 00 16 bytes */
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/* 01 64 bytes */
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/* 10 108 bytes */
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/* 11 reserved */
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#define LE_C80_DMATC 0x00ff /* DMA transfer counter */
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/* control and status register 116 (csr116) */
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#define LE_C116_PME_EN_OVR 0x0400 /* PME_EN overwrite */
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#define LE_C116_LCDET 0x0200 /* link change detected */
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#define LE_C116_LCMODE 0x0100 /* link change wakeup mode */
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#define LE_C116_PMAT 0x0080 /* pattern matched */
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#define LE_C116_EMPPLBA 0x0040 /* magic packet physical logical
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broadcast accept */
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#define LE_C116_MPMAT 0x0020 /* magic packet match */
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#define LE_C116_MPPEN 0x0010 /* magic packet pin enable */
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#define LE_C116_RST_POL 0x0001 /* PHY_RST pin polarity */
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/* control and status register 122 (csr122) */
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#define LE_C122_RCVALGN 0x0001 /* receive packet align */
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/* control and status register 124 (csr124) */
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#define LE_C124_RPA 0x0008 /* runt packet accept */
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/* control and status register 125 (csr125) */
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#define LE_C125_IPG 0xff00 /* inter-packet gap */
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#define LE_C125_IFS1 0x00ff /* inter-frame spacing part 1 */
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/* bus configuration register 0 (bcr0) */
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#define LE_B0_MSRDA 0xffff /* reserved locations */
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/* bus configuration register 1 (bcr1) */
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#define LE_B1_MSWRA 0xffff /* reserved locations */
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/* bus configuration register 2 (bcr2) */
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#define LE_B2_PHYSSELEN 0x2000 /* enable writes to BCR18[4:3] */
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#define LE_B2_LEDPE 0x1000 /* LED program enable */
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#define LE_B2_APROMWE 0x0100 /* Address PROM Write Enable */
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#define LE_B2_INTLEVEL 0x0080 /* 1 == edge triggered */
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/* bus configuration register 4 (bcr4) */
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/* bus configuration register 5 (bcr5) */
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/* bus configuration register 6 (bcr6) */
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/* bus configuration register 7 (bcr7) */
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/* bus configuration register 48 (bcr48) */
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#define LE_B4_LEDOUT 0x8000 /* LED output active */
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#define LE_B4_LEDPOL 0x4000 /* LED polarity */
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#define LE_B4_LEDDIS 0x2000 /* LED disable */
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#define LE_B4_100E 0x1000 /* 100Mb/s enable */
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#define LE_B4_MPSE 0x0200 /* magic packet status enable */
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#define LE_B4_FDLSE 0x0100 /* full-duplex link status enable */
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#define LE_B4_PSE 0x0080 /* pulse stretcher enable */
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#define LE_B4_LNKSE 0x0040 /* link status enable */
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#define LE_B4_RCVME 0x0020 /* receive match status enable */
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#define LE_B4_XMTE 0x0010 /* transmit status enable */
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#define LE_B4_POWER 0x0008 /* power enable */
|
||||
#define LE_B4_RCVE 0x0004 /* receive status enable */
|
||||
#define LE_B4_SPEED 0x0002 /* high speed enable */
|
||||
#define LE_B4_COLE 0x0001 /* collision status enable */
|
||||
|
||||
/* bus configuration register 9 (bcr9) */
|
||||
#define LE_B9_FDRPAD 0x0004 /* full-duplex runt packet accept
|
||||
disable */
|
||||
#define LE_B9_FDEN 0x0001 /* full-duplex enable */
|
||||
|
||||
/* bus configuration register 18 (bcr18) */
|
||||
#define LE_B18_ROMTMG 0xf000 /* expansion rom timing */
|
||||
#define LE_B18_NOUFLO 0x0800 /* no underflow on transmit */
|
||||
#define LE_B18_MEMCMD 0x0200 /* memory read multiple enable */
|
||||
#define LE_B18_EXTREQ 0x0100 /* extended request */
|
||||
#define LE_B18_DWIO 0x0080 /* double-word I/O */
|
||||
#define LE_B18_BREADE 0x0040 /* burst read enable */
|
||||
#define LE_B18_BWRITE 0x0020 /* burst write enable */
|
||||
#define LE_B18_PHYSEL1 0x0010 /* PHYSEL 1 */
|
||||
#define LE_B18_PHYSEL0 0x0008 /* PHYSEL 0 */
|
||||
/* 00 ex ROM/Flash */
|
||||
/* 01 EADI/MII snoop */
|
||||
/* 10 reserved */
|
||||
/* 11 reserved */
|
||||
#define LE_B18_LINBC 0x0007 /* reserved locations */
|
||||
|
||||
/* bus configuration register 19 (bcr19) */
|
||||
#define LE_B19_PVALID 0x8000 /* EEPROM status valid */
|
||||
#define LE_B19_PREAD 0x4000 /* EEPROM read command */
|
||||
#define LE_B19_EEDET 0x2000 /* EEPROM detect */
|
||||
#define LE_B19_EEN 0x0010 /* EEPROM port enable */
|
||||
#define LE_B19_ECS 0x0004 /* EEPROM chip select */
|
||||
#define LE_B19_ESK 0x0002 /* EEPROM serial clock */
|
||||
#define LE_B19_EDI 0x0001 /* EEPROM data in */
|
||||
#define LE_B19_EDO 0x0001 /* EEPROM data out */
|
||||
|
||||
/* bus configuration register 20 (bcr20) */
|
||||
#define LE_B20_APERREN 0x0400 /* Advanced parity error handling */
|
||||
#define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */
|
||||
#define LE_B20_SSTYLE 0x0007 /* Software Style */
|
||||
#define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */
|
||||
#define LE_B20_SSTYLE_PCNETPCI2 2 /* PCnet-PCI (32-bit) */
|
||||
#define LE_B20_SSTYLE_PCNETPCI3 3 /* PCnet-PCI (32-bit) */
|
||||
|
||||
/* bus configuration register 25 (bcr25) */
|
||||
#define LE_B25_SRAM_SIZE 0x00ff /* SRAM size */
|
||||
|
||||
/* bus configuration register 26 (bcr26) */
|
||||
#define LE_B26_SRAM_BND 0x00ff /* SRAM boundary */
|
||||
|
||||
/* bus configuration register 27 (bcr27) */
|
||||
#define LE_B27_PTRTST 0x8000 /* reserved for manuf. tests */
|
||||
#define LE_B27_LOLATRX 0x4000 /* low latency receive */
|
||||
#define LE_B27_EBCS 0x0038 /* expansion bus clock source */
|
||||
/* 000 CLK pin */
|
||||
/* 001 time base clock */
|
||||
/* 010 EBCLK pin */
|
||||
/* 011 reserved */
|
||||
/* 1xx reserved */
|
||||
#define LE_B27_CLK_FAC 0x0007 /* clock factor */
|
||||
/* 000 1 */
|
||||
/* 001 1/2 */
|
||||
/* 010 reserved */
|
||||
/* 011 1/4 */
|
||||
/* 1xx reserved */
|
||||
|
||||
/* bus configuration register 28 (bcr28) */
|
||||
#define LE_B28_EADDRL 0xffff /* expansion port address lower */
|
||||
|
||||
/* bus configuration register 29 (bcr29) */
|
||||
#define LE_B29_FLASH 0x8000 /* flash access */
|
||||
#define LE_B29_LAAINC 0x4000 /* lower address auto increment */
|
||||
#define LE_B29_EPADDRU 0x0007 /* expansion port address upper */
|
||||
|
||||
/* bus configuration register 30 (bcr30) */
|
||||
#define LE_B30_EBDATA 0xffff /* expansion bus data port */
|
||||
|
||||
/* bus configuration register 31 (bcr31) */
|
||||
#define LE_B31_STVAL 0xffff /* software timer value */
|
||||
|
||||
/* bus configuration register 32 (bcr32) */
|
||||
#define LE_B32_ANTST 0x8000 /* reserved for manuf. tests */
|
||||
#define LE_B32_MIIPD 0x4000 /* MII PHY Detect (manuf. tests) */
|
||||
#define LE_B32_FMDC 0x3000 /* fast management data clock */
|
||||
#define LE_B32_APEP 0x0800 /* auto-poll PHY */
|
||||
#define LE_B32_APDW 0x0700 /* auto-poll dwell time */
|
||||
#define LE_B32_DANAS 0x0080 /* disable autonegotiation */
|
||||
#define LE_B32_XPHYRST 0x0040 /* PHY reset */
|
||||
#define LE_B32_XPHYANE 0x0020 /* PHY autonegotiation enable */
|
||||
#define LE_B32_XPHYFD 0x0010 /* PHY full-duplex */
|
||||
#define LE_B32_XPHYSP 0x0008 /* PHY speed */
|
||||
#define LE_B32_MIIILP 0x0002 /* MII internal loopback */
|
||||
|
||||
/* bus configuration register 33 (bcr33) */
|
||||
#define LE_B33_SHADOW 0x8000 /* shadow enable */
|
||||
#define LE_B33_MII_SEL 0x4000 /* MII selected */
|
||||
#define LE_B33_ACOMP 0x2000 /* internal PHY autonegotiation comp */
|
||||
#define LE_B33_LINK 0x1000 /* link status */
|
||||
#define LE_B33_FDX 0x0800 /* full-duplex */
|
||||
#define LE_B33_SPEED 0x0400 /* 1 == high speed */
|
||||
#define LE_B33_PHYAD 0x03e0 /* PHY address */
|
||||
#define PHYAD_SHIFT 5
|
||||
#define LE_B33_REGAD 0x001f /* register address */
|
||||
|
||||
/* bus configuration register 34 (bcr34) */
|
||||
#define LE_B34_MIIMD 0xffff /* MII data */
|
||||
|
||||
/* bus configuration register 49 (bcr49) */
|
||||
#define LE_B49_PCNET 0x8000 /* PCnet mode - Must Be One */
|
||||
#define LE_B49_PHYSEL_D 0x0300 /* PHY_SEL_Default */
|
||||
#define LE_B49_PHYSEL_L 0x0010 /* PHY_SEL_Lock */
|
||||
#define LE_B49_PHYSEL 0x0003 /* PHYSEL */
|
||||
/* 00 10baseT PHY */
|
||||
/* 01 HomePNA PYY */
|
||||
/* 10 external PHY */
|
||||
/* 11 reserved */
|
||||
|
||||
/* Initialzation block (mode) */
|
||||
#define LE_MODE_PROM 0x8000 /* promiscuous mode */
|
||||
/* 0x7f80 reserved, must be zero */
|
||||
|
|
|
|||
Loading…
Reference in New Issue