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DEC specifies that dealing with CSR0 in the interrupt routine must be 

done in a special order. Do that here also, but for now inside #ifdef vax
because of the (possible) impact on other arch's.
Now vaxen without IOMMU can use the MI LANCE driver.
This commit is contained in:
ragge 1999-10-29 19:50:07 +00:00
parent 05bfcdfbf4
commit 12c16f443f
1 changed files with 11 additions and 1 deletions
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12
sys/dev/ic/am7990.c
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@ -1,4 +1,4 @@
/* $NetBSD: am7990.c,v 1.54 1998/08/15 10:51:17 mycroft Exp $ */
/* $NetBSD: am7990.c,v 1.55 1999/10/29 19:50:07 ragge Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
@ -411,9 +411,19 @@ am7990_intr(arg)
if ((isr & LE_C0_INTR) == 0)
return (0);
#ifdef __vax__
/*
* DEC needs this write order to the registers, don't know
* the results on other arch's. Ragge 991029
*/
isr &= ~LE_C0_INEA;
(*sc->sc_wrcsr)(sc, LE_CSR0, isr);
(*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA);
#else
(*sc->sc_wrcsr)(sc, LE_CSR0,
isr & (LE_C0_INEA | LE_C0_BABL | LE_C0_MISS | LE_C0_MERR |
LE_C0_RINT | LE_C0_TINT | LE_C0_IDON));
#endif
if (isr & LE_C0_ERR) {
if (isr & LE_C0_BABL) {
#ifdef LEDEBUG