Use size_t in prototype (so this will be LP64 clean for PPC64 someday).
Calculate len separately for icache & dcache in case each has different cacheline widths. Make the code for both loops the same except for the dcbst/icbi. Deal with sizes >=2GB properly (like that'll happen but ...)
This commit is contained in:
parent
dde8f75509
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12810ed37d
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@ -1,4 +1,4 @@
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/* $NetBSD: syncicache.c,v 1.8 2002/03/18 05:10:58 dbj Exp $ */
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/* $NetBSD: syncicache.c,v 1.9 2002/03/26 21:20:24 matt Exp $ */
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/*
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* Copyright (C) 1995-1997, 1999 Wolfgang Solfrank.
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@ -92,11 +92,11 @@ getcachelinesize(void)
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#endif
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void
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__syncicache(void *from, int len)
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__syncicache(void *from, size_t len)
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{
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int l, off;
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size_t l, off;
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size_t linesz;
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char *p;
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int linesz;
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#if !defined(_KERNEL) && !defined(_STANDALONE)
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if (!_cachelinesize)
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@ -105,24 +105,25 @@ __syncicache(void *from, int len)
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if (CACHEINFO.dcache_size > 0) {
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linesz = CACHEINFO.dcache_line_size;
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off = (u_int)from & (linesz - 1);
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l = len += off;
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off = (uintptr_t)from & (linesz - 1);
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l = (len + off + linesz - 1) & ~(linesz - 1);
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p = (char *)from - off;
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do {
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__asm__ __volatile ("dcbst 0,%0" :: "r"(p));
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p += linesz;
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} while ((l -= linesz) > 0);
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} while ((l -= linesz) != 0);
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}
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__asm__ __volatile ("sync");
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if (CACHEINFO.icache_size > 0 ) {
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linesz = CACHEINFO.icache_line_size;
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off = (u_int)from & (linesz - 1);
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off = (uintptr_t)from & (linesz - 1);
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l = (len + off + linesz - 1) & ~(linesz - 1);
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p = (char *)from - off;
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do {
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__asm__ __volatile ("icbi 0,%0" :: "r"(p));
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p += linesz;
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} while ((len -= linesz) > 0);
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} while ((l -= linesz) != 0);
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}
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__asm__ __volatile ("isync");
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.h,v 1.14 2002/03/13 00:38:13 eeh Exp $ */
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/* $NetBSD: cpu.h,v 1.15 2002/03/26 21:20:24 matt Exp $ */
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/*
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* Copyright (C) 1999 Wolfgang Solfrank.
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@ -184,7 +184,7 @@ extern void icache_flush(vaddr_t, vsize_t);
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#endif
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#endif
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void __syncicache(void *, int);
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void __syncicache(void *, size_t);
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: syncicache.c,v 1.6 2002/03/18 05:10:59 dbj Exp $ */
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/* $NetBSD: syncicache.c,v 1.7 2002/03/26 21:20:24 matt Exp $ */
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/*
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* Copyright (C) 1995-1997, 1999 Wolfgang Solfrank.
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@ -92,11 +92,11 @@ getcachelinesize(void)
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#endif
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void
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__syncicache(void *from, int len)
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__syncicache(void *from, size_t len)
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{
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int l, off;
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size_t l, off;
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size_t linesz;
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char *p;
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int linesz;
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#if !defined(_KERNEL) && !defined(_STANDALONE)
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if (!_cachelinesize)
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@ -105,24 +105,25 @@ __syncicache(void *from, int len)
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if (CACHEINFO.dcache_size > 0) {
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linesz = CACHEINFO.dcache_line_size;
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off = (u_int)from & (linesz - 1);
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l = len += off;
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off = (uintptr_t)from & (linesz - 1);
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l = (len + off + linesz - 1) & ~(linesz - 1);
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p = (char *)from - off;
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do {
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__asm__ __volatile ("dcbst 0,%0" :: "r"(p));
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p += linesz;
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} while ((l -= linesz) > 0);
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} while ((l -= linesz) != 0);
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}
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__asm__ __volatile ("sync");
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if (CACHEINFO.icache_size > 0 ) {
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linesz = CACHEINFO.icache_line_size;
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off = (u_int)from & (linesz - 1);
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off = (uintptr_t)from & (linesz - 1);
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l = (len + off + linesz - 1) & ~(linesz - 1);
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p = (char *)from - off;
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do {
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__asm__ __volatile ("icbi 0,%0" :: "r"(p));
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p += linesz;
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} while ((len -= linesz) > 0);
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} while ((l -= linesz) != 0);
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}
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__asm__ __volatile ("isync");
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}
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