Add the final glue bits required to enable the SPI interface on the
DBAU1550. This is parameterized somewhat as machdep pluggable code, so different boards can supply different implementations. At the moment, the DBAU1550 is the only Au1550 board I know of with SPI connected devices. I have not enabled I2C on the DBAU1550, as we do not have drivers for either of the I2C connected devices (a different temperature/voltage sensor and a serial eeprom.)
This commit is contained in:
gdamore
parent
bcad08160c
commit
118d36b6e7
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@ -1,4 +1,4 @@
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/* $NetBSD: board.h,v 1.3 2006/02/23 03:51:40 gdamore Exp $ */
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/* $NetBSD: board.h,v 1.4 2006/10/02 08:13:53 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Itronix Inc.
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@ -48,6 +48,8 @@ struct alchemy_board {
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struct aupcmcia_machdep *ab_pcmcia;
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const struct auspi_machdep *(*ab_spi)(bus_addr_t);
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/*
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* XXX: csb250 (and perhaps others) will require pci_idsel
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* entry point
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@ -1,4 +1,4 @@
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/* $NetBSD: dbau1550.c,v 1.6 2006/03/25 07:28:20 gdamore Exp $ */
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/* $NetBSD: dbau1550.c,v 1.7 2006/10/02 08:13:53 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Itronix Inc.
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@ -32,7 +32,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: dbau1550.c,v 1.6 2006/03/25 07:28:20 gdamore Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dbau1550.c,v 1.7 2006/10/02 08:13:53 gdamore Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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@ -45,10 +45,13 @@ __KERNEL_RCSID(0, "$NetBSD: dbau1550.c,v 1.6 2006/03/25 07:28:20 gdamore Exp $")
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#include <mips/alchemy/dev/aupcmciavar.h>
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#include <mips/alchemy/dev/aupcmciareg.h>
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#include <mips/alchemy/dev/augpioreg.h>
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#include <mips/alchemy/dev/auspivar.h>
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#include <evbmips/alchemy/obiovar.h>
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#include <evbmips/alchemy/board.h>
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#include <evbmips/alchemy/dbau1550reg.h>
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#include "auspi.h"
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/*
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* This should be converted to use bus_space routines.
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*/
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@ -72,13 +75,9 @@ static void dbau1550_slot_enable(int);
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static void dbau1550_slot_disable(int);
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static int dbau1550_slot_status(int);
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static const char *dbau1550_slot_name(int);
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static const struct auspi_machdep *dbau1550_spi(bus_addr_t);
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static const struct obiodev dbau1550_devices[] = {
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#if 0
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{ "aupsc", -1, -1 },
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{ "aupsc", -1, -1 },
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{ "aupsc", -1, -1 },
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#endif
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{ NULL },
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};
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@ -93,13 +92,14 @@ static struct aupcmcia_machdep dbau1550_pcmcia = {
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};
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static struct alchemy_board dbau1550_info = {
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"AMD Alchemy DBAu1550",
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dbau1550_devices,
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dbau1550_init,
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dbau1550_pci_intr_map,
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dbau1550_reboot,
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dbau1550_poweroff,
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&dbau1550_pcmcia,
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.ab_name = "AMD Alchemy DBAu1550",
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.ab_devices = dbau1550_devices,
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.ab_init = dbau1550_init,
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.ab_pci_intr_map =dbau1550_pci_intr_map,
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.ab_reboot = dbau1550_reboot,
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.ab_poweroff = dbau1550_poweroff,
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.ab_pcmcia = &dbau1550_pcmcia,
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.ab_spi = dbau1550_spi,
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};
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const struct alchemy_board *
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@ -113,6 +113,8 @@ void
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dbau1550_init(void)
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{
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uint16_t whoami;
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uint32_t sysclk;
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uint32_t pinfunc;
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if (MIPS_PRID_COPTS(cpu_id) != MIPS_AU1550)
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panic("dbau1550: CPU not Au1550");
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@ -133,6 +135,35 @@ dbau1550_init(void)
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printf("no daughtercard\n");
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/* leave console and clocks alone -- YAMON should have got it right! */
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/*
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* Initialize PSC clocks.
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*
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* PSC0 is SPI. Use 48MHz FREQ1.
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* PSC1 is AC97.
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* PSC2 is SMBus, and must be 48MHz. (Configured by YAMON)
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* PSC3 is I2S.
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*
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* FREQ2 is 48MHz for USBH/USBD.
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*/
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sysclk = GET32(SYS_CLKSRC);
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sysclk &= ~(SCS_MP0(7) | SCS_DP0 | SCS_CP0);
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sysclk |= SCS_MP0(3);
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PUT32(SYS_CLKSRC, sysclk);
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/*
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* Configure pin function for PSC devices.
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*/
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pinfunc = GET32(SYS_PINFUNC);
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/* configure PSC0 SYNC1 */
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pinfunc |= SPF_S0;
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/* configure PSC2 for SMBus (YAMON default) */
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pinfunc &= ~SPF_PSC2_MASK;
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pinfunc |= SPF_PSC2_SMBUS;
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/* configure PSC3 for I2S (YAMON default) */
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pinfunc &= ~SPF_PSC3_MASK;
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pinfunc |= SPF_PSC3_I2S;
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PUT32(SYS_PINFUNC, pinfunc);
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}
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int
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@ -337,3 +368,40 @@ dbau1550_slot_name(int slot)
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return "???";
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}
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}
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#if NAUSPI > 0
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static int
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dbau1550_spi_select(void *arg, int slave)
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{
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uint16_t status;
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if ((slave < 0) || (slave > 1))
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return EINVAL;
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status = GET16(DBAU1550_BOARD_SPECIFIC);
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if (slave) {
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status |= DBAU1550_SPI_DEV_SEL;
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} else {
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status &= ~DBAU1550_SPI_DEV_SEL;
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}
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PUT16(DBAU1550_BOARD_SPECIFIC, status);
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return 0;
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}
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const struct auspi_machdep *
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dbau1550_spi(bus_addr_t ba)
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{
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static const struct auspi_machdep md = {
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.am_nslaves = 2,
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.am_cookie = NULL,
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.am_select = dbau1550_spi_select,
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};
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/* DBAU1550 only has SPI on PSC0 */
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if (ba != PSC0_BASE)
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return NULL;
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return &md;
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}
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#endif /* NAUSPI > 0 */
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@ -1,4 +1,4 @@
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/* $NetBSD: dbau1550reg.h,v 1.4 2006/02/23 03:51:40 gdamore Exp $ */
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/* $NetBSD: dbau1550reg.h,v 1.5 2006/10/02 08:13:53 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Itronix Inc.
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@ -81,7 +81,7 @@
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/*
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* DBAU1550_BOARD_SPECIFIC
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*/
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#define DBAU1550_PCI_SPI_DEV_SEL (1 << 13)
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#define DBAU1550_SPI_DEV_SEL (1 << 13)
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#define DBAU1550_PCI_CFG_HOST (1 << 12)
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#define DBAU1550_PCI_EN_GPIO200_RST (1 << 10)
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#define DBAU1550_PCI_M33 (1 << 8)
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.30 2006/09/09 03:58:46 simonb Exp $ */
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/* $NetBSD: machdep.c,v 1.31 2006/10/02 08:13:53 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Itronix Inc.
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@ -107,7 +107,7 @@
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.30 2006/09/09 03:58:46 simonb Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.31 2006/10/02 08:13:53 gdamore Exp $");
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#include "opt_ddb.h"
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#include "opt_kgdb.h"
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@ -148,6 +148,7 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.30 2006/09/09 03:58:46 simonb Exp $");
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#include <evbmips/alchemy/board.h>
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#include <mips/alchemy/dev/aupcivar.h>
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#include <mips/alchemy/dev/aupcmciavar.h>
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#include <mips/alchemy/dev/auspivar.h>
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#include <mips/alchemy/include/aureg.h>
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#include <mips/alchemy/include/auvar.h>
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#include <mips/alchemy/include/aubusvar.h>
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@ -556,3 +557,14 @@ aupcmcia_machdep(void)
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board = board_info();
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return (board->ab_pcmcia);
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}
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const struct auspi_machdep *
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auspi_machdep(bus_addr_t ba)
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{
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const struct alchemy_board *board;
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board = board_info();
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if (board->ab_spi != NULL)
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return (board->ab_spi(ba));
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return NULL;
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}
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@ -1,4 +1,4 @@
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# $NetBSD: DBAU1550,v 1.8 2006/04/04 04:30:28 gdamore Exp $
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# $NetBSD: DBAU1550,v 1.9 2006/10/02 08:13:53 gdamore Exp $
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#
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# Kernel config for the AMD Alchemy DBAu1550 evaluation board.
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@ -57,3 +57,17 @@ atapibus* at atabus?
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cd* at atapibus? drive ? flags 0x0000 # ATAPI CD-ROM drives
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sd* at atapibus? drive ? flags 0x0000 # ATAPI disk drives
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uk* at atapibus? drive ? flags 0x0000 # ATAPI unknown
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# Alchemy On-chip Programmable Serial Controllers
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aupsc0 at aubus0 addr 0x11a00000
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aupsc1 at aubus0 addr 0x11b00000
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aupsc2 at aubus0 addr 0x10a00000
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aupsc3 at aubus0 addr 0x10b00000
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# Serial Peripheral Interface
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auspi0 at aupsc0
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spi0 at auspi0
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tmp121temp* at spi0 slave 0
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#ausmbus0 at aupsc2
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#iic0 at ausmbus0
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