Finalize import of the Atheros HAL 0.9.9.13, bringing ath(4)
up-to-date where the HAL API changed.
This commit is contained in:
dyoung
parent
6f9ff5e059
commit
110ceded85
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@ -33,7 +33,7 @@
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGES.
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*
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* $Id: athhal-elf-o.uue,v 1.1.1.2 2004/07/19 23:51:18 dyoung Exp $
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* $Id: athhal-elf-o.uue,v 1.2 2004/07/28 08:57:40 dyoung Exp $
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*/
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#define ATH_HAL_VERSION "0.9.9.13"
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begin 644 hal.o
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@ -4,7 +4,7 @@ copyright does _NOT_ contain a "or GPL" clause and does _NOT_ permit
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redistribution with changes.
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/*-
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* Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting, Atheros
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* Copyright (c) 2002-2004 Sam Leffler, Errno Consulting, Atheros
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* Communications, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms are permitted
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@ -39,5 +39,5 @@ redistribution with changes.
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* SUCH DAMAGES.
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*
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* $NetBSD$
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* $Id: COPYRIGHT,v 1.2 2003/06/25 04:50:21 sam Exp $
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* $Id: COPYRIGHT,v 1.2 2004/05/15 22:26:24 samleffler Exp $
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*/
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@ -1,5 +1,5 @@
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$NetBSD$
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$Id: README,v 1.2 2003/07/02 01:55:27 sam Exp $
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$Id: README,v 1.2 2004/05/15 22:26:25 samleffler Exp $
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WARNING: THIS IS A BETA DISTRIBUTION. THIS SOFTWARE HAS KNOWN PROBLEMS AND
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@ -10,8 +10,8 @@ WARNING: USE AT YOUR OWN RISK!
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Atheros Hardware Access Layer (HAL)
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===================================
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* Copyright (c) 2002, 2003 Sam Leffler.
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* Copyright (c) 2002, 2003 Atheros Communications, Inc.
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* Copyright (c) 2002-2004 Sam Leffler.
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* Copyright (c) 2002-2004 Atheros Communications, Inc.
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* All rights reserved.
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Read the file COPYRIGHT for the complete copyright.
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@ -34,7 +34,8 @@
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGES.
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*
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* $Id: ah.h,v 1.1.1.5 2004/01/12 20:29:53 samleffler Exp $
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* $NetBSD$
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* $Id: ah.h,v 1.3 2004/06/09 16:33:48 samleffler Exp $
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*/
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#ifndef _ATH_AH_H_
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@ -107,6 +108,13 @@ typedef enum {
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AH_TRUE = 1,
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} HAL_BOOL;
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typedef enum {
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HAL_CAP_REG_DMN = 0, /* current regulatory domain */
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HAL_CAP_CIPHER = 1, /* hardware supports cipher */
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HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */
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HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
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} HAL_CAPABILITY_TYPE;
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/*
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* "States" for setting the LED. These correspond to
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* the possible 802.11 operational states and there may
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@ -137,6 +145,48 @@ typedef enum {
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#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
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/*
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* Transmit queue subtype. These map directly to
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* WME Access Categories (except for UPSD). Refer
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* to Table 5 of the WME spec.
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*/
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typedef enum {
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HAL_WME_AC_BK = 0, /* background access category */
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HAL_WME_AC_BE = 1, /* best effort access category*/
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HAL_WME_AC_VI = 2, /* video access category */
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HAL_WME_AC_VO = 3, /* voice access category */
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HAL_WME_UPSD = 4, /* uplink power save */
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} HAL_TX_QUEUE_SUBTYPE;
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/*
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* Transmit queue flags that control various
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* operational parameters.
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*/
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typedef enum {
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TXQ_FLAG_TXINT_ENABLE = 0x0001, /* TXOK,TXERR Interrupts */
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TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, /* TXDESC Interrupts */
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TXQ_FLAG_BACKOFF_DISABLE = 0x0004, /* disable Post Backoff */
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TXQ_FLAG_COMPRESSION_ENABLE = 0x0008, /* compression enabled */
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TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0010, /* enable ready time
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expiry policy */
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TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0020, /* enable backoff while
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sending fragment burst*/
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} HAL_TX_QUEUE_FLAGS;
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typedef struct {
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u_int32_t tqi_ver; /* hal TXQ version */
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HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */
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HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */
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u_int32_t tqi_priority;
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u_int32_t tqi_aifs; /* AIFS shift */
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int32_t tqi_cwmin; /* cwMin shift */
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int32_t tqi_cwmax; /* cwMax shift */
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u_int32_t tqi_cbrPeriod;
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u_int32_t tqi_cbrOverflowLimit;
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u_int32_t tqi_burstTime;
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u_int32_t tqi_readyTime;
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} HAL_TXQ_INFO;
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/*
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* Transmit packet types. This belongs in ah_desc.h, but
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* is here so we can give a proper type to various parameters
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@ -242,6 +292,7 @@ typedef struct {
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#define CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */
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#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */
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#define CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */
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#define CHANNEL_XR 0x0800 /* XR channel */
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#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
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#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
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@ -252,6 +303,8 @@ typedef struct {
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#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
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#endif
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#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
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#define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
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#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
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#define CHANNEL_ALL \
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(CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_5GHZ|CHANNEL_2GHZ|CHANNEL_TURBO)
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#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO)
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@ -282,6 +335,7 @@ enum {
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#else
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HAL_MODE_11G = 0x008,
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#endif
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HAL_MODE_108G = 0x020,
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HAL_MODE_ALL = 0xfff
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};
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@ -321,14 +375,22 @@ typedef enum {
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} HAL_OPMODE;
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typedef struct {
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int wk_len;
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u_int8_t wk_key[16]; /* XXX big enough for WEP */
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u_int8_t kv_type; /* one of HAL_CIPHER */
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u_int8_t kv_pad;
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u_int16_t kv_len; /* length in bits */
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u_int8_t kv_val[16]; /* enough for 128-bit keys */
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u_int8_t kv_mic[8]; /* TKIP MIC key */
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} HAL_KEYVAL;
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typedef enum {
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HAL_CIPHER_WEP = 0,
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HAL_CIPHER_AES_CCM = 1,
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HAL_CIPHER_CKIP = 2
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HAL_CIPHER_AES_OCB = 1,
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HAL_CIPHER_AES_CCM = 2,
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HAL_CIPHER_CKIP = 3,
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HAL_CIPHER_TKIP = 4,
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HAL_CIPHER_CLR = 5, /* no encryption */
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HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */
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} HAL_CIPHER;
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enum {
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@ -337,12 +399,17 @@ enum {
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};
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/*
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* Per-station beacon timer state.
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* Per-station beacon timer state. Note that the specified
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* beacon interval (given in TU's) can also include flags
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* to force a TSF reset and to enable the beacon xmit logic.
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*/
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typedef struct {
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u_int32_t bs_nexttbtt; /* next beacon in TU */
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u_int32_t bs_nextdtim; /* next DTIM in TU */
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u_int16_t bs_intval; /* beacon interval/period */
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u_int32_t bs_intval; /* beacon interval+flags */
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#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
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#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
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#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
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u_int8_t bs_dtimperiod;
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u_int8_t bs_cfpperiod; /* # of DTIMs between CFPs */
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u_int16_t bs_cfpmaxduration; /* max CFP duration in TU */
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@ -367,7 +434,7 @@ struct ath_desc;
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struct ath_hal {
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u_int32_t ah_magic; /* consistency check magic number */
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u_int32_t ah_abi; /* HAL ABI version */
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#define HAL_ABI_VERSION 0x04010701 /* YYMMDDnn */
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#define HAL_ABI_VERSION 0x04050400 /* YYMMDDnn */
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u_int16_t ah_devid; /* PCI device ID */
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u_int16_t ah_subvendorid; /* PCI subvendor ID */
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HAL_SOFTC ah_sc; /* back pointer to driver/os state */
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@ -388,17 +455,20 @@ struct ath_hal {
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HAL_BOOL (*ah_reset)(struct ath_hal *, HAL_OPMODE,
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HAL_CHANNEL *, HAL_BOOL bChannelChange,
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HAL_STATUS *status);
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HAL_BOOL (*ah_phyDisable)(struct ath_hal *);
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void (*ah_setPCUConfig)(struct ath_hal *);
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HAL_BOOL (*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *);
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/* Transmit functions */
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HAL_BOOL (*ah_updateTxTrigLevel)(struct ath_hal*,
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HAL_BOOL incTrigLevel);
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int (*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE type,
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HAL_BOOL irq);
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int (*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
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const HAL_TXQ_INFO *qInfo);
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HAL_BOOL (*ah_setTxQueueProps)(struct ath_hal *, int q,
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const HAL_TXQ_INFO *qInfo);
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HAL_BOOL (*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
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HAL_BOOL (*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
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u_int32_t (*ah_getTxDP)(struct ath_hal*, u_int);
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u_int32_t (*ah_getTxDP)(struct ath_hal*, u_int);
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HAL_BOOL (*ah_setTxDP)(struct ath_hal*, u_int, u_int32_t txdp);
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HAL_BOOL (*ah_startTxDma)(struct ath_hal*, u_int);
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HAL_BOOL (*ah_stopTxDma)(struct ath_hal*, u_int);
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@ -417,6 +487,12 @@ struct ath_hal {
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HAL_BOOL lastSeg);
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HAL_STATUS (*ah_procTxDesc)(struct ath_hal *, struct ath_desc *);
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HAL_BOOL (*ah_hasVEOL)(struct ath_hal *);
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/* NB: experimental, may go away */
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HAL_BOOL (*ah_updateTxDesc)(struct ath_hal *, struct ath_desc *,
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u_int txRate0, u_int txTries0,
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u_int txRate1, u_int txTries1,
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u_int txRate2, u_int txTries2,
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u_int txRate3, u_int txTries3);
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/* Receive Functions */
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u_int32_t (*ah_getRxDP)(struct ath_hal*);
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@ -440,11 +516,17 @@ struct ath_hal {
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void (*ah_rxMonitor)(struct ath_hal *);
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/* Misc Functions */
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void (*ah_dumpState)(struct ath_hal *);
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HAL_BOOL (*ah_getDiagState)(struct ath_hal *,
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int, void **, u_int *);
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HAL_STATUS (*ah_getCapability)(struct ath_hal *,
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HAL_CAPABILITY_TYPE, u_int32_t capability,
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u_int32_t *result);
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HAL_BOOL (*ah_setCapability)(struct ath_hal *,
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HAL_CAPABILITY_TYPE, u_int32_t capability,
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u_int32_t setting, HAL_STATUS *);
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HAL_BOOL (*ah_getDiagState)(struct ath_hal *, int request,
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const void *args, u_int32_t argsize,
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void **result, u_int32_t *resultsize);
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void (*ah_getMacAddress)(struct ath_hal *, u_int8_t *);
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HAL_BOOL (*ah_setMacAddress)(struct ath_hal *, const u_int8_t *);
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HAL_BOOL (*ah_setMacAddress)(struct ath_hal *, const u_int8_t*);
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HAL_BOOL (*ah_setRegulatoryDomain)(struct ath_hal*,
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u_int16_t, HAL_STATUS *);
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void (*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
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@ -460,17 +542,20 @@ struct ath_hal {
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u_int32_t (*ah_getTsf32)(struct ath_hal*);
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u_int64_t (*ah_getTsf64)(struct ath_hal*);
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void (*ah_resetTsf)(struct ath_hal*);
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u_int16_t (*ah_getRegDomain)(struct ath_hal*);
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HAL_BOOL (*ah_detectCardPresent)(struct ath_hal*);
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void (*ah_updateMibCounters)(struct ath_hal*, HAL_MIB_STATS*);
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HAL_BOOL (*ah_isHwCipherSupported)(struct ath_hal*, HAL_CIPHER);
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HAL_RFGAIN (*ah_getRfGain)(struct ath_hal*);
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#if 0
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u_int32_t (*ah_getCurRssi)(struct ath_hal*);
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u_int32_t (*ah_getDefAntenna)(struct ath_hal*);
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void (*ah_setDefAntenna)(struct ath_hal*, u_int32_t antenna);
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void (*ah_setDefAntenna)(struct ath_hal*, u_int32_t ant);
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#endif
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HAL_BOOL (*ah_setSlotTime)(struct ath_hal*, u_int);
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u_int (*ah_getSlotTime)(struct ath_hal*);
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HAL_BOOL (*ah_setAckTimeout)(struct ath_hal*, u_int);
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u_int (*ah_getAckTimeout)(struct ath_hal*);
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HAL_BOOL (*ah_setCTSTimeout)(struct ath_hal*, u_int);
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u_int (*ah_getCTSTimeout)(struct ath_hal*);
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/* Key Cache Functions */
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u_int32_t (*ah_getKeyCacheSize)(struct ath_hal*);
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@ -495,7 +580,7 @@ struct ath_hal {
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/* Beacon Management Functions */
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void (*ah_beaconInit)(struct ath_hal *,
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u_int32_t, u_int32_t);
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u_int32_t nexttbtt, u_int32_t intval);
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void (*ah_setStationBeaconTimers)(struct ath_hal*,
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const HAL_BEACON_STATE *, u_int32_t tsf,
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u_int32_t dtimCount, u_int32_t cfpCcount);
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@ -552,7 +637,7 @@ extern HAL_BOOL ath_hal_init_channels(struct ath_hal *,
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/*
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* Return bit mask of wireless modes supported by the hardware.
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*/
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extern u_int ath_hal_getwirelessmodes(struct ath_hal *ah, HAL_CTRY_CODE cc);
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extern u_int ath_hal_getwirelessmodes(struct ath_hal*, HAL_CTRY_CODE);
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/*
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* Return rate table for specified mode (11a, 11b, 11g, etc).
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@ -1,6 +1,6 @@
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/* $NetBSD$ */
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/*-
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* Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting, Atheros
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* Copyright (c) 2002-2004 Sam Leffler, Errno Consulting, Atheros
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* Communications, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms are permitted
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@ -34,7 +34,7 @@
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGES.
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*
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* $Id: ah_desc.h,v 1.11 2003/06/25 04:50:22 sam Exp $
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* $Id: ah_desc.h,v 1.2 2004/05/15 22:26:25 samleffler Exp $
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*/
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#ifndef _DEV_ATH_DESC_H
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@ -54,6 +54,7 @@ struct ath_tx_status {
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u_int16_t ts_tstamp; /* h/w assigned timestamp */
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u_int8_t ts_status; /* frame status, 0 => xmit ok */
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u_int8_t ts_rate; /* h/w transmit rate index */
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#define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */
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int8_t ts_rssi; /* tx ack RSSI */
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u_int8_t ts_shortretry; /* # short retries */
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u_int8_t ts_longretry; /* # long retries */
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@ -73,10 +74,17 @@ struct ath_tx_status {
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*
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* If rx_status is zero, then the frame was received ok;
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* otherwise the error information is indicated and rs_phyerr
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* contains a phy error code if HAL_RXERR_PHY is set.
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* contains a phy error code if HAL_RXERR_PHY is set. In general
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* the frame contents is undefined when an error occurred thought
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* for some errors (e.g. a decryption error), it may be meaningful.
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*
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* Note that the receive timestamp is expanded using the TSF to
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* a full 16 bits (regardless of what the h/w provides directly).
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*
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* rx_rssi is in units of dbm above the noise floor. This value
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* is measured during the preamble and PLCP; i.e. with the initial
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* 4us of detection. The noise floor is typically a consistent
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* -96dBm absolute power in a 20MHz channel.
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*/
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struct ath_rx_status {
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u_int16_t rs_datalen; /* rx frame length */
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@ -1,6 +1,6 @@
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/* $NetBSD$ */
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/*-
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* Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting, Atheros
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* Copyright (c) 2002-2004 Sam Leffler, Errno Consulting, Atheros
|
||||
* Communications, Inc. All rights reserved.
|
||||
*
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* Redistribution and use in source and binary forms are permitted
|
||||
|
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@ -34,7 +34,7 @@
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGES.
|
||||
*
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* $Id: ah_devid.h,v 1.7 2003/10/22 21:17:40 sam Exp $
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* $Id: ah_devid.h,v 1.4 2004/06/09 16:33:48 samleffler Exp $
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*/
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#ifndef _DEV_ATH_DEVID_H_
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@ -46,7 +46,8 @@
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* of 0x168c, but some vendors, in their infinite wisdom
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* do not follow this so we must handle them specially.
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*/
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#define ATHEROS_3COM_VENDOR_ID 0xa727 /* 3Com PCI vendor ID */
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#define ATHEROS_3COM_VENDOR_ID 0xa727 /* 3Com 3CRPAG175 vendor ID */
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#define ATHEROS_3COM2_VENDOR_ID 0x10b7 /* 3Com 3CRDAG675 vendor ID */
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/* AR5210 (for reference) */
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||||
#define AR5210_DEFAULT 0x1107 /* No eeprom HW default */
|
||||
|
|
@ -65,6 +66,9 @@
|
|||
#define AR5212_DEVID 0x0013 /* Final ar5212 devid */
|
||||
#define AR5212_FPGA 0xf013 /* Emulation board */
|
||||
#define AR5212_DEVID_IBM 0x1014 /* IBM minipci ID */
|
||||
#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
|
||||
#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
|
||||
#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
|
||||
|
||||
#define AR_SUBVENDOR_ID_NOG 0x0e11 /* No 11G subvendor ID */
|
||||
#endif /* _DEV_ATH_DEVID_H */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*-
|
||||
* Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting, Atheros
|
||||
* Copyright (c) 2002-2004 Sam Leffler, Errno Consulting, Atheros
|
||||
* Communications, Inc. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms are permitted
|
||||
|
|
@ -34,7 +34,7 @@
|
|||
* SUCH DAMAGES.
|
||||
*
|
||||
* $NetBSD$
|
||||
* $Id: ah_osdep.c,v 1.28 2003/11/01 01:43:21 sam Exp $
|
||||
* $Id: ah_osdep.c,v 1.3 2004/06/09 16:33:48 samleffler Exp $
|
||||
*/
|
||||
#ifdef __FreeBSD__
|
||||
#include "opt_ah.h"
|
||||
|
|
@ -91,13 +91,9 @@ extern void ath_hal_free(void *);
|
|||
extern void ath_hal_assert_failed(const char* filename,
|
||||
int lineno, const char* msg);
|
||||
#endif
|
||||
#ifdef AH_DEBUG
|
||||
extern void HALDEBUG(struct ath_hal *ah, const char* fmt, ...);
|
||||
extern void HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...);
|
||||
#endif /* AH_DEBUG */
|
||||
|
||||
#ifdef AH_DEBUG
|
||||
static int ath_hal_debug = 0; /* XXX */
|
||||
static int ath_hal_debug = 0;
|
||||
#endif /* AH_DEBUG */
|
||||
|
||||
#ifdef __FreeBSD__
|
||||
|
|
@ -171,17 +167,9 @@ err:
|
|||
}
|
||||
#endif /* __NetBSD__ */
|
||||
|
||||
void*
|
||||
ath_hal_malloc(size_t size)
|
||||
{
|
||||
return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
|
||||
}
|
||||
|
||||
void
|
||||
ath_hal_free(void* p)
|
||||
{
|
||||
return free(p, M_DEVBUF);
|
||||
}
|
||||
/*
|
||||
* Print/log message support.
|
||||
*/
|
||||
|
||||
void
|
||||
ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap)
|
||||
|
|
@ -198,188 +186,25 @@ ath_hal_printf(struct ath_hal *ah, const char* fmt, ...)
|
|||
va_end(ap);
|
||||
}
|
||||
|
||||
/*
|
||||
* Format an Ethernet MAC for printing.
|
||||
*/
|
||||
const char*
|
||||
ath_hal_ether_sprintf(const u_int8_t *mac)
|
||||
{
|
||||
return ether_sprintf(mac);
|
||||
}
|
||||
|
||||
#ifdef AH_DEBUG
|
||||
#ifdef AH_ASSERT
|
||||
void
|
||||
HALDEBUG(struct ath_hal *ah, const char* fmt, ...)
|
||||
ath_hal_assert_failed(const char* filename, int lineno, const char *msg)
|
||||
{
|
||||
if (ath_hal_debug) {
|
||||
va_list ap;
|
||||
va_start(ap, fmt);
|
||||
ath_hal_vprintf(ah, fmt, ap);
|
||||
va_end(ap);
|
||||
}
|
||||
printf("Atheros HAL assertion failure: %s: line %u: %s\n",
|
||||
filename, lineno, msg);
|
||||
panic("ath_hal_assert");
|
||||
}
|
||||
#endif /* AH_ASSERT */
|
||||
|
||||
void
|
||||
HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...)
|
||||
{
|
||||
if (ath_hal_debug >= level) {
|
||||
va_list ap;
|
||||
va_start(ap, fmt);
|
||||
ath_hal_vprintf(ah, fmt, ap);
|
||||
va_end(ap);
|
||||
}
|
||||
}
|
||||
#endif /* AH_DEBUG */
|
||||
|
||||
#ifdef AH_DEBUG_ALQ
|
||||
/*
|
||||
* ALQ register tracing support.
|
||||
*
|
||||
* Setting hw.ath.hal.alq=1 enables tracing of all register reads and
|
||||
* writes to the file /tmp/ath_hal.log. The file format is a simple
|
||||
* fixed-size array of records. When done logging set hw.ath.hal.alq=0
|
||||
* and then decode the file with the arcode program (that is part of the
|
||||
* HAL). If you start+stop tracing the data will be appended to an
|
||||
* existing file.
|
||||
*
|
||||
* NB: doesn't handle multiple devices properly; only one DEVICE record
|
||||
* is emitted and the different devices are not identified.
|
||||
*/
|
||||
#include <sys/alq.h>
|
||||
#include <sys/pcpu.h>
|
||||
#include <contrib/dev/ath/ah_decode.h>
|
||||
|
||||
static struct alq *ath_hal_alq;
|
||||
static int ath_hal_alq_emitdev; /* need to emit DEVICE record */
|
||||
static u_int ath_hal_alq_lost; /* count of lost records */
|
||||
static const char *ath_hal_logfile = "/tmp/ath_hal.log";
|
||||
static u_int ath_hal_alq_qsize = 64*1024;
|
||||
|
||||
static int
|
||||
ath_hal_setlogging(int enable)
|
||||
{
|
||||
int error;
|
||||
|
||||
if (enable) {
|
||||
error = suser(curthread);
|
||||
if (error == 0) {
|
||||
error = alq_open(&ath_hal_alq, ath_hal_logfile,
|
||||
curthread->td_ucred,
|
||||
sizeof (struct athregrec), ath_hal_alq_qsize);
|
||||
ath_hal_alq_lost = 0;
|
||||
ath_hal_alq_emitdev = 1;
|
||||
printf("ath_hal: logging to %s enabled\n",
|
||||
ath_hal_logfile);
|
||||
}
|
||||
} else {
|
||||
if (ath_hal_alq)
|
||||
alq_close(ath_hal_alq);
|
||||
ath_hal_alq = NULL;
|
||||
printf("ath_hal: logging disabled\n");
|
||||
error = 0;
|
||||
}
|
||||
return (error);
|
||||
}
|
||||
|
||||
static int
|
||||
sysctl_hw_ath_hal_log(SYSCTL_HANDLER_ARGS)
|
||||
{
|
||||
int error, enable;
|
||||
|
||||
enable = (ath_hal_alq != NULL);
|
||||
error = sysctl_handle_int(oidp, &enable, 0, req);
|
||||
if (error || !req->newptr)
|
||||
return (error);
|
||||
else
|
||||
return (ath_hal_setlogging(enable));
|
||||
}
|
||||
SYSCTL_PROC(_hw_ath_hal, OID_AUTO, alq, CTLTYPE_INT|CTLFLAG_RW,
|
||||
0, 0, sysctl_hw_ath_hal_log, "I", "Enable HAL register logging");
|
||||
SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_size, CTLFLAG_RW,
|
||||
&ath_hal_alq_qsize, 0, "In-memory log size (#records)");
|
||||
SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_lost, CTLFLAG_RW,
|
||||
&ath_hal_alq_lost, 0, "Register operations not logged");
|
||||
|
||||
static struct ale *
|
||||
ath_hal_alq_get(struct ath_hal *ah)
|
||||
{
|
||||
struct ale *ale;
|
||||
|
||||
if (ath_hal_alq_emitdev) {
|
||||
ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
|
||||
if (ale) {
|
||||
struct athregrec *r =
|
||||
(struct athregrec *) ale->ae_data;
|
||||
r->op = OP_DEVICE;
|
||||
r->reg = 0;
|
||||
r->val = ah->ah_devid;
|
||||
alq_post(ath_hal_alq, ale);
|
||||
ath_hal_alq_emitdev = 0;
|
||||
} else
|
||||
ath_hal_alq_lost++;
|
||||
}
|
||||
ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
|
||||
if (!ale)
|
||||
ath_hal_alq_lost++;
|
||||
return ale;
|
||||
}
|
||||
|
||||
void
|
||||
ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
|
||||
{
|
||||
if (ath_hal_alq) {
|
||||
struct ale *ale = ath_hal_alq_get(ah);
|
||||
if (ale) {
|
||||
struct athregrec *r = (struct athregrec *) ale->ae_data;
|
||||
r->op = OP_WRITE;
|
||||
r->reg = reg;
|
||||
r->val = val;
|
||||
alq_post(ath_hal_alq, ale);
|
||||
}
|
||||
}
|
||||
#if _BYTE_ORDER == _BIG_ENDIAN
|
||||
if (reg >= 0x4000 && reg < 0x5000)
|
||||
bus_space_write_4(ah->ah_st, ah->ah_sh, reg, htole32(val));
|
||||
else
|
||||
#endif
|
||||
bus_space_write_4(ah->ah_st, ah->ah_sh, reg, val);
|
||||
}
|
||||
|
||||
u_int32_t
|
||||
ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
|
||||
{
|
||||
u_int32_t val;
|
||||
|
||||
val = bus_space_read_4(ah->ah_st, ah->ah_sh, reg);
|
||||
#if _BYTE_ORDER == _BIG_ENDIAN
|
||||
if (reg >= 0x4000 && reg < 0x5000)
|
||||
val = le32toh(val);
|
||||
#endif
|
||||
if (ath_hal_alq) {
|
||||
struct ale *ale = ath_hal_alq_get(ah);
|
||||
if (ale) {
|
||||
struct athregrec *r = (struct athregrec *) ale->ae_data;
|
||||
r->op = OP_READ;
|
||||
r->reg = reg;
|
||||
r->val = val;
|
||||
alq_post(ath_hal_alq, ale);
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
void
|
||||
OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
|
||||
{
|
||||
if (ath_hal_alq) {
|
||||
struct ale *ale = ath_hal_alq_get(ah);
|
||||
if (ale) {
|
||||
struct athregrec *r = (struct athregrec *) ale->ae_data;
|
||||
r->op = OP_MARK;
|
||||
r->reg = id;
|
||||
r->val = v;
|
||||
alq_post(ath_hal_alq, ale);
|
||||
}
|
||||
}
|
||||
}
|
||||
#elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
|
||||
/*
|
||||
* Memory-mapped device register read/write. These are here
|
||||
* as routines when debugging support is enabled and/or when
|
||||
|
|
@ -390,7 +215,7 @@ OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
|
|||
* NB: see the comments in ah_osdep.h about byte-swapping register
|
||||
* reads and writes to understand what's going on below.
|
||||
*/
|
||||
|
||||
#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
|
||||
void
|
||||
ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
|
||||
{
|
||||
|
|
@ -416,15 +241,30 @@ ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
|
|||
}
|
||||
#endif /* AH_DEBUG || AH_REGOPS_FUNC */
|
||||
|
||||
#ifdef AH_ASSERT
|
||||
#ifdef AH_DEBUG
|
||||
void
|
||||
ath_hal_assert_failed(const char* filename, int lineno, const char *msg)
|
||||
HALDEBUG(struct ath_hal *ah, const char* fmt, ...)
|
||||
{
|
||||
printf("Atheros HAL assertion failure: %s: line %u: %s\n",
|
||||
filename, lineno, msg);
|
||||
panic("ath_hal_assert");
|
||||
if (ath_hal_debug) {
|
||||
va_list ap;
|
||||
va_start(ap, fmt);
|
||||
ath_hal_vprintf(ah, fmt, ap);
|
||||
va_end(ap);
|
||||
}
|
||||
}
|
||||
#endif /* AH_ASSERT */
|
||||
|
||||
|
||||
void
|
||||
HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...)
|
||||
{
|
||||
if (ath_hal_debug >= level) {
|
||||
va_list ap;
|
||||
va_start(ap, fmt);
|
||||
ath_hal_vprintf(ah, fmt, ap);
|
||||
va_end(ap);
|
||||
}
|
||||
}
|
||||
#endif /* AH_DEBUG */
|
||||
|
||||
/*
|
||||
* Delay n microseconds.
|
||||
|
|
@ -447,6 +287,28 @@ ath_hal_getuptime(struct ath_hal *ah)
|
|||
return (tv.tv_sec * 1000) + (tv.tv_usec / 1000);
|
||||
}
|
||||
|
||||
/*
|
||||
* Allocate/free memory.
|
||||
*/
|
||||
|
||||
void *
|
||||
ath_hal_malloc(size_t size)
|
||||
{
|
||||
return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
|
||||
}
|
||||
|
||||
void
|
||||
ath_hal_free(void* p)
|
||||
{
|
||||
free(p, M_DEVBUF);
|
||||
}
|
||||
|
||||
void *
|
||||
ath_hal_memcpy(void *dst, const void *src, size_t n)
|
||||
{
|
||||
return memcpy(dst, src, n);
|
||||
}
|
||||
|
||||
void
|
||||
bcopy(const void *src, void *dst, size_t len)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* $NetBSD$ */
|
||||
/*-
|
||||
* Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting, Atheros
|
||||
* Copyright (c) 2002-2004 Sam Leffler, Errno Consulting, Atheros
|
||||
* Communications, Inc. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms are permitted
|
||||
|
|
@ -34,7 +34,7 @@
|
|||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGES.
|
||||
*
|
||||
* $Id: ah_osdep.h,v 1.10 2003/11/01 01:21:31 sam Exp $
|
||||
* $Id: ah_osdep.h,v 1.1.1.7 2004/06/09 16:25:50 samleffler Exp $
|
||||
*/
|
||||
#ifndef _ATH_AH_OSDEP_H_
|
||||
#define _ATH_AH_OSDEP_H_
|
||||
|
|
@ -58,16 +58,22 @@ typedef bus_addr_t HAL_BUS_ADDR;
|
|||
extern void ath_hal_delay(int);
|
||||
#define OS_DELAY(_n) ath_hal_delay(_n)
|
||||
|
||||
#define OS_INLINE __inline
|
||||
#define OS_MEMZERO(_a, _size) bzero((_a), (_size))
|
||||
#define OS_MEMCPY(_dst, _src, _size) bcopy((_src), (_dst), (_size))
|
||||
#define OS_MACEQU(_a, _b) \
|
||||
(bcmp((_a), (_b), IEEE80211_ADDR_LEN) == 0)
|
||||
#define OS_MEMZERO(_a, _n) __builtin_memset((_a), 0, (_n))
|
||||
#define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n)
|
||||
extern void * ath_hal_memcpy(void *, const void *, size_t);
|
||||
|
||||
#define abs(_a) __builtin_abs(_a)
|
||||
|
||||
struct ath_hal;
|
||||
extern u_int32_t ath_hal_getuptime(struct ath_hal *);
|
||||
#define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah)
|
||||
|
||||
/*
|
||||
* Byte order/swapping support.
|
||||
*/
|
||||
#define AH_LITTLE_ENDIAN 1234
|
||||
#define AH_BIG_ENDIAN 4321
|
||||
|
||||
/*
|
||||
* Register read/write; we assume the registers will always
|
||||
* be memory-mapped. Note that register accesses are done
|
||||
|
|
@ -75,15 +81,7 @@ extern u_int32_t ath_hal_getuptime(struct ath_hal *);
|
|||
* (AH_DEBUG) or we are explicitly configured this way. The
|
||||
* latter is used on some platforms where the full i/o space
|
||||
* cannot be directly mapped.
|
||||
*/
|
||||
#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
|
||||
#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
|
||||
#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
|
||||
|
||||
extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
|
||||
extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
|
||||
#else
|
||||
/*
|
||||
*
|
||||
* The hardware registers are native little-endian byte order.
|
||||
* Big-endian hosts are handled by enabling hardware byte-swap
|
||||
* of register reads and writes at reset. But the PCI clock
|
||||
|
|
@ -92,11 +90,18 @@ extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
|
|||
* Most of this code is collapsed at compile time because the
|
||||
* register values are constants.
|
||||
*/
|
||||
#define AH_LITTLE_ENDIAN 1234
|
||||
#define AH_BIG_ENDIAN 4321
|
||||
#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
|
||||
/* use functions to do register operations */
|
||||
#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
|
||||
#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
|
||||
|
||||
#if _BYTE_ORDER == _BIG_ENDIAN
|
||||
#define OS_REG_WRITE(_ah, _reg, _val) do { \
|
||||
extern void ath_hal_reg_write(struct ath_hal *ah,
|
||||
u_int reg, u_int32_t val);
|
||||
extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
|
||||
#else
|
||||
/* inline register operations */
|
||||
#if AH_BYTE_ORDER == AH_BIG_ENDIAN
|
||||
#define OS_REG_WRITE(_ah, _reg, _val) do { \
|
||||
if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \
|
||||
bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \
|
||||
(_reg), htole32(_val)); \
|
||||
|
|
@ -104,23 +109,20 @@ extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
|
|||
bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \
|
||||
(_reg), (_val)); \
|
||||
} while (0)
|
||||
#define OS_REG_READ(_ah, _reg) \
|
||||
#define OS_REG_READ(_ah, _reg) \
|
||||
(((_reg) >= 0x4000 && (_reg) < 0x5000) ? \
|
||||
le32toh(bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, \
|
||||
(_reg))) : \
|
||||
bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
|
||||
#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
|
||||
#define OS_REG_WRITE(_ah, _reg, _val) \
|
||||
#else /* AH_LITTLE_ENDIAN */
|
||||
#define OS_REG_WRITE(_ah, _reg, _val) \
|
||||
bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, (_reg), (_val))
|
||||
#define OS_REG_READ(_ah, _reg) \
|
||||
#define OS_REG_READ(_ah, _reg) \
|
||||
((u_int32_t) bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
|
||||
#endif /* _BYTE_ORDER */
|
||||
#endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
|
||||
|
||||
#ifdef AH_DEBUG_ALQ
|
||||
extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
|
||||
#else
|
||||
#endif /* AH_BYTE_ORDER */
|
||||
#endif /* AH_DEBUG || AH_REGFUNC */
|
||||
#define OS_MARK(_ah, _id, _v)
|
||||
#endif
|
||||
|
||||
extern void ath_hal_detach(struct ath_hal *);
|
||||
|
||||
#endif /* _ATH_AH_OSDEP_H_ */
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* $NetBSD$ */
|
||||
/*-
|
||||
* Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting
|
||||
* Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -34,6 +34,6 @@
|
|||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES.
|
||||
*
|
||||
* $Id: version.h,v 1.27 2003/12/07 02:20:39 sam Exp $
|
||||
* $Id: version.h,v 1.1.1.10 2004/07/13 19:13:39 samleffler Exp $
|
||||
*/
|
||||
#define ATH_HAL_VERSION "0.9.6.3"
|
||||
#define ATH_HAL_VERSION "0.9.9.13"
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: ath.c,v 1.30 2004/07/23 10:15:13 mycroft Exp $ */
|
||||
/* $NetBSD: ath.c,v 1.31 2004/07/28 08:57:40 dyoung Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
|
||||
|
|
@ -41,7 +41,7 @@
|
|||
__FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.54 2004/04/05 04:42:42 sam Exp $");
|
||||
#endif
|
||||
#ifdef __NetBSD__
|
||||
__KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.30 2004/07/23 10:15:13 mycroft Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.31 2004/07/28 08:57:40 dyoung Exp $");
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -431,6 +431,7 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
|
|||
struct ifnet *ifp = &ic->ic_if;
|
||||
struct ath_hal *ah;
|
||||
HAL_STATUS status;
|
||||
HAL_TXQ_INFO qinfo;
|
||||
int error = 0;
|
||||
|
||||
DPRINTF(ATH_DEBUG_ANY, ("%s: devid 0x%x\n", __func__, devid));
|
||||
|
|
@ -483,8 +484,8 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
|
|||
* Copy these back; they are set as a side effect
|
||||
* of constructing the channel list.
|
||||
*/
|
||||
ath_regdomain = ath_hal_getregdomain(ah);
|
||||
ath_countrycode = ath_hal_getcountrycode(ah);
|
||||
ath_hal_getregdomain(ah, &ath_regdomain);
|
||||
ath_hal_getcountrycode(ah, &ath_countrycode);
|
||||
|
||||
/*
|
||||
* Setup rate tables for all potential media types.
|
||||
|
|
@ -520,23 +521,20 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
|
|||
* allocate more tx queues for splitting management
|
||||
* frames and for QOS support.
|
||||
*/
|
||||
sc->sc_txhalq = ath_hal_setuptxqueue(ah,
|
||||
HAL_TX_QUEUE_DATA,
|
||||
AH_TRUE /* enable interrupts */
|
||||
);
|
||||
if (sc->sc_txhalq == (u_int) -1) {
|
||||
if_printf(ifp, "unable to setup a data xmit queue!\n");
|
||||
goto bad2;
|
||||
}
|
||||
sc->sc_bhalq = ath_hal_setuptxqueue(ah,
|
||||
HAL_TX_QUEUE_BEACON,
|
||||
AH_TRUE /* enable interrupts */
|
||||
);
|
||||
sc->sc_bhalq = ath_hal_setuptxqueue(ah,HAL_TX_QUEUE_BEACON,NULL);
|
||||
if (sc->sc_bhalq == (u_int) -1) {
|
||||
if_printf(ifp, "unable to setup a beacon xmit queue!\n");
|
||||
goto bad2;
|
||||
}
|
||||
|
||||
memset(&qinfo, 0, sizeof(qinfo));
|
||||
qinfo.tqi_subtype = HAL_WME_AC_BE;
|
||||
sc->sc_txhalq = ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_DATA, &qinfo);
|
||||
if (sc->sc_txhalq == (u_int) -1) {
|
||||
if_printf(ifp, "unable to setup a data xmit queue!\n");
|
||||
goto bad2;
|
||||
}
|
||||
|
||||
ifp->if_softc = sc;
|
||||
ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
|
||||
ifp->if_start = ath_start;
|
||||
|
|
@ -788,13 +786,6 @@ ath_intr1(struct ath_softc *sc)
|
|||
}
|
||||
ath_hal_getisr(ah, &status); /* NB: clears ISR too */
|
||||
DPRINTF(ATH_DEBUG_INTR, ("%s: status 0x%x\n", __func__, status));
|
||||
#ifdef AR_DEBUG
|
||||
if (ath_debug &&
|
||||
(status & (HAL_INT_FATAL|HAL_INT_RXORN|HAL_INT_BMISS))) {
|
||||
if_printf(ifp, "ath_intr: status 0x%x\n", status);
|
||||
ath_hal_dumpstate(ah);
|
||||
}
|
||||
#endif /* AR_DEBUG */
|
||||
status &= sc->sc_imask; /* discard unasked for bits */
|
||||
if (status & HAL_INT_FATAL) {
|
||||
sc->sc_stats.ast_hardware++;
|
||||
|
|
@ -1246,10 +1237,6 @@ ath_watchdog(struct ifnet *ifp)
|
|||
if (sc->sc_tx_timer) {
|
||||
if (--sc->sc_tx_timer == 0) {
|
||||
if_printf(ifp, "device timeout\n");
|
||||
#ifdef AR_DEBUG
|
||||
if (ath_debug & ATH_DEBUG_WATCHDOG)
|
||||
ath_hal_dumpstate(sc->sc_ah);
|
||||
#endif /* AR_DEBUG */
|
||||
ath_reset(sc);
|
||||
ifp->if_oerrors++;
|
||||
sc->sc_stats.ast_watchdog++;
|
||||
|
|
@ -1332,6 +1319,7 @@ ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
|
|||
ifr->ifr_data, sizeof (sc->sc_stats));
|
||||
break;
|
||||
case SIOCGATHDIAG: {
|
||||
#if 0 /* XXX punt */
|
||||
struct ath_diag *ad = (struct ath_diag *)data;
|
||||
struct ath_hal *ah = sc->sc_ah;
|
||||
void *data;
|
||||
|
|
@ -1344,6 +1332,9 @@ ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
|
|||
error = copyout(data, ad->ad_data, ad->ad_size);
|
||||
} else
|
||||
error = EINVAL;
|
||||
#else
|
||||
error = EINVAL;
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
default:
|
||||
|
|
@ -1769,19 +1760,25 @@ ath_beacon_config(struct ath_softc *sc)
|
|||
struct ath_hal *ah = sc->sc_ah;
|
||||
struct ieee80211com *ic = &sc->sc_ic;
|
||||
struct ieee80211_node *ni = ic->ic_bss;
|
||||
u_int32_t nexttbtt;
|
||||
u_int32_t nexttbtt, intval;
|
||||
|
||||
nexttbtt = (LE_READ_4(ni->ni_tstamp + 4) << 22) |
|
||||
(LE_READ_4(ni->ni_tstamp) >> 10);
|
||||
DPRINTF(ATH_DEBUG_BEACON, ("%s: nexttbtt=%u\n", __func__, nexttbtt));
|
||||
nexttbtt += ni->ni_intval;
|
||||
intval = ni->ni_intval & HAL_BEACON_PERIOD;
|
||||
if (ic->ic_opmode == IEEE80211_M_STA) {
|
||||
HAL_BEACON_STATE bs;
|
||||
u_int32_t bmisstime;
|
||||
|
||||
/* NB: no PCF support right now */
|
||||
memset(&bs, 0, sizeof(bs));
|
||||
bs.bs_intval = ni->ni_intval;
|
||||
/*
|
||||
* Reset our tsf so the hardware will update the
|
||||
* tsf register to reflect timestamps found in
|
||||
* received beacons.
|
||||
*/
|
||||
bs.bs_intval = intval | HAL_BEACON_RESET_TSF;
|
||||
bs.bs_nexttbtt = nexttbtt;
|
||||
bs.bs_dtimperiod = bs.bs_intval;
|
||||
bs.bs_nextdtim = nexttbtt;
|
||||
|
|
@ -1824,12 +1821,6 @@ ath_beacon_config(struct ath_softc *sc)
|
|||
, bs.bs_sleepduration
|
||||
));
|
||||
ath_hal_intrset(ah, 0);
|
||||
/*
|
||||
* Reset our tsf so the hardware will update the
|
||||
* tsf register to reflect timestamps found in
|
||||
* received beacons.
|
||||
*/
|
||||
ath_hal_resettsf(ah);
|
||||
ath_hal_beacontimers(ah, &bs, 0/*XXX*/, 0, 0);
|
||||
sc->sc_imask |= HAL_INT_BMISS;
|
||||
ath_hal_intrset(ah, sc->sc_imask);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: athioctl.h,v 1.5 2004/04/30 23:59:55 dyoung Exp $ */
|
||||
/* $NetBSD: athioctl.h,v 1.6 2004/07/28 08:57:40 dyoung Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
|
||||
|
|
@ -97,12 +97,19 @@ struct ath_stats {
|
|||
#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
|
||||
|
||||
struct ath_diag {
|
||||
char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
|
||||
u_int ad_id;
|
||||
caddr_t ad_data;
|
||||
u_int ad_size;
|
||||
char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
|
||||
u_int16_t ad_id;
|
||||
#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */
|
||||
#define ATH_DIAG_IN 0x4000 /* copy in parameters */
|
||||
#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */
|
||||
#define ATH_DIAG_ID 0x0fff
|
||||
u_int16_t ad_in_size; /* pack to fit, yech */
|
||||
caddr_t ad_in_data;
|
||||
caddr_t ad_out_data;
|
||||
u_int ad_out_size;
|
||||
|
||||
};
|
||||
|
||||
#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: athvar.h,v 1.8 2004/04/30 23:59:52 dyoung Exp $ */
|
||||
/* $NetBSD: athvar.h,v 1.9 2004/07/28 08:57:40 dyoung Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
|
||||
|
|
@ -262,13 +262,10 @@ int ath_intr(void *);
|
|||
((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
|
||||
#define ath_hal_getratetable(_ah, _mode) \
|
||||
((*(_ah)->ah_getRateTable)((_ah), (_mode)))
|
||||
#define ath_hal_getregdomain(_ah) \
|
||||
((*(_ah)->ah_getRegDomain)((_ah)))
|
||||
#define ath_hal_getcountrycode(_ah) (_ah)->ah_countryCode
|
||||
#define ath_hal_getmac(_ah, _mac) \
|
||||
((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
|
||||
#define ath_hal_detach(_ah) \
|
||||
((*(_ah)->ah_detach)((_ah)))
|
||||
#define ath_hal_setmac(_ah, _mac) \
|
||||
((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
|
||||
#define ath_hal_intrset(_ah, _mask) \
|
||||
((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
|
||||
#define ath_hal_intrget(_ah) \
|
||||
|
|
@ -330,6 +327,28 @@ int ath_intr(void *);
|
|||
(_dc), (_cc)))
|
||||
#define ath_hal_setassocid(_ah, _bss, _associd) \
|
||||
((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd), 0))
|
||||
#define ath_hal_getcapability(_ah, _cap, _param, _result) \
|
||||
((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
|
||||
#define ath_hal_getregdomain(_ah, _prd) \
|
||||
ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd))
|
||||
#define ath_hal_getcountrycode(_ah, _pcc) \
|
||||
(*(_pcc) = (_ah)->ah_countryCode)
|
||||
#define ath_hal_detach(_ah) \
|
||||
((*(_ah)->ah_detach)(_ah))
|
||||
|
||||
#ifdef SOFTLED
|
||||
#define ath_hal_gpioCfgOutput(_ah, _gpio) \
|
||||
((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio)))
|
||||
#define ath_hal_gpioCfgInput(_ah, _gpio) \
|
||||
((*(_ah)->ah_gpioCfgInput)((_ah), (_gpio)))
|
||||
#define ath_hal_gpioGet(_ah, _gpio) \
|
||||
((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
|
||||
#define ath_hal_gpioSet(_ah, _gpio, _b) \
|
||||
((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
|
||||
#define ath_hal_gpioSetIntr(_ah, _gpioSel, _b) \
|
||||
((*(_ah)->ah_gpioSetIntr)((_ah), (_sel), (_b)))
|
||||
#endif
|
||||
|
||||
#define ath_hal_setopmode(_ah) \
|
||||
((*(_ah)->ah_setPCUConfig)((_ah)))
|
||||
#define ath_hal_stoptxdma(_ah, _qnum) \
|
||||
|
|
@ -340,12 +359,16 @@ int ath_intr(void *);
|
|||
((*(_ah)->ah_startPcuReceive)((_ah)))
|
||||
#define ath_hal_stopdmarecv(_ah) \
|
||||
((*(_ah)->ah_stopDmaReceive)((_ah)))
|
||||
#define ath_hal_dumpstate(_ah) \
|
||||
((*(_ah)->ah_dumpState)((_ah)))
|
||||
#define ath_hal_getdiagstate(_ah, _id, _data, _size) \
|
||||
((*(_ah)->ah_getDiagState)((_ah), (_id), (_data), (_size)))
|
||||
#define ath_hal_setuptxqueue(_ah, _type, _irq) \
|
||||
((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
|
||||
#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
|
||||
((*(_ah)->ah_getDiagState)((_ah), (_id), \
|
||||
(_indata), (_insize), (_outdata), (_outsize)))
|
||||
#define ath_hal_getregdomain(_ah, _prd) \
|
||||
ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd))
|
||||
#define ath_hal_getcountrycode(_ah, _pcc) \
|
||||
(*(_pcc) = (_ah)->ah_countryCode)
|
||||
|
||||
#define ath_hal_setuptxqueue(_ah, _type, _qinfo) \
|
||||
((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_qinfo)))
|
||||
#define ath_hal_resettxqueue(_ah, _q) \
|
||||
((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
|
||||
#define ath_hal_releasetxqueue(_ah, _q) \
|
||||
|
|
@ -357,10 +380,6 @@ int ath_intr(void *);
|
|||
#define ath_hal_rxmonitor(_ah) \
|
||||
((*(_ah)->ah_rxMonitor)((_ah)))
|
||||
|
||||
#define ath_hal_setupbeacondesc(_ah, _ds, _opmode, _flen, _hlen, \
|
||||
_rate, _antmode) \
|
||||
((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \
|
||||
(_flen), (_hlen), (_rate), (_antmode)))
|
||||
#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
|
||||
((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
|
||||
#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \
|
||||
|
|
@ -371,9 +390,9 @@ int ath_intr(void *);
|
|||
((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
|
||||
(_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
|
||||
(_flags), (_rtsrate), (_rtsdura)))
|
||||
#define ath_hal_setupxtxdesc(_ah, _ds, _short, \
|
||||
#define ath_hal_setupxtxdesc(_ah, _ds, \
|
||||
_txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
|
||||
((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), (_short), \
|
||||
((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
|
||||
(_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
|
||||
#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last) \
|
||||
((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last)))
|
||||
|
|
|
|||
Loading…
Reference in New Issue