rewrite suspend/resume routine. If you suspend while playing audio,
clcs and clct continue playing when resume.
This commit is contained in:
tacha
parent
8490f0b0c0
commit
109656b0a7
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@ -1,4 +1,4 @@
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/* $NetBSD: cs4280.c,v 1.15 2001/02/13 04:11:11 tacha Exp $ */
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/* $NetBSD: cs4280.c,v 1.16 2001/04/18 01:35:06 tacha Exp $ */
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/*
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* Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved.
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@ -660,9 +660,7 @@ cs4280_halt_output(addr)
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mem = BA1READ4(sc, CS4280_PCTL);
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BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK);
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#ifdef DIAGNOSTIC
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sc->sc_prun = 0;
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#endif
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return 0;
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}
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@ -675,9 +673,7 @@ cs4280_halt_input(addr)
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mem = BA1READ4(sc, CS4280_CCTL);
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BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK);
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#ifdef DIAGNOSTIC
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sc->sc_rrun = 0;
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#endif
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return 0;
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}
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@ -706,8 +702,8 @@ cs4280_trigger_output(addr, start, end, blksize, intr, arg, param)
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#ifdef DIAGNOSTIC
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if (sc->sc_prun)
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printf("cs4280_trigger_output: already running\n");
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sc->sc_prun = 1;
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#endif
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sc->sc_prun = 1;
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DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p "
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"blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg));
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@ -774,6 +770,7 @@ cs4280_trigger_output(addr, start, end, blksize, intr, arg, param)
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BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE);
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sc->sc_prate = param->sample_rate;
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cs4280_set_dac_rate(sc, param->sample_rate);
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pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK;
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@ -798,8 +795,9 @@ cs4280_trigger_input(addr, start, end, blksize, intr, arg, param)
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#ifdef DIAGNOSTIC
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if (sc->sc_rrun)
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printf("cs4280_trigger_input: already running\n");
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sc->sc_rrun = 1;
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#endif
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sc->sc_rrun = 1;
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DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p "
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"blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg));
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sc->sc_rintr = intr;
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@ -846,6 +844,7 @@ cs4280_trigger_input(addr, start, end, blksize, intr, arg, param)
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cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK;
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BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE);
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sc->sc_rrate = param->sample_rate;
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cs4280_set_adc_rate(sc, param->sample_rate);
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cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK;
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@ -861,6 +860,8 @@ cs4280_power(why, v)
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void *v;
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{
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struct cs428x_softc *sc = (struct cs428x_softc *)v;
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static u_int32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0;
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static u_int32_t cctl = 0, cba = 0, cie = 0;
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DPRINTF(("%s: cs4280_power why=%d\n",
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sc->sc_dev.dv_xname, why));
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@ -869,10 +870,28 @@ cs4280_power(why, v)
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case PWR_STANDBY:
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sc->sc_suspend = why;
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cs4280_halt_output(sc);
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cs4280_halt_input(sc);
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/* should I powerdown here ? */
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cs428x_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL);
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/* save current playback status */
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if ( sc->sc_prun ) {
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pctl = BA1READ4(sc, CS4280_PCTL);
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pfie = BA1READ4(sc, CS4280_PFIE);
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pba = BA1READ4(sc, CS4280_PBA);
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pdtc = BA1READ4(sc, CS4280_PDTC);
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DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n",
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pctl, pfie, pba, pdtc));
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}
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/* save current capture status */
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if ( sc->sc_rrun ) {
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cctl = BA1READ4(sc, CS4280_CCTL);
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cie = BA1READ4(sc, CS4280_CIE);
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cba = BA1READ4(sc, CS4280_CBA);
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DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n",
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cctl, cie, cba));
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}
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/* Stop DMA */
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BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK);
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BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK);
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break;
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case PWR_RESUME:
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if (sc->sc_suspend == PWR_RESUME) {
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@ -884,7 +903,28 @@ cs4280_power(why, v)
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cs4280_init(sc, 0);
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cs4280_reset_codec(sc);
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/* restore ac97 registers */
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(*sc->codec_if->vtbl->restore_ports)(sc->codec_if);
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/* restore DMA related status */
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if(sc->sc_prun) {
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DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n",
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pctl, pfie, pba, pdtc));
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cs4280_set_dac_rate(sc, sc->sc_prate);
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BA1WRITE4(sc, CS4280_PDTC, pdtc);
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BA1WRITE4(sc, CS4280_PBA, pba);
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BA1WRITE4(sc, CS4280_PFIE, pfie);
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BA1WRITE4(sc, CS4280_PCTL, pctl);
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}
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if (sc->sc_rrun) {
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DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n",
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cctl, cie, cba));
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cs4280_set_adc_rate(sc, sc->sc_rrate);
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BA1WRITE4(sc, CS4280_CBA, cba);
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BA1WRITE4(sc, CS4280_CIE, cie);
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BA1WRITE4(sc, CS4280_CCTL, cctl);
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}
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break;
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case PWR_SOFTSUSPEND:
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case PWR_SOFTSTANDBY:
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@ -1291,7 +1331,9 @@ cs4280_init(sc, init)
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*/
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mem = BA1READ4(sc, CS4280_PCTL);
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sc->pctl = mem & PCTL_MASK; /* save startup value */
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cs4280_halt_output(sc);
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BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK);
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if (init != 0)
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sc->sc_prun = 0;
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/* Save capture parameter and then write zero.
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* this ensures that DMA doesn't immediately occur upon
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@ -1299,7 +1341,9 @@ cs4280_init(sc, init)
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*/
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mem = BA1READ4(sc, CS4280_CCTL);
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sc->cctl = mem & CCTL_MASK; /* save startup value */
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cs4280_halt_input(sc);
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BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK);
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if (init != 0)
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sc->sc_rrun = 0;
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/* Processor Startup Procedure */
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BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV);
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@ -1,4 +1,4 @@
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/* $NetBSD: cs4281.c,v 1.3 2001/02/07 14:41:11 tacha Exp $ */
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/* $NetBSD: cs4281.c,v 1.4 2001/04/18 01:35:07 tacha Exp $ */
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/*
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* Copyright (c) 2000 Tatoku Ogaito. All rights reserved.
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@ -95,9 +95,9 @@ void cs4281_reset_codec(void *);
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/* Internal functions */
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u_int8_t cs4281_sr2regval(int);
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void cs4281_set_dac_rate(struct cs428x_softc *, int );
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void cs4281_set_adc_rate(struct cs428x_softc *, int );
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int cs4281_init(struct cs428x_softc *);
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void cs4281_set_dac_rate(struct cs428x_softc *, int);
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void cs4281_set_adc_rate(struct cs428x_softc *, int);
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int cs4281_init(struct cs428x_softc *, int);
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/* Power Management */
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void cs4281_power(int, void *);
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@ -262,7 +262,7 @@ cs4281_attach(parent, self, aux)
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/*
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* Sound System start-up
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*/
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if (cs4281_init(sc) != 0)
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if (cs4281_init(sc,1) != 0)
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return;
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sc->type = TYPE_CS4281;
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@ -509,9 +509,7 @@ cs4281_halt_output(addr)
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struct cs428x_softc *sc = addr;
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BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK);
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#ifdef DIAGNOSTIC
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sc->sc_prun = 0;
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#endif
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return 0;
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}
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@ -522,9 +520,7 @@ cs4281_halt_input(addr)
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struct cs428x_softc *sc = addr;
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BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK);
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#ifdef DIAGNOSTIC
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sc->sc_rrun = 0;
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#endif
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return 0;
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}
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@ -554,8 +550,8 @@ cs4281_trigger_output(addr, start, end, blksize, intr, arg, param)
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#ifdef DIAGNOSTIC
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if (sc->sc_prun)
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printf("cs4281_trigger_output: already running\n");
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sc->sc_prun = 1;
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#endif
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sc->sc_prun = 1;
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DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p "
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"blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg));
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@ -617,6 +613,7 @@ cs4281_trigger_output(addr, start, end, blksize, intr, arg, param)
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BA0WRITE4(sc, CS4281_DMR0, fmt);
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/* set sample rate */
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sc->sc_prate = param->sample_rate;
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cs4281_set_dac_rate(sc, param->sample_rate);
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/* start DMA */
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@ -624,14 +621,6 @@ cs4281_trigger_output(addr, start, end, blksize, intr, arg, param)
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/* Enable interrupts */
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BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM);
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#if 1
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/* XXX
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* I think these BA0WRITE4 should not be here
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*/
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BA0WRITE4(sc, CS4281_PPRVC, 7);
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BA0WRITE4(sc, CS4281_PPLVC, 7);
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#endif
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DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR)));
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DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR)));
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DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0)));
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@ -664,8 +653,8 @@ cs4281_trigger_input(addr, start, end, blksize, intr, arg, param)
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#ifdef DIAGNOSTIC
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if (sc->sc_rrun)
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printf("cs4281_trigger_input: already running\n");
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sc->sc_rrun = 1;
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#endif
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sc->sc_rrun = 1;
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DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p "
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"blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg));
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sc->sc_rintr = intr;
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@ -715,6 +704,7 @@ cs4281_trigger_input(addr, start, end, blksize, intr, arg, param)
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BA0WRITE4(sc, CS4281_DMR1, fmt);
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/* set sample rate */
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sc->sc_rrate = param->sample_rate;
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cs4281_set_adc_rate(sc, param->sample_rate);
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/* Start DMA */
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@ -737,6 +727,8 @@ cs4281_power(why, v)
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void *v;
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{
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struct cs428x_softc *sc = (struct cs428x_softc *)v;
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static u_int32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0;
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static u_int32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0;
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DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why));
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switch (why) {
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@ -744,10 +736,24 @@ cs4281_power(why, v)
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case PWR_STANDBY:
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sc->sc_suspend = why;
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cs4281_halt_output(sc);
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cs4281_halt_input(sc);
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/* should I powerdown here ? */
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cs428x_write_codec(sc, AC97_REG_POWER, CS4281_POWER_DOWN_ALL);
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/* save current playback status */
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if (sc->sc_prun) {
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dcr0 = BA0READ4(sc, CS4281_DCR0);
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dmr0 = BA0READ4(sc, CS4281_DMR0);
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dbc0 = BA0READ4(sc, CS4281_DBC0);
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dba0 = BA0READ4(sc, CS4281_DBA0);
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}
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/* save current capture status */
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if (sc->sc_rrun) {
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dcr1 = BA0READ4(sc, CS4281_DCR1);
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dmr1 = BA0READ4(sc, CS4281_DMR1);
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dbc1 = BA0READ4(sc, CS4281_DBC1);
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dba1 = BA0READ4(sc, CS4281_DBA1);
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}
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/* Stop DMA */
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BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK);
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BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK);
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break;
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case PWR_RESUME:
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if (sc->sc_suspend == PWR_RESUME) {
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@ -756,10 +762,30 @@ cs4281_power(why, v)
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return;
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}
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sc->sc_suspend = why;
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cs4281_init(sc);
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cs4281_init(sc,0);
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cs4281_reset_codec(sc);
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/* restore ac97 registers */
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(*sc->codec_if->vtbl->restore_ports)(sc->codec_if);
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/* restore DMA related status */
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if (sc->sc_prun) {
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cs4281_set_dac_rate(sc, sc->sc_prate);
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BA0WRITE4(sc, CS4281_DBA0, dba0);
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BA0WRITE4(sc, CS4281_DBC0, dbc0);
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BA0WRITE4(sc, CS4281_DMR0, dmr0);
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BA0WRITE4(sc, CS4281_DCR0, dcr0);
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}
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if (sc->sc_rrun) {
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cs4281_set_adc_rate(sc, sc->sc_rrate);
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BA0WRITE4(sc, CS4281_DBA1, dba1);
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BA0WRITE4(sc, CS4281_DBC1, dbc1);
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BA0WRITE4(sc, CS4281_DMR1, dmr1);
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BA0WRITE4(sc, CS4281_DCR1, dcr1);
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}
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/* enable intterupts */
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if (sc->sc_prun || sc->sc_rrun)
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BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM);
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break;
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case PWR_SOFTSUSPEND:
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case PWR_SOFTSTANDBY:
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@ -924,8 +950,9 @@ cs4281_set_dac_rate(sc, rate)
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}
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int
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cs4281_init(sc)
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cs4281_init(sc, init)
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struct cs428x_softc *sc;
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int init;
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{
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int n;
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u_int16_t data;
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@ -1219,5 +1246,16 @@ cs4281_init(sc)
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dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM;
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BA0WRITE4(sc, CS4281_HIMR,
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BA0READ4(sc, CS4281_HIMR) & dat32);
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/* set current status */
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if (init != 0) {
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sc->sc_prun = 0;
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sc->sc_rrun = 0;
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}
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/* setup playback volume */
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BA0WRITE4(sc, CS4281_PPRVC, 7);
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BA0WRITE4(sc, CS4281_PPLVC, 7);
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return 0;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: cs428x.c,v 1.1 2001/02/07 14:41:12 tacha Exp $ */
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/* $NetBSD: cs428x.c,v 1.2 2001/04/18 01:35:07 tacha Exp $ */
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/*
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* Copyright (c) 2000 Tatoku Ogaito. All rights reserved.
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@ -377,8 +377,11 @@ cs428x_src_wait(sc)
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n = 0;
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while ((BA0READ4(sc, CS428X_ACCTL) & ACCTL_DCV)) {
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delay(1000);
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while (++n > 1000)
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while (++n > 1000) {
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printf("cs428x_src_wait: 0x%08x\n",
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BA0READ4(sc, CS428X_ACCTL));
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return -1;
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}
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}
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return 0;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: cs428x.h,v 1.3 2001/02/07 14:41:12 tacha Exp $ */
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/* $NetBSD: cs428x.h,v 1.4 2001/04/18 01:35:08 tacha Exp $ */
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/*
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* Copyright (c) 2000 Tatoku Ogaito. All rights reserved.
|
||||
|
|
@ -93,9 +93,8 @@ struct cs428x_softc {
|
|||
struct cs428x_dma *sc_pdma;
|
||||
char *sc_pbuf;
|
||||
int (*halt_output)__P((void *));
|
||||
#ifdef DIAGNOSTIC
|
||||
char sc_prun;
|
||||
#endif
|
||||
char sc_prun; /* playback status */
|
||||
int sc_prate; /* playback sample rate */
|
||||
|
||||
/* capturing */
|
||||
void (*sc_rintr)(void *); /* dma completion intr handler */
|
||||
|
|
@ -107,9 +106,8 @@ struct cs428x_softc {
|
|||
char *sc_rbuf;
|
||||
int sc_rparam; /* record format */
|
||||
int (*halt_input)__P((void *));
|
||||
#ifdef DIAGNOSTIC
|
||||
char sc_rrun;
|
||||
#endif
|
||||
char sc_rrun; /* recording status */
|
||||
int sc_rrate; /* recording sample rate */
|
||||
|
||||
/* Although cs4281 does not support midi (yet),
|
||||
* don't remove these definition.
|
||||
|
|
|
|||
Loading…
Reference in New Issue