Some fixes and a bit consistency.
- naming practice of reverse endian PCI register access macros. - kse.c, errors in P1SR access and P1CR4 definition. - nvt.c, redundant device ID check.
This commit is contained in:
nisimura
parent
d2ebfa6451
commit
0ec9d4427f
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@ -1,4 +1,4 @@
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/* $NetBSD: kse.c,v 1.2 2009/01/12 09:41:59 tsutsui Exp $ */
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/* $NetBSD: kse.c,v 1.3 2009/01/25 03:39:28 nisimura Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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@ -44,8 +44,10 @@
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* - no VTOPHYS() translation, vaddr_t == paddr_t.
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* - PIPT writeback cache aware.
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*/
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#define CSR_READ(l, r) in32rb((l)->csr+(r))
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#define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))
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#define CSR_READ_4(l, r) in32rb((l)->csr+(r))
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#define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))
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#define CSR_READ_2(l, r) in16rb((l)->csr+(r))
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#define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
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#define VTOPHYS(va) (uint32_t)(va)
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#define DEVTOV(pa) (uint32_t)(pa)
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#define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz))
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@ -92,18 +94,9 @@ struct desc {
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#define MARM 0x202 /* MAC address middle */
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#define MARH 0x204 /* MAC address high */
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#define CIDR 0x400 /* chip ID and enable */
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#define P1CR4 0x510 /* port 1 control 4 */
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#define P1CR4 0x512 /* port 1 control 4 */
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#define P1SR 0x514 /* port 1 status */
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#define CSR_READ_4(l, off) \
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*(volatile unsigned *)((l)->csr + (off))
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#define CSR_WRITE_4(l, off, val) \
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*(volatile unsigned *)((l)->csr + (off)) = (val)
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#define CSR_READ_2(l, off) \
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*(volatile unsigned short *)((l)->csr + (off))
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#define CSR_WRITE_2(l, off, val) \
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*(volatile unsigned short *)((l)->csr + (off)) = (val)
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#define FRAMESIZE 1536
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struct local {
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@ -161,7 +154,7 @@ kse_init(unsigned tag, void *data)
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val = pcicfgread(tag, PCI_ID_REG);
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if (PCI_PRODUCT(val) == 0x8841) {
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val = CSR_READ_4(l, P1SR);
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val = CSR_READ_2(l, P1SR);
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fdx = !!(val & (1U << 9));
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printf("%s", (val & (1U << 8)) ? "100Mbps" : "10Mbps");
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if (fdx)
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@ -203,7 +196,7 @@ kse_send(void *dev, char *buf, unsigned len)
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txd->xd1 = htole32(T1_FS | T1_LS | (len & T1_TBS_MASK));
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txd->xd0 = htole32(T0_OWN);
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wbinv(txd, sizeof(struct desc));
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CSR_WRITE(l, MDTSC, 01); /* start transmission */
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CSR_WRITE_4(l, MDTSC, 01); /* start transmission */
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loop = 100;
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do {
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txstat = le32toh(txd->xd0);
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@ -244,7 +237,7 @@ printf("recving with %u sec. timeout\n", timo);
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rxd->xd0 = htole32(R0_OWN);
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wbinv(rxd, sizeof(struct desc));
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l->rx ^= 1;
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CSR_WRITE(l, MDRSC, 01); /* restart receiving */
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CSR_WRITE_4(l, MDRSC, 01); /* restart receiving */
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goto again;
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}
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/* good frame */
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@ -257,7 +250,7 @@ printf("recving with %u sec. timeout\n", timo);
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rxd->xd0 = htole32(R0_OWN);
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wbinv(rxd, sizeof(struct desc));
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l->rx ^= 1;
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CSR_WRITE(l, MDRSC, 01); /* necessary? */
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CSR_WRITE_4(l, MDRSC, 01); /* necessary? */
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return len;
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}
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@ -267,10 +260,10 @@ mii_dealan(struct local *l, unsigned timo)
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unsigned val, bound;
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val = (1U << 13) | (1U << 7) | 0x1f /* advertise all caps */;
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CSR_WRITE_4(l, P1CR4, val);
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CSR_WRITE_2(l, P1CR4, val);
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bound = getsecs() + timo;
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do {
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val = CSR_READ_4(l, P1SR);
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val = CSR_READ_2(l, P1SR);
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if (val & (1U << 5)) /* link is found up */
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break;
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DELAY(10 * 1000);
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@ -1,4 +1,4 @@
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/* $NetBSD: nvt.c,v 1.16 2009/01/12 09:41:59 tsutsui Exp $ */
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/* $NetBSD: nvt.c,v 1.17 2009/01/25 03:39:28 nisimura Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -175,21 +175,16 @@ nvt_init(unsigned tag, void *data)
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struct desc *txd, *rxd;
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uint8_t *en;
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val = pcicfgread(tag, PCI_ID_REG);
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if (PCI_DEVICE(0x1106, 0x3053) != val
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&& PCI_DEVICE(0x1106, 0x3065) != val)
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return NULL;
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l = ALLOC(struct local, sizeof(struct desc)); /* desc alignment */
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memset(l, 0, sizeof(struct local));
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l->csr = DEVTOV(pcicfgread(tag, 0x14)); /* use mem space */
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l->csr = ~01 & DEVTOV(pcicfgread(tag, 0x10)); /* use IO space */
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val = CTL1_RESET;
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CSR_WRITE_1(l, VR_CTL1, val);
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do {
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val = CSR_READ_1(l, VR_CTL1);
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} while (val & CTL1_RESET);
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/* PHY number is loaded from EEPROM */
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l->phy = CSR_READ_1(l, VR_MIICFG) & 0x1f;
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en = data;
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@ -1,4 +1,4 @@
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/* $NetBSD: pcn.c,v 1.15 2009/01/12 09:41:59 tsutsui Exp $ */
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/* $NetBSD: pcn.c,v 1.16 2009/01/25 03:39:28 nisimura Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -44,10 +44,10 @@
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* - no vtophys() translation, vaddr_t == paddr_t.
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* - PIPT writeback cache aware.
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*/
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#define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
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#define CSR_READ_2(l, r) in16rb((l)->csr+(r))
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#define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))
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#define CSR_READ_4(l, r) in32rb((l)->csr+(r))
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#define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))
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#define CSR_READ_2(l, r) in16rb((l)->csr+(r))
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#define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
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#define VTOPHYS(va) (uint32_t)(va)
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#define DEVTOV(pa) (uint32_t)(pa)
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#define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz))
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@ -1,4 +1,4 @@
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/* $NetBSD: tlp.c,v 1.21 2009/01/12 09:41:59 tsutsui Exp $ */
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/* $NetBSD: tlp.c,v 1.22 2009/01/25 03:39:28 nisimura Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -44,8 +44,8 @@
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* - no vtophys() translation, vaddr_t == paddr_t.
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* - PIPT writeback cache aware.
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*/
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#define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))
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#define CSR_READ(l, r) in32rb((l)->csr+(r))
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#define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))
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#define VTOPHYS(va) (uint32_t)(va)
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#define DEVTOV(pa) (uint32_t)(pa)
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#define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz))
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@ -1,4 +1,4 @@
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/* $NetBSD: wm.c,v 1.9 2009/01/12 09:41:59 tsutsui Exp $ */
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/* $NetBSD: wm.c,v 1.10 2009/01/25 03:39:28 nisimura Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -46,8 +46,8 @@
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* - no vtophys() translation, vaddr_t == paddr_t.
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* - PIPT writeback cache aware.
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*/
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#define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))
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#define CSR_READ(l, r) in32rb((l)->csr+(r))
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#define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))
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#define VTOPHYS(va) (uint32_t)(va)
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#define DEVTOV(pa) (uint32_t)(pa)
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#define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz))
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