Converted the fault handlers for the PA7100LC and up to handle
mappings not marked TLB_NO_RW_ALIAS.
This commit is contained in:
fredette
parent
3b13379090
commit
0e92be5ea7
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@ -1,4 +1,4 @@
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/* $NetBSD: trap.S,v 1.3 2002/08/11 22:29:09 fredette Exp $ */
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/* $NetBSD: trap.S,v 1.4 2002/08/13 20:29:52 fredette Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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@ -1253,7 +1253,7 @@ $hash_loop_tlbd_t
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/*
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* Otherwise, just calculate the HPT tag, set the
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* dirty bit on the mapping, and load it into the
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* TLB and HPT.
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* HPT and TLB.
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*/
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$load_tlbd_t
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VTAG(%r8, %r9, %r16)
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@ -1519,13 +1519,33 @@ LEAF_ENTRY(desidhash_l)
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EXIT(desidhash_l)
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.align 32
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/*
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* This is a handler for interruption 20, "TLB dirty bit trap". It
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* is used on the PA7100LC (PCX-L), PA7300LC (PCX-L2), PA8000 (PCX-U),
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* PA8200 (PCX-W), PA8500 (PCX-W), and PA8600 (PCX-W+). Only shadowed
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* registers are available, and they are:
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*
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* %r1 = C trap number
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* %r8 = data address space identifier
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* %r9 = data address offset
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* %r16 = undefined
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* %r17 = undefined
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* %r24 = undefined
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* %r25 = undefined
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*/
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$tlbd_l
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mfctl cr28, r24
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/*
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* Calculate the offset of the HPT entry into %r24,
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* and save it into %cr28 for recovery later, when
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* we want to update the HPT.
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*/
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HPTENT
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mtctl %r24, %cr28
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/*
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* Chase the list of entries for this hash bucket until we find
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* the correct mapping or NULL.
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* Search the list of mappings attached to this
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* HPT entry until we find the faulting mapping.
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* If we don't find it, trap to C.
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*/
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ldw HPT_ENTRY(r24), r16
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$hash_loop_tlbd_l
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@ -1537,31 +1557,118 @@ $hash_loop_tlbd_l
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comb,<>,n r8, r17, $hash_loop_tlbd_l
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ldw PV_HASH(r16), r16
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/* Set the dirty bit for this physical page. */
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/*
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* We found the faulting mapping. If it is not
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* marked TLB_NO_RW_ALIAS, we have to flush all
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* other mappings of this page.
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*/
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ldw PV_TLBPAGE(r16), r17
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ldw PV_TLBPROT(r16), r25
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bb,>=,n %r25, TLB_NO_RW_ALIAS_POS, $flush_all_tlbd_l
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/*
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* Otherwise, set the dirty bit on the mapping, and
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* load it into the HPT and TLB.
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*/
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b $tlb_inshpt_l
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depi 1, TLB_DIRTY_POS, 1, r25
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.align 8
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/*
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* This flushes all other mappings of the page. Since
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* the flushing subroutine destroys effectively preserves
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* only the address of the writable mapping, we have to
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* reload all other registers before we can continue.
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*/
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$flush_all_tlbd_l
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bl $flush_all_tlbd, %r1
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copy %r16, %r24
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copy %r0, %r1 /* reload %r1, 0 => DTLB */
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DTLBPRE /* reload %r8, %r9 */
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copy %r24, %r16 /* reload %r16 */
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mfctl %cr28, %r24 /* reload %r24 */
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ldw PV_TLBPAGE(%r16), %r17 /* reload %r17 */
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ldw PV_TLBPROT(%r16), %r25 /* reload %r25 */
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b $tlb_inshpt_l
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depi 1, TLB_DIRTY_POS, 1, %r25 /* set dirty bit */
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/*
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* This is a handler for interruption 6, "Instruction TLB miss fault",
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* and interruption 16, "Non-access instruction TLB miss fault". It
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* is used on the PA7100LC (PCX-L), PA7300LC (PCX-L2), PA8000 (PCX-U),
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* PA8200 (PCX-W), PA8500 (PCX-W), and PA8600 (PCX-W+). Only shadowed
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* registers are available, and they are:
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*
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* %r1 = C trap number
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* %r8 = instruction address space identifier
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* %r9 = instruction address offset
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* %r16 = undefined
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* %r17 = undefined
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* %r24 = undefined
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* %r25 = undefined
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*/
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$itlb_l
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depi 1, TFF_ITLB_POS, 1, r1 /* mark for ITLB insert */
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/* FALLTHROUGH */
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/*
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* This is a handler for interruption 17, "Non-access data TLB miss
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* fault". It is used on the PA7100LC (PCX-L), PA7300LC (PCX-L2),
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* PA8000 (PCX-U), PA8200 (PCX-W), PA8500 (PCX-W), and PA8600 (PCX-W+).
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* Only shadowed registers are available, and they are:
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*
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* %r1 = C trap number
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* %r8 = data address space identifier
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* %r9 = data address offset
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* %r16 = undefined
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* %r17 = undefined
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* %r24 = undefined
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* %r25 = undefined
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*/
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$dtlbna_l
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/*
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* Calculate the offset of the HPT entry into %r24,
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* and save it into %cr28 for recovery later, when
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* we want to update the HPT.
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*
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* XXX fredette: does the PA7100LC not provide the
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* HPT entry in %cr28 for a non-access DTLB miss?
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* What about an ITLB miss or non-access ITLB miss?
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* Having this here, if unnecessary, hurts the
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* performance of all of these faults.
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*/
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HPTENT
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mtctl r24, cr28
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/* FALLTHROUGH */
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$dtlb_l
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mfctl cr28, r24
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/*
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* r1 is the trap type
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* r8 is the space of the address that had the TLB miss
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* r9 is the offset of the address that had the TLB miss
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* r24 is the correspondent HPT entry pointer
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/*
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* This is a handler for interruption 15, "Data TLB miss fault".
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* It is used on the PA7100LC (PCX-L), PA7300LC (PCX-L2),
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* PA8000 (PCX-U), PA8200 (PCX-W), PA8500 (PCX-W), and PA8600 (PCX-W+).
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* Only shadowed registers are available, and they are:
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*
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* %r1 = C trap number
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* %r8 = data address space identifier
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* %r9 = data address offset
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* %r16 = undefined
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* %r17 = undefined
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* %r24 = undefined
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* %r25 = undefined
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*/
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$dtlb_l
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/*
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* On entry, %cr28 contains the address of the
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* relevant HPT entry, courtesy of hpti_g's call
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* to PDC_TLB(8)/PDC_TLB_CONFIG(1) asking for
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* PDC_TLB_CURRPDE.
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*/
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mfctl cr28, r24
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/*
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* Chase the list of entries for this hash bucket until we find
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* the correct mapping or NULL.
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* Search the list of mappings attached to this
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* HPT entry until we find the faulting mapping.
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* If we don't find it, branch to a subhandler
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* that checks for a non-access fault caused by
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* an LPA instruction.
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*/
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ldw HPT_ENTRY(r24), r16
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$hash_loop_l
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@ -1573,14 +1680,32 @@ $hash_loop_l
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comb,<>,n r8, r17, $hash_loop_l
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ldw PV_HASH(r16), r16
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/* Now set things up to enter the real mapping that we want */
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/*
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* If this mapping is not marked TLB_REF, and
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* it isn't marked TLB_NO_RW_ALIAS, we have to
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* flush any writable mapping for this page.
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* Since TLB_REF and TLB_NO_RW_ALIAS are adjacent,
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* we can test if they are both clear with one
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* extru instruction.
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*/
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ldw PV_TLBPAGE(r16), r17
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ldw PV_TLBPROT(r16), r25
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extru,<> %r25, TLB_NO_RW_ALIAS_POS, 2, %r0
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b,n $flush_writable_l
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/* Mark this mapping as referenced. */
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depi 1, TLB_REF_POS, 1, r25
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/*
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* Load the HPT cache with the miss information for the next time.
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* The HPT entry address was saved by the HPTENT
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/*
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* Load the HPT entry and TLB with a mapping. On entry:
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*
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* %r1 = C trap number
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* %r8 = address space identifier
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* %r9 = address offset
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* %r16 = mapping
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* %r17 = TLB page
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* %r24 = HPT entry
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* %r25 = TLB protection
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*/
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$tlb_inshpt_l
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stw r25, PV_TLBPROT(r16)
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@ -1603,6 +1728,56 @@ $tlb_itlb_l
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nop ! nop
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rfir
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nop
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/*
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* Flush any writable mapping in the TLB and cache, in order
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* to insert a readable mapping. On entry:
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*
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* %r1 = C trap number
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* %r8 = undefined
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* %r9 = undefined
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* %r16 = struct pv_entry * of readable mapping
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* %r17 = undefined
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* %r24 = undefined
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* %r25 = undefined
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*/
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$flush_writable_l
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/*
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* Branch if this was an ITLB fault.
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*/
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bb,<,n %r1, TFF_ITLB_POS, $flush_writable_itlb_l
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/*
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* Flush any writable mapping, then reload registers
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* for an HPT and DTLB insertion.
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*/
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bl $flush_writable, %r1
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copy %r16, %r24
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copy %r0, %r1 /* reload %r0, 0 => DTLB */
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DTLBPRE /* reload %r8, %r9 */
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copy %r24, %r16 /* reload %r16 */
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ldw PV_TLBPAGE(%r16), %r17 /* reload %r17 */
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ldw PV_TLBPROT(%r16), %r25 /* reload %r25 */
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mfctl %cr28, %r24 /* reload %r24 */
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b $tlb_inshpt_l
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depi 1, TLB_REF_POS, 1, %r25 /* set ref bit */
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$flush_writable_itlb_l
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/*
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* Flush any writable mapping, then reload registers
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* for an HPT and ITLB insertion.
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*/
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bl $flush_writable, %r1
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copy %r16, %r24
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ldil L%TFF_ITLB, %r1 /* reload %r0 */
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ITLBPRE /* reload %r8, %r9 */
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copy %r24, %r16 /* reload %r16 */
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ldw PV_TLBPAGE(%r16), %r17 /* reload %r17 */
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ldw PV_TLBPROT(%r16), %r25 /* reload %r25 */
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mfctl %cr28, %r24 /* reload %r24 */
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b $tlb_inshpt_l
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depi 1, TLB_REF_POS, 1, %r25 /* set ref bit */
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#endif /* HP7100LC_CPU */
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.export $tlbiflpa, entry
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