Aren
/
NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

PR port-sparc/54789: Sparc boot fails with "Trap 0x21 while interrupts disabled" 

Remove assumption that cpu_info is smaller than 1kB.
This commit is contained in:
ad 2019-12-30 22:13:46 +00:00
parent bd97401499
commit 0e79d963e9
6 changed files with 55 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
sys/arch/sparc/dev/apc.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: apc.c,v 1.1 2010/01/15 20:57:12 bouyer Exp $ */
/* $NetBSD: apc.c,v 1.2 2019/12/30 22:13:46 ad Exp $ */
/*
* Copyright (c) 2010 Manuel Bouyer.
@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: apc.c,v 1.1 2010/01/15 20:57:12 bouyer Exp $");
__KERNEL_RCSID(0, "$NetBSD: apc.c,v 1.2 2019/12/30 22:13:46 ad Exp $");
/*
@ -45,7 +45,7 @@ __KERNEL_RCSID(0, "$NetBSD: apc.c,v 1.1 2010/01/15 20:57:12 bouyer Exp $");
static int apcmatch(device_t, struct cfdata *, void *);
static void apcattach(device_t, device_t, void *);
static void apc_cpu_sleep(struct cpu_info *);
static void apc_cpu_sleep(void);
struct apc_softc {
device_t sc_dev;
@ -86,7 +86,7 @@ apcattach(device_t parent, device_t self, void *aux)
}
static void
apc_cpu_sleep(struct cpu_info *ci)
apc_cpu_sleep(void)
{
uint8_t val;
if (apc == NULL)

4
sys/arch/sparc/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.103 2019/12/01 15:34:45 ad Exp $ */
/* $NetBSD: cpu.h,v 1.104 2019/12/30 22:13:47 ad Exp $ */
/*
* Copyright (c) 1992, 1993
@ -374,7 +374,7 @@ struct cpu_info {
* unrecoverable faults end up here.
*/
void (*memerr)(unsigned, u_int, u_int, struct trapframe *);
void (*idlespin)(struct cpu_info *);
void (*idlespin)(void);
/* Module Control Registers */
/*bus_space_handle_t*/ long ci_mbusport;
/*bus_space_handle_t*/ long ci_mxccregs;

9
sys/arch/sparc/sparc/clkctrl.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: clkctrl.c,v 1.5 2011/07/17 23:32:37 mrg Exp $ */
/* $NetBSD: clkctrl.c,v 1.6 2019/12/30 22:13:47 ad Exp $ */
/*
* Copyright (c) 2005 Michael Lorenz
@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: clkctrl.c,v 1.5 2011/07/17 23:32:37 mrg Exp $");
__KERNEL_RCSID(0, "$NetBSD: clkctrl.c,v 1.6 2019/12/30 22:13:47 ad Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -44,7 +44,7 @@ static void clkctrl_attach(device_t, device_t, void *);
CFATTACH_DECL_NEW(clkctrl, 0,
clkctrl_match, clkctrl_attach, NULL, NULL);
static void tadpole_cpu_sleep(struct cpu_info *);
static void tadpole_cpu_sleep(void);
volatile uint8_t *clkctrl_reg = NULL;
static int
@ -91,8 +91,9 @@ clkctrl_attach(device_t parent, device_t self, void *aux)
/* ARGSUSED */
static void
tadpole_cpu_sleep(struct cpu_info *ci)
tadpole_cpu_sleep(void)
{
if (clkctrl_reg == 0)
return;
*clkctrl_reg = 0;

20
sys/arch/sparc/sparc/lock_stubs.s
View File

@ -1,4 +1,4 @@
/* $NetBSD: lock_stubs.s,v 1.12 2008/05/25 15:56:12 chs Exp $ */
/* $NetBSD: lock_stubs.s,v 1.13 2019/12/30 22:13:47 ad Exp $ */
/*-
* Copyright (c) 2002, 2007 The NetBSD Foundation, Inc.
@ -122,10 +122,10 @@ ENTRY(mutex_exit)
* void mutex_spin_enter(kmutex_t *);
*/
ENTRY(mutex_spin_enter)
sethi %hi(CPUINFO_VA), %o4
ld [ %o4 + CPUINFO_MTX_COUNT ], %o5
sethi %hi(CPUINFO_VA+CPUINFO_MTX_COUNT), %o4
ld [ %o4 + %lo(CPUINFO_VA+CPUINFO_MTX_COUNT) ], %o5
sub %o5, 1, %o1
st %o1, [ %o4 + CPUINFO_MTX_COUNT ]
st %o1, [ %o4 + %lo(CPUINFO_VA+CPUINFO_MTX_COUNT) ]
ldub [ %o0 + MTX_IPL ], %o2
rd %psr, %o1
sll %o2, 8, %o2
@ -140,8 +140,9 @@ ENTRY(mutex_spin_enter)
nop
tst %o5
1:
sethi %hi(CPUINFO_VA+CPUINFO_MTX_OLDSPL), %o4
bz,a 2f
st %o3, [ %o4 + CPUINFO_MTX_OLDSPL ]
st %o3, [ %o4 + %lo(CPUINFO_VA+CPUINFO_MTX_OLDSPL) ]
2:
#if defined(MULTIPROCESSOR) || defined(DIAGNOSTIC)
ldstub [ %o0 + MTX_LOCK ], %o2
@ -166,12 +167,13 @@ ENTRY(mutex_spin_exit)
#elif defined(MULTIPROCESSOR)
clrb [ %o0 + MTX_LOCK ]
#endif
sethi %hi(CPUINFO_VA), %o2
ld [ %o2 + CPUINFO_MTX_OLDSPL ], %o3
ld [ %o2 + CPUINFO_MTX_COUNT ], %o1
sethi %hi(CPUINFO_VA+CPUINFO_MTX_OLDSPL), %o2
ld [ %o2 + %lo(CPUINFO_VA+CPUINFO_MTX_OLDSPL) ], %o3
sethi %hi(CPUINFO_VA+CPUINFO_MTX_COUNT), %o2
ld [ %o2 + %lo(CPUINFO_VA+CPUINFO_MTX_COUNT) ], %o1
addcc %o1, 1, %o4
bnz 1f
st %o4, [ %o2 + CPUINFO_MTX_COUNT ]
st %o4, [ %o2 + %lo(CPUINFO_VA+CPUINFO_MTX_COUNT) ]
rd %psr, %o1
andn %o1, PSR_PIL, %o1
wr %o3, %o1, %psr

55
sys/arch/sparc/sparc/locore.s
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.s,v 1.274 2019/06/07 00:18:26 mrg Exp $ */
/* $NetBSD: locore.s,v 1.275 2019/12/30 22:13:47 ad Exp $ */
/*
* Copyright (c) 1996 Paul Kranenburg
@ -1954,10 +1954,11 @@ memfault_sun4c:
#if defined(SUN4M)
_ENTRY(memfault_sun4m)
memfault_sun4m:
sethi %hi(CPUINFO_VA), %l4
sethi %hi(CPUINFO_VA+CPUINFO_GETSYNCFLT), %l4
ld [%l4 + %lo(CPUINFO_VA+CPUINFO_GETSYNCFLT)], %l5
sethi %hi(CPUINFO_VA+CPUINFO_SYNCFLTDUMP), %l4
jmpl %l5, %l7
or %l4, %lo(CPUINFO_SYNCFLTDUMP), %l4
or %l4, %lo(CPUINFO_VA+CPUINFO_SYNCFLTDUMP), %l4
TRAP_SETUP(-CCFSZ-80)
! tally fault (curcpu()->cpu_data.cpu_nfault++) (clobbers %o0,%o1,%o2)
INCR64(CPUINFO_VA + CPUINFO_NFAULT)
@ -2519,10 +2520,10 @@ softintr_common:
set _C_LABEL(sintrhand), %l4! %l4 = sintrhand[intlev];
ld [%l4 + %l5], %l4
sethi %hi(CPUINFO_VA), %o2
ld [ %o2 + CPUINFO_IDEPTH ], %o3
sethi %hi(CPUINFO_VA+CPUINFO_IDEPTH), %o2
ld [ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ], %o3
inc %o3
st %o3, [ %o2 + CPUINFO_IDEPTH ]
st %o3, [ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ]
b 3f
st %fp, [%sp + CCFSZ + 16]
@ -2543,10 +2544,10 @@ softintr_common:
bnz 1b
nop
sethi %hi(CPUINFO_VA), %o2
ld [ %o2 + CPUINFO_IDEPTH ], %o3
sethi %hi(CPUINFO_VA+CPUINFO_IDEPTH), %o2
ld [ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ], %o3
dec %o3
st %o3, [ %o2 + CPUINFO_IDEPTH ]
st %o3, [ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ]
mov %l7, %g1
wr %l6, 0, %y
@ -2563,8 +2564,8 @@ softintr_common:
#if defined(SUN4M)
_ENTRY(_C_LABEL(sparc_interrupt4m))
#if !defined(MSIIEP) /* "normal" sun4m */
sethi %hi(CPUINFO_VA), %l6
ld [%l6 + CPUINFO_INTREG], %l7
sethi %hi(CPUINFO_VA+CPUINFO_INTREG), %l6
ld [%l6 + %lo(CPUINFO_VA+CPUINFO_INTREG)], %l7
mov 1, %l4
ld [%l7 + ICR_PI_PEND_OFFSET], %l5 ! get pending interrupts
sll %l4, %l3, %l4 ! hw intr bits are in the lower halfword
@ -2704,10 +2705,10 @@ sparc_interrupt_common:
set _C_LABEL(intrhand), %l4 ! %l4 = intrhand[intlev];
ld [%l4 + %l5], %l4
sethi %hi(CPUINFO_VA), %o2
ld [ %o2 + CPUINFO_IDEPTH ], %o3
sethi %hi(CPUINFO_VA+CPUINFO_IDEPTH), %o2
ld [ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ], %o3
inc %o3
st %o3, [ %o2 + CPUINFO_IDEPTH ]
st %o3, [ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ]
b 3f
st %fp, [%sp + CCFSZ + 16]
@ -2742,10 +2743,10 @@ sparc_interrupt_common:
add %sp, CCFSZ, %o0
/* all done: restore registers and go return */
4:
sethi %hi(CPUINFO_VA), %o2
ld [ %o2 + CPUINFO_IDEPTH ], %o3
sethi %hi(CPUINFO_VA+CPUINFO_IDEPTH), %o2
ld [ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ], %o3
dec %o3
st %o3, [ %o2 + CPUINFO_IDEPTH ]
st %o3, [ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ]
mov %l7, %g1
wr %l6, 0, %y
@ -2763,8 +2764,8 @@ sparc_interrupt_common:
* %l6 = &cpuinfo
*/
lev14_softint:
sethi %hi(CPUINFO_VA), %l7
ldd [%l7 + CPUINFO_LEV14], %l4
sethi %hi(CPUINFO_VA+CPUINFO_LEV14), %l7
ldd [%l7 + %lo(CPUINFO_VA+CPUINFO_LEV14)], %l4
inccc %l5
addx %l4, %g0, %l4
std %l4, [%l7 + CPUINFO_LEV14]
@ -4961,13 +4962,13 @@ Lsw_noras:
* Call the idlespin() function if it exists, otherwise just return.
*/
ENTRY(cpu_idle)
sethi %hi(CPUINFO_VA), %o0
ld [%o0 + CPUINFO_IDLESPIN], %o1
sethi %hi(CPUINFO_VA+CPUINFO_IDLESPIN), %o0
ld [%o0 + %lo(CPUINFO_VA+CPUINFO_IDLESPIN)], %o1
tst %o1
bz 1f
nop
jmp %o1
nop ! CPUINFO_VA is already in %o0
nop
1:
retl
nop
@ -5641,8 +5642,8 @@ Lpanic_savefpstate:
_ALIGN
ENTRY(ipi_savefpstate)
sethi %hi(CPUINFO_VA), %o5
ldd [%o5 + CPUINFO_SAVEFPSTATE], %o2
sethi %hi(CPUINFO_VA+CPUINFO_SAVEFPSTATE), %o5
ldd [%o5 + %lo(CPUINFO_VA+CPUINFO_SAVEFPSTATE)], %o2
inccc %o3
addx %o2, 0, %o2
std %o2, [%o5 + CPUINFO_SAVEFPSTATE]
@ -5855,14 +5856,16 @@ _ENTRY(_C_LABEL(cypress_get_syncflt))
_ENTRY(_C_LABEL(smp_get_syncflt))
save %sp, -CCFSZ, %sp
sethi %hi(CPUINFO_VA), %o4
sethi %hi(CPUINFO_VA+CPUINFO_GETSYNCFLT), %o4
ld [%l4 + %lo(CPUINFO_VA+CPUINFO_GETSYNCFLT)], %o5
clr %l1
clr %l3
sethi %hi(CPUINFO_VA+CPUINFO_SYNCFLTDUMP), %o4
jmpl %o5, %l7
or %o4, %lo(CPUINFO_SYNCFLTDUMP), %l4
or %o4, %lo(CPUINFO_VA+CPUINFO_SYNCFLTDUMP), %l4
! load values out of the dump
sethi %hi(CPUINFO_VA+CPUINFO_SYNCFLTDUMP), %o4
ld [%o4 + %lo(CPUINFO_VA+CPUINFO_SYNCFLTDUMP)], %o5
st %o5, [%i0]
ld [%o4 + %lo(CPUINFO_VA+CPUINFO_SYNCFLTDUMP+4)], %o5

8
sys/arch/sparc/sparc/msiiep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: msiiep.c,v 1.47 2019/11/10 21:16:33 chs Exp $ */
/* $NetBSD: msiiep.c,v 1.48 2019/12/30 22:13:47 ad Exp $ */
/*
* Copyright (c) 2001 Valeriy E. Ushakov
@ -27,7 +27,7 @@
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: msiiep.c,v 1.47 2019/11/10 21:16:33 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: msiiep.c,v 1.48 2019/12/30 22:13:47 ad Exp $");
#include <sys/param.h>
#include <sys/malloc.h>
@ -72,7 +72,7 @@ CFATTACH_DECL_NEW(msiiep, 0, msiiep_match, msiiep_attach, NULL, NULL);
/* sleep in idle spin */
static void msiiep_cpu_sleep(struct cpu_info *);
static void msiiep_cpu_sleep(void);
volatile uint32_t *msiiep_mid = NULL;
@ -241,7 +241,7 @@ msiiep_attach(device_t parent, device_t self, void *aux)
/* ARGSUSED */
void
msiiep_cpu_sleep(struct cpu_info *ci)
msiiep_cpu_sleep(void)
{
uint32_t reg;