au_icu.c is in mips/ and should not depend on evbmips intr handler struct.
convert various u_int32_t to preferred uint32_t.
This commit is contained in:
gdamore
parent
3d80f87df2
commit
0cf592aa8a
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@ -1,4 +1,4 @@
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/* $NetBSD: mach_intr.c,v 1.1 2006/02/07 18:57:12 gdamore Exp $ */
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/* $NetBSD: mach_intr.c,v 1.2 2006/02/09 18:03:12 gdamore Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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@ -45,7 +45,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mach_intr.c,v 1.1 2006/02/07 18:57:12 gdamore Exp $");
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__KERNEL_RCSID(0, "$NetBSD: mach_intr.c,v 1.2 2006/02/09 18:03:12 gdamore Exp $");
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#include "opt_ddb.h"
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@ -70,8 +70,7 @@ evbmips_intr_init(void)
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}
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void
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evbmips_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc,
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u_int32_t ipending)
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evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
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{
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au_iointr(status, cause, pc, ipending);
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.h,v 1.6 2005/11/27 14:01:45 yamt Exp $ */
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/* $NetBSD: intr.h,v 1.7 2006/02/09 18:03:12 gdamore Exp $ */
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/*-
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* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
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@ -88,8 +88,8 @@
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#ifdef _KERNEL
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extern const u_int32_t ipl_sr_bits[_IPL_N];
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extern const u_int32_t ipl_si_to_sr[_IPL_NSOFT];
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extern const uint32_t ipl_sr_bits[_IPL_N];
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extern const uint32_t ipl_si_to_sr[_IPL_NSOFT];
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extern int _splraise(int);
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extern int _spllower(int);
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@ -121,7 +121,7 @@ struct evbmips_intrhand {
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void evbmips_intr_init(void);
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void intr_init(void);
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void evbmips_iointr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
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void evbmips_iointr(uint32_t, uint32_t, uint32_t, uint32_t);
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void *evbmips_intr_establish(int, int (*)(void *), void *);
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void evbmips_intr_disestablish(void *);
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#endif /* _KERNEL */
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@ -1,4 +1,4 @@
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/* $NetBSD: malta_intr.c,v 1.10 2005/11/25 13:55:14 simonb Exp $ */
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/* $NetBSD: malta_intr.c,v 1.11 2006/02/09 18:03:12 gdamore Exp $ */
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/*
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* Copyright 2001, 2002 Wasabi Systems, Inc.
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@ -40,7 +40,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.10 2005/11/25 13:55:14 simonb Exp $");
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__KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.11 2006/02/09 18:03:12 gdamore Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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@ -64,7 +64,7 @@ __KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.10 2005/11/25 13:55:14 simonb Exp $
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* This is a mask of bits to clear in the SR when we go to a
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* given hardware interrupt priority level.
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*/
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const u_int32_t ipl_sr_bits[_IPL_N] = {
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const uint32_t ipl_sr_bits[_IPL_N] = {
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0, /* 0: IPL_NONE */
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MIPS_SOFT_INT_MASK_0, /* 1: IPL_SOFT */
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@ -104,7 +104,7 @@ const u_int32_t ipl_sr_bits[_IPL_N] = {
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* given software interrupt priority level.
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* Hardware ipls are port/board specific.
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*/
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const u_int32_t mips_ipl_si_to_sr[_IPL_NSOFT] = {
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const uint32_t mips_ipl_si_to_sr[_IPL_NSOFT] = {
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MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
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MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
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MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
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@ -165,7 +165,7 @@ void
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malta_cal_timer(bus_space_tag_t st, bus_space_handle_t sh)
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{
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uint32_t ctrdiff[4], startctr, endctr;
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u_int8_t regc;
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uint8_t regc;
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int i;
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/* Disable interrupts first. */
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@ -1,4 +1,4 @@
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/* $NetBSD: au_icu.c,v 1.13 2006/02/06 23:23:53 gdamore Exp $ */
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/* $NetBSD: au_icu.c,v 1.14 2006/02/09 18:03:12 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Itronix Inc.
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@ -75,7 +75,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.13 2006/02/06 23:23:53 gdamore Exp $");
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__KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.14 2006/02/09 18:03:12 gdamore Exp $");
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#include "opt_ddb.h"
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@ -93,14 +93,14 @@ __KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.13 2006/02/06 23:23:53 gdamore Exp $");
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#include <mips/alchemy/include/aureg.h>
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#include <mips/alchemy/include/auvar.h>
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#define REGVAL(x) *((volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1((x))))
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#define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
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/*
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* This is a mask of bits to clear in the SR when we go to a
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* given hardware interrupt priority level.
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*/
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const u_int32_t ipl_sr_bits[_IPL_N] = {
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const uint32_t ipl_sr_bits[_IPL_N] = {
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0, /* 0: IPL_NONE */
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MIPS_SOFT_INT_MASK_0, /* 1: IPL_SOFT */
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@ -138,7 +138,7 @@ const u_int32_t ipl_sr_bits[_IPL_N] = {
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* given software interrupt priority level.
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* Hardware ipls are port/board specific.
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*/
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const u_int32_t mips_ipl_si_to_sr[_IPL_NSOFT] = {
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const uint32_t mips_ipl_si_to_sr[_IPL_NSOFT] = {
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MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
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MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
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MIPS_SOFT_INT_MASK_0, /* IPL_SOFTNET */
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@ -155,8 +155,15 @@ struct au_icu_intrhead au_icu_intrtab[NIRQS];
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#define NINTRS 4 /* MIPS INT0 - INT3 */
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struct au_intrhand {
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LIST_ENTRY(au_intrhand) ih_q;
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int (*ih_func)(void *);
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void *ih_arg;
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int ih_irq;
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};
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struct au_cpuintr {
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LIST_HEAD(, evbmips_intrhand) cintr_list;
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LIST_HEAD(, au_intrhand) cintr_list;
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struct evcnt cintr_count;
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};
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@ -199,7 +206,7 @@ void *
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au_intr_establish(int irq, int req, int level, int type,
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int (*func)(void *), void *arg)
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{
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struct evbmips_intrhand *ih;
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struct au_intrhand *ih;
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uint32_t icu_base;
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int cpu_int, s;
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struct au_chipdep *chip;
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@ -282,7 +289,7 @@ au_intr_establish(int irq, int req, int level, int type,
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void
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au_intr_disestablish(void *cookie)
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{
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struct evbmips_intrhand *ih = cookie;
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struct au_intrhand *ih = cookie;
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uint32_t icu_base;
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int irq, s;
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@ -318,11 +325,11 @@ au_intr_disestablish(void *cookie)
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}
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void
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au_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
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au_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
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{
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struct evbmips_intrhand *ih;
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struct au_intrhand *ih;
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int level;
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u_int32_t icu_base = 0, irqmask = 0; /* Both XXX gcc */
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uint32_t icu_base = 0, irqmask = 0; /* Both XXX gcc */
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for (level = 3; level >= 0; level--) {
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if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
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