Decode PCI Enhanced Allocation.
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msaitoh
parent
031ff5c667
commit
0ceebb2878
@ -1,4 +1,4 @@
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/* $NetBSD: pci_subr.c,v 1.206 2018/10/04 07:43:12 msaitoh Exp $ */
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/* $NetBSD: pci_subr.c,v 1.207 2018/11/05 03:51:31 msaitoh Exp $ */
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/*
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* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
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@ -40,7 +40,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.206 2018/10/04 07:43:12 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.207 2018/11/05 03:51:31 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_pci.h"
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@ -2409,7 +2409,167 @@ pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff)
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onoff("Transaction Pending", reg, PCI_AFSR_TP);
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}
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/* XXX pci_conf_print_ea_cap */
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static void
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pci_conf_print_ea_cap_prop(unsigned int prop)
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{
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switch (prop) {
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case PCI_EA_PROP_MEM_NONPREF:
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printf("Memory Space, Non-Prefetchable\n");
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break;
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case PCI_EA_PROP_MEM_PREF:
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printf("Memory Space, Prefetchable\n");
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break;
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case PCI_EA_PROP_IO:
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printf("I/O Space\n");
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break;
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case PCI_EA_PROP_VF_MEM_NONPREF:
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printf("Resorce for VF use, Memory Space, Non-Prefetchable\n");
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break;
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case PCI_EA_PROP_VF_MEM_PREF:
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printf("Resorce for VF use, Memory Space, Prefetch\n");
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break;
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case PCI_EA_PROP_BB_MEM_NONPREF:
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printf("Behind the Bridge, Memory Space, Non-Pref\n");
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break;
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case PCI_EA_PROP_BB_MEM_PREF:
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printf("Behind the Bridge, Memory Space. Prefetchable\n");
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break;
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case PCI_EA_PROP_BB_IO:
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printf("Behind Bridge, I/O Space\n");
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break;
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case PCI_EA_PROP_MEM_UNAVAIL:
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printf("Memory Space Unavailable\n");
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break;
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case PCI_EA_PROP_IO_UNAVAIL:
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printf("IO Space Unavailable\n");
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break;
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case PCI_EA_PROP_UNAVAIL:
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printf("Entry Unavailable for use\n");
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break;
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default:
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printf("Reserved\n");
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break;
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}
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}
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static void
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pci_conf_print_ea_cap(const pcireg_t *regs, int capoff)
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{
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pcireg_t reg, reg2;
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unsigned int entries, entoff, i;
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printf("\n Enhanced Allocation Capability Register\n");
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reg = regs[o2i(capoff + PCI_EA_CAP1)];
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printf(" EA Num Entries register: 0x%04x\n", reg >> 16);
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entries = __SHIFTOUT(reg, PCI_EA_CAP1_NUMENTRIES);
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printf(" EA Num Entries: %u\n", entries);
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/* Type 1 only */
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if (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) == PCI_HDRTYPE_PPB) {
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reg = regs[o2i(capoff + PCI_EA_CAP2)];
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printf(" EA Capability Second register: 0x%08x\n", reg);
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printf(" Fixed Secondary Bus Number: %hhu\n",
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(unsigned char)__SHIFTOUT(reg, PCI_EA_CAP2_SECONDARY));
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printf(" Fixed Subordinate Bus Number: %hhu\n",
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(unsigned char)__SHIFTOUT(reg, PCI_EA_CAP2_SUBORDINATE));
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entoff = capoff + 8;
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} else
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entoff = capoff + 4;
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for (i = 0; i < entries; i++) {
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uint64_t base, offset;
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bool baseis64, offsetis64;
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unsigned int bei, entry_size;
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printf(" Entry %u:\n", i);
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/* The first DW */
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reg = regs[o2i(entoff)];
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printf(" The first register: 0x%08x\n", reg);
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entry_size = __SHIFTOUT(reg, PCI_EA_ES);
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printf(" Entry size: %u\n", entry_size);
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printf(" BAR Equivalent Indicator: ");
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bei = __SHIFTOUT(reg, PCI_EA_BEI);
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switch (bei) {
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case PCI_EA_BEI_BAR0:
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case PCI_EA_BEI_BAR1:
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case PCI_EA_BEI_BAR2:
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case PCI_EA_BEI_BAR3:
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case PCI_EA_BEI_BAR4:
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case PCI_EA_BEI_BAR5:
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printf("BAR %u\n", bei - PCI_EA_BEI_BAR0);
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break;
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case PCI_EA_BEI_BEHIND:
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printf("Behind the function\n");
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break;
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case PCI_EA_BEI_NOTIND:
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printf("Not Indicated\n");
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break;
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case PCI_EA_BEI_EXPROM:
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printf("Expansion ROM\n");
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break;
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case PCI_EA_BEI_VFBAR0:
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case PCI_EA_BEI_VFBAR1:
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case PCI_EA_BEI_VFBAR2:
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case PCI_EA_BEI_VFBAR3:
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case PCI_EA_BEI_VFBAR4:
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case PCI_EA_BEI_VFBAR5:
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printf("VF BAR %u\n", bei - PCI_EA_BEI_VFBAR0);
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break;
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case PCI_EA_BEI_RESERVED:
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default:
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printf("Reserved\n");
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break;
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}
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printf(" Primary Properties: ");
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pci_conf_print_ea_cap_prop(__SHIFTOUT(reg, PCI_EA_PP));
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printf(" Secondary Properties: ");
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pci_conf_print_ea_cap_prop(__SHIFTOUT(reg, PCI_EA_SP));
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onoff("Writable", reg, PCI_EA_W);
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onoff("Enable for this entry", reg, PCI_EA_E);
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if (entry_size == 0) {
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entoff += 4;
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continue;
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}
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/* Base addr */
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reg = regs[o2i(entoff + 4)];
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base = reg & PCI_EA_LOWMASK;
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baseis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT;
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printf(" Base Address Register Low: 0x%08x\n", reg);
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if (baseis64) {
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/* 64bit */
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reg2 = regs[o2i(entoff + 12)];
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printf(" Base Address Register high: 0x%08x\n",
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reg2);
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base |= (uint64_t)reg2 << 32;
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}
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/* Offset addr */
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reg = regs[o2i(entoff + 8)];
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offset = reg & PCI_EA_LOWMASK;
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offsetis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT;
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printf(" Max Offset Register Low: 0x%08x\n", reg);
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if (offsetis64) {
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/* 64bit */
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reg2 = regs[o2i(entoff + (baseis64 ? 16 : 12))];
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printf(" Max Offset Register high: 0x%08x\n",
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reg2);
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offset |= (uint64_t)reg2 << 32;
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}
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printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64
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"\n", base, base + offset);
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entoff += 4;
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entoff += baseis64 ? 8 : 4;
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entoff += offsetis64 ? 8 : 4;
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}
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}
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/* XXX pci_conf_print_fpb_cap */
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static struct {
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@ -2439,7 +2599,7 @@ static struct {
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{ PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap },
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{ PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap },
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{ PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap},
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{ PCI_CAP_EA, "Enhanced Allocation", NULL },
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{ PCI_CAP_EA, "Enhanced Allocation", pci_conf_print_ea_cap },
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{ PCI_CAP_FPB, "Flattening Portal Bridge", NULL }
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};
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@ -1,4 +1,4 @@
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/* $NetBSD: pcireg.h,v 1.142 2018/10/03 06:46:09 msaitoh Exp $ */
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/* $NetBSD: pcireg.h,v 1.143 2018/11/05 03:51:31 msaitoh Exp $ */
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/*
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* Copyright (c) 1995, 1996, 1999, 2000
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@ -1866,6 +1866,54 @@ struct pci_rom {
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* Extended capability ID: 0x0014
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* Enhanced Allocation
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*/
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#define PCI_EA_CAP1 0x00 /* Capability First */
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#define PCI_EA_CAP1_NUMENTRIES __BITS(21, 16) /* Num Entries */
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#define PCI_EA_CAP2 0x04 /* Capability Second (for type1) */
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#define PCI_EA_CAP2_SECONDARY __BITS(7, 0) /* Fixed Secondary Bus No. */
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#define PCI_EA_CAP2_SUBORDINATE __BITS(15, 8) /* Fixed Subordinate Bus No. */
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/* Bit definitions for the first DW of each entry */
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#define PCI_EA_ES __BITS(2, 0) /* Entry Size */
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#define PCI_EA_BEI __BITS(7, 4) /* BAR Equivalent Indicator */
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#define PCI_EA_BEI_BAR0 0 /* BAR0 (10h) */
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#define PCI_EA_BEI_BAR1 1 /* BAR1 (14h) */
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#define PCI_EA_BEI_BAR2 2 /* BAR2 (18h) */
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#define PCI_EA_BEI_BAR3 3 /* BAR3 (1ch) */
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#define PCI_EA_BEI_BAR4 4 /* BAR4 (20h) */
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#define PCI_EA_BEI_BAR5 5 /* BAR5 (24h) */
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#define PCI_EA_BEI_BEHIND 6 /* Behind the function (for type1) */
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#define PCI_EA_BEI_NOTIND 7 /* Not Indicated */
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#define PCI_EA_BEI_EXPROM 8 /* Expansion ROM */
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#define PCI_EA_BEI_VFBAR0 9 /* VF BAR0 */
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#define PCI_EA_BEI_VFBAR1 10 /* VF BAR1 */
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#define PCI_EA_BEI_VFBAR2 11 /* VF BAR2 */
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#define PCI_EA_BEI_VFBAR3 12 /* VF BAR3 */
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#define PCI_EA_BEI_VFBAR4 13 /* VF BAR4 */
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#define PCI_EA_BEI_VFBAR5 14 /* VF BAR5 */
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#define PCI_EA_BEI_RESERVED 15 /* Reserved (treat as Not Indicated) */
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#define PCI_EA_PP __BITS(15, 8) /* Primary Properties */
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#define PCI_EA_SP __BITS(23, 16) /* Secondary Properties */
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/* PP and SP's values */
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#define PCI_EA_PROP_MEM_NONPREF 0x00 /* Memory Space, Non-Prefetchable */
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#define PCI_EA_PROP_MEM_PREF 0x01 /* Memory Space, Prefetchable */
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#define PCI_EA_PROP_IO 0x02 /* I/O Space */
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#define PCI_EA_PROP_VF_MEM_NONPREF 0x03 /* Resorce for VF use. Mem. Non-Pref */
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#define PCI_EA_PROP_VF_MEM_PREF 0x04 /* Resorce for VF use. Mem. Prefetch */
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#define PCI_EA_PROP_BB_MEM_NONPREF 0x05 /* Behind Bridge: MEM. Non-Pref */
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#define PCI_EA_PROP_BB_MEM_PREF 0x06 /* Behind Bridge: MEM. Prefetch */
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#define PCI_EA_PROP_BB_IO 0x07 /* Behind Bridge: I/O Space */
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#define PCI_EA_PROP_MEM_UNAVAIL 0xfd /* Memory Space Unavailable */
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#define PCI_EA_PROP_IO_UNAVAIL 0xfe /* IO Space Unavailable */
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#define PCI_EA_PROP_UNAVAIL 0xff /* Entry Unavailable for use */
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#define PCI_EA_W __BIT(30) /* Writable */
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#define PCI_EA_E __BIT(31) /* Enable for this entry */
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#define PCI_EA_LOWMASK __BITS(31, 2) /* Low register's mask */
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#define PCI_EA_BASEMAXOFFSET_S __BIT(1) /* Field Size */
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#define PCI_EA_BASEMAXOFFSET_64BIT __BIT(1) /* 64bit */
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#define PCI_EA_BASEMAXOFFSET_32BIT 0 /* 32bit */
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/*
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* Extended capability ID: 0x0015
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