Don't change a videomode that's been setup in the firmware.
Extend the register debugging output (and hopefully make it easier to read).
This commit is contained in:
jdc
parent
29517913b7
commit
0ca8bdd1bd
@ -1,4 +1,4 @@
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/* $NetBSD: machfb.c,v 1.102 2020/08/07 23:31:07 macallan Exp $ */
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/* $NetBSD: machfb.c,v 1.103 2020/10/10 08:29:32 jdc Exp $ */
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/*
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* Copyright (c) 2002 Bang Jun-Young
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@ -34,7 +34,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0,
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"$NetBSD: machfb.c,v 1.102 2020/08/07 23:31:07 macallan Exp $");
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"$NetBSD: machfb.c,v 1.103 2020/10/10 08:29:32 jdc Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -233,6 +233,7 @@ static int mach64_ref_freq(void);
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#ifdef MACHFB_DEBUG
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static void mach64_get_mode(struct mach64_softc *, struct videomode *);
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static void mach64_print_reg(struct mach64_softc *);
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#endif
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static int mach64_calc_crtcregs(struct mach64_softc *,
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@ -413,6 +414,7 @@ mach64_attach(device_t parent, device_t self, void *aux)
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struct mach64_softc *sc = device_private(self);
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struct pci_attach_args *pa = aux;
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struct rasops_info *ri;
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const char *mptr = NULL;
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prop_data_t edid_data;
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const struct videomode *mode = NULL;
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int bar, id, expected_id;
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@ -509,6 +511,7 @@ mach64_attach(device_t parent, device_t self, void *aux)
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(int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base);
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#ifdef MACHFB_DEBUG
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mach64_get_mode(sc, NULL);
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mach64_print_reg(sc);
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#endif
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prop_dictionary_get_uint32(device_properties(self), "width", &width);
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@ -517,8 +520,12 @@ mach64_attach(device_t parent, device_t self, void *aux)
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default_mode.hdisplay = width;
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default_mode.vdisplay = height;
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prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev),
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"videomode", &mptr);
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memset(&sc->sc_ei, 0, sizeof(sc->sc_ei));
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if ((edid_data = prop_dictionary_get(device_properties(self), "EDID"))
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if (mptr == NULL &&
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(edid_data = prop_dictionary_get(device_properties(self), "EDID"))
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!= NULL) {
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sc->sc_edid_size = uimin(1024, prop_data_size(edid_data));
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@ -923,8 +930,8 @@ mach64_get_mode(struct mach64_softc *sc, struct videomode *mode)
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{
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int htotal, hdisplay, hsync_start, hsync_end;
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int vtotal, vdisplay, vsync_start, vsync_end;
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int gen_ctl, clk_ctl, clock;
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int ref_freq, ref_div, mclk_fb_div, vclk_post_div, vclk_fb_div;
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int clk_ctl, clock;
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int ref_freq, ref_div, vclk_post_div, vclk_fb_div;
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int nhsync, nvsync;
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int post_div, dot_clock, vrefresh, vrefresh2;
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@ -932,27 +939,13 @@ mach64_get_mode(struct mach64_softc *sc, struct videomode *mode)
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hsync_end = regr(sc, CRTC_H_SYNC_STRT_WID);
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vdisplay = regr(sc, CRTC_V_TOTAL_DISP);
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vsync_end = regr(sc, CRTC_V_SYNC_STRT_WID);
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gen_ctl = regr(sc, CRTC_GEN_CNTL);
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clk_ctl = regr(sc, CLOCK_CNTL);
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clock = clk_ctl & 3;
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ref_div = regrb_pll(sc, PLL_REF_DIV);
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mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV);
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vclk_post_div = regrb_pll(sc, VCLK_POST_DIV);
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vclk_fb_div = regrb_pll(sc, VCLK0_FB_DIV + clock);
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ref_freq = mach64_ref_freq();
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aprint_normal_dev(sc->sc_dev, "CRTC registers:\n");
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aprint_normal("\th total: 0x%08x h sync: 0x%08x\n",
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hdisplay, hsync_end);
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aprint_normal("\tv total: 0x%08x v sync: 0x%08x\n",
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vdisplay, vsync_end);
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aprint_normal("\t g cntl: 0x%08x c cntl: 0x%08x\n",
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gen_ctl, clk_ctl);
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aprint_normal("\t rfreq %d rdiv: %d\n", ref_freq, ref_div);
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aprint_normal_dev(sc->sc_dev, "PLL registers:\n");
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aprint_normal("\t m div: 0x%02x p div: 0x%02x v%d div: 0x%02x\n",
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mclk_fb_div, vclk_post_div, clock, vclk_fb_div);
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htotal = ((hdisplay & 0x01ff) + 1) << 3;
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hdisplay = (((hdisplay & 0x1ff0000) >> 16) + 1) << 3;
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if (hsync_end & CRTC_HSYNC_NEG)
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@ -1015,6 +1008,55 @@ mach64_get_mode(struct mach64_softc *sc, struct videomode *mode)
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mode->flags |= VID_NVSYNC;
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}
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}
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static void
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mach64_print_reg(struct mach64_softc *sc)
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{
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struct reglist {
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int offset;
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const char *name;
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};
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static const struct reglist reglist_tab[] = {
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{ 0x0000, "CRTC_H_TOTAL_DISP" },
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{ 0x0004, "CRTC_H_SYNC_STRT_WID" },
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{ 0x0008, "CRTC_V_TOTAL_DISP" },
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{ 0x000C, "CRTC_V_SYNC_STRT_WID" },
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{ 0x0010, "CRTC_VLINE_CRNT_VLINE" },
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{ 0x0014, "CRTC_OFF_PITCH" },
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{ 0x001C, "CRTC_GEN_CNTL" },
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{ 0x0090, "CLOCK_CNTL" },
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{ 0, NULL }
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};
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static const struct reglist plllist_tab[] = {
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{ 0x02, "PLL_REF_DIV" },
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{ 0x03, "PLL_GEN_CNTL" },
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{ 0x04, "MCLK_FB_DIV" },
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{ 0x05, "PLL_VCLK_CNTL" },
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{ 0x06, "VCLK_POST_DIV" },
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{ 0x07, "VCLK0_FB_DIV" },
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{ 0x08, "VCLK1_FB_DIV" },
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{ 0x09, "VCLK2_FB_DIV" },
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{ 0x0A, "VCLK3_FB_DIV" },
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{ 0x0B, "PLL_XCLK_CNTL" },
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{ 0x10, "LVDSPLL_CNTL0" },
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{ 0x11, "LVDSPLL_CNTL0" },
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{ 0x19, "EXT_VPLL_CNTL" },
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{ 0x1A, "EXT_VPLL_REF_DIV" },
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{ 0x1B, "EXT_VPLL_FB_DIV" },
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{ 0x1C, "EXT_VPLL_MSB" },
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{ 0, NULL }
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};
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const struct reglist *r;
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aprint_normal("CRTC registers\n");
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for (r = reglist_tab; r->name != NULL; r++)
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aprint_normal("0x%04x 0x%08x %s\n", r->offset,
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regr(sc, r->offset), r->name);
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aprint_normal("PLL registers\n");
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for (r = plllist_tab; r->name != NULL; r++)
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aprint_normal("0x%02x 0x%02x %s\n", r->offset,
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regrb_pll(sc, r->offset), r->name);
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}
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#endif
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static int
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