New file with interrupt-handling code. Add intr_fasttrap().
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mycroft
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/*-
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* Copyright (c) 1993 Charles Hannum.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: intr.c,v 1.1 1993/10/22 19:27:40 mycroft Exp $
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/file.h>
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#include <sys/device.h>
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#include <sys/syslog.h>
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#include <machine/cpu.h>
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#include <machine/pio.h>
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#include <i386/isa/isa.h>
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#include <i386/isa/isavar.h>
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#include <i386/isa/icu.h>
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#include <i386/isa/timerreg.h>
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void isa_defaultirq __P((void));
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void isa_flushintrs __P((void));
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void isa_intrmaskwickedness __P((void));
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int intrmask[NIRQ];
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struct intrhand *intrhand[NIRQ];
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int fastvec;
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#define IDTVEC(name) __CONCAT(X,name)
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/* default interrupt vector table entries */
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extern *IDTVEC(intr)[];
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/* fast interrupt vector table */
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extern *IDTVEC(fast)[];
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/* out of range default interrupt vector gate entry */
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extern IDTVEC(wild);
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/*
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* Register a fast vector.
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*/
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void
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intr_fasttrap(intr, ih, class)
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int intr;
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struct intrhand *ih;
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{
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int irqnum = ffs(intr) - 1;
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#ifdef DIAGNOSTIC
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if (intr == IRQUNK || intr == IRQNONE ||
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(intr &~ (1 << irqnum)) != IRQNONE)
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panic("intr_fasttrap: weird irq");
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#endif
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if (fastvec & intr)
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panic("intr_fasttrap: irq is already fast vector");
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if (intrhand[irqnum])
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panic("intr_fasttrap: irq is already slow vector");
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fastvec |= intr;
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switch (class) {
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case DV_DULL:
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break;
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case DV_DISK:
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case DV_TAPE:
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biomask |= intr;
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break;
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case DV_IFNET:
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netmask |= intr;
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break;
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case DV_TTY:
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ttymask |= intr;
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break;
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case DV_CPU:
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default:
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panic("intr_fasttrap: weird devclass");
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}
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ih->ih_count = 0;
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ih->ih_next = NULL;
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intrhand[irqnum] = ih;
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setidt(irqnum, IDTVEC(fast)[irqnum], SDT_SYS386IGT, SEL_KPL);
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}
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/*
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* Register an interrupt handler.
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*/
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void
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intr_establish(intr, ih, class)
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int intr;
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struct intrhand *ih;
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enum devclass class;
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{
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int irqnum = ffs(intr) - 1;
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register struct intrhand **p, *q;
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#ifdef DIAGNOSTIC
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if (intr == IRQUNK || intr == IRQNONE ||
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(intr &~ (1 << irqnum)) != IRQNONE)
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panic("intr_establish: weird irq");
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#endif
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if (fastvec & intr)
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panic("intr_establish: irq is already fast vector");
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switch (class) {
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case DV_DULL:
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break;
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case DV_DISK:
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case DV_TAPE:
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biomask |= intr;
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break;
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case DV_IFNET:
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netmask |= intr;
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break;
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case DV_TTY:
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ttymask |= intr;
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break;
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case DV_CPU:
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default:
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panic("intr_establish: weird devclass");
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}
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ih->ih_count = 0;
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ih->ih_next = NULL;
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/*
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* This is O(N^2), but we want to preserve the order, and N is
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* always small.
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*/
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for (p = &intrhand[intr]; (q = *p) != NULL; p = &q->ih_next)
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;
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*p = ih;
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intr_enable(intr);
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}
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/*
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* Set up the masks for each interrupt handler based on the information
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* recorded by intr_establish().
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*/
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void
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isa_intrmaskwickedness()
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{
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int irq, mask;
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for (irq = 0; irq < NIRQ; irq++) {
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mask = (1 << irq) | astmask;
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if (biomask & (1 << irq))
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mask |= biomask;
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if (ttymask & (1 << irq))
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mask |= ttymask;
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if (netmask & (1 << irq))
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mask |= netmask;
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intrmask[irq] = mask;
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}
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impmask = netmask | ttymask;
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printf("biomask %x ttymask %x netmask %x impmask %x astmask %s\n",
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biomask, ttymask, netmask, impmask, astmask);
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}
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/*
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* Fill in default interrupt table, and mask all interrupts.
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*/
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void
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isa_defaultirq()
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{
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int i;
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/* icu vectors */
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for (i = ICU_OFFSET; i < ICU_OFFSET + ICU_LEN ; i++)
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setidt(i, IDTVEC(intr)[i], SDT_SYS386IGT, SEL_KPL);
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/* out of range vectors */
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for (; i < NIDT; i++)
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setidt(i, &IDTVEC(wild), SDT_SYS386IGT, SEL_KPL);
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/* initialize 8259's */
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outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU1+1, ICU_OFFSET); /* starting at this vector index */
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outb(IO_ICU1+1, IRQ_SLAVE);
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#ifdef AUTO_EOI_1
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outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
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#else
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outb(IO_ICU1+1, 1); /* 8086 mode */
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#endif
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outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
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outb(IO_ICU1, 0x0a); /* default to IRR on read */
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#ifdef REORDER_IRQ
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outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
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#endif
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outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */
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outb(IO_ICU2+1, ffs(IRQ_SLAVE)-1);
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#ifdef AUTO_EOI_2
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outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */
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#else
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outb(IO_ICU2+1, 1); /* 8086 mode */
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#endif
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outb(IO_ICU2+1, 0xff); /* leave interrupts masked */
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outb(IO_ICU2, 0x0a); /* default to IRR on read */
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}
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/*
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* Flush any pending interrupts.
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*/
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void
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isa_flushintrs()
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{
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register int i;
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/* clear any pending interrupts */
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for (i = 0; i < 8; i++) {
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outb(IO_ICU1, ICU_EOI);
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outb(IO_ICU2, ICU_EOI);
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}
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}
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/*
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* Determine what IRQ a device is using by trying to force it to generate an
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* interrupt and seeing which IRQ line goes high. It is not safe to call
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* this function after autoconfig.
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*/
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u_short
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isa_discoverintr(force, aux)
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void (*force)();
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{
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int time = TIMER_FREQ * 1; /* wait up to 1 second */
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u_int last, now;
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u_short iobase = IO_TIMER1;
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isa_flushintrs();
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/* attempt to force interrupt */
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force(aux);
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/* set timer 2 to a known state */
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outb(iobase + TIMER_MODE, TIMER_SEL2|TIMER_RATEGEN|TIMER_16BIT);
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outb(iobase + TIMER_CNTR2, 0xff);
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outb(iobase + TIMER_CNTR2, 0xff);
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last = 0xffff;
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while (time > 0) {
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register u_char irr, lo, hi;
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irr = inb(IO_ICU1) & ~IRQ_SLAVE;
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if (irr)
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return 1 << (ffs(irr) - 1);
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irr = inb(IO_ICU2);
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if (irr)
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return 1 << (ffs(irr) + 7);
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outb(iobase + TIMER_MODE, TIMER_SEL2|TIMER_LATCH);
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lo = inb(iobase + TIMER_CNTR2);
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hi = inb(iobase + TIMER_CNTR2);
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now = (hi << 8) | lo;
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if (now <= last)
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time -= (last - now);
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else
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time -= 0x10000 - (now - last);
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last = now;
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}
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return IRQNONE;
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}
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/*
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* Caught a stray interrupt, notify
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*/
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void
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isa_strayintr(d)
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int d;
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{
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extern u_long intrcnt_stray[],
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intrcnt_wild;
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/*
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* Stray interrupts on irq 7 occur when an interrupt line is raised
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* and then lowered before the CPU acknowledges it. This generally
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* means either the device is screwed or something is cli'ing too
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* long and it's timing out.
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*
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* -1 is passed by the generic handler for out of range exceptions,
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* since we don't really want 208 little vectors. (It wouldn't be
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* all that much code, but why bother?)
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*/
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if (d == -1) {
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intrcnt_wild++;
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log(LOG_ERR, "wild interrupt\n");
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} else {
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if (intrcnt_stray[d]++ < 5)
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log(LOG_ERR, "stray interrupt %d%s\n", d,
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intrcnt_stray[d] == 5 ? "; stopped logging" : "");
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}
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}
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/*
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* Handle a NMI, possibly a machine check.
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* return true to panic system, false to ignore.
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*
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* This implementation is hist[oe]rical.
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*/
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int
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isa_nmi()
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{
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log(LOG_CRIT, "NMI port 61 %x, port 70 %x\n", inb(0x61), inb(0x70));
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return 0;
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}
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