Drop cpuinfo's `L1_ptps'; instead keep a per CPU segment (level 2) page
table descriptor that is used to patch up a region (level 1) page table associated with a user pmap at context switch time.
This commit is contained in:
pk
parent
759e4c8f58
commit
0bf09a4ae7
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@ -1,4 +1,4 @@
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/* $NetBSD: cpuvar.h,v 1.17 1998/10/12 20:56:48 pk Exp $ */
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/* $NetBSD: cpuvar.h,v 1.18 1998/10/16 22:39:18 pk Exp $ */
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/*
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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@ -155,6 +155,7 @@ struct cpu_info {
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/* Context administration */
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int *ctx_tbl; /* [4m] SRMMU-edible context table */
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paddr_t ctx_tbl_pa; /* [4m] ctx table physical address */
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u_int cpu_seg_ptd; /* [4m] CPUINFO_VA segment ptp PA */
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union ctxinfo *ctxinfo;
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union ctxinfo *ctx_freelist; /* context free list */
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int ctx_kick; /* allocation rover when none free */
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@ -1,4 +1,4 @@
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# $NetBSD: genassym.cf,v 1.16 1998/10/12 21:50:22 pk Exp $
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# $NetBSD: genassym.cf,v 1.17 1998/10/16 22:39:18 pk Exp $
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#
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# Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -132,6 +132,9 @@ define SRUN SRUN
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define VM_PMAP offsetof(struct vmspace, vm_map.pmap)
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define PMAP_CTX offsetof(struct pmap, pm_ctx)
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define PMAP_CTXNUM offsetof(struct pmap, pm_ctxnum)
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define PMAP_REGPTPS offsetof(struct pmap, pm_reg_ptps)
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define REGTAB_CPU_OFF (int)(&((int *)0)[VA_VREG(CPUINFO_VA)])
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# interrupt/fault metering
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ifdef UVM
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@ -157,6 +160,8 @@ define CPUINFO_REDZONE offsetof(struct cpu_info, redzone)
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define REDSIZE REDSIZE
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define CPUINFO_IDLE_U offsetof(struct cpu_info, idle_u)
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define CPUINFO_CURPCB offsetof(struct cpu_info, curpcb)
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define CPUINFO_SEGPTD offsetof(struct cpu_info, cpu_seg_ptd)
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define CPUINFO_CPUNO offsetof(struct cpu_info, cpu_no)
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# PTE bits and related information
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define PG_W PG_W
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.102 1998/10/14 14:47:20 pk Exp $ */
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/* $NetBSD: locore.s,v 1.103 1998/10/16 22:39:17 pk Exp $ */
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/*
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* Copyright (c) 1996 Paul Kranenburg
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@ -4841,6 +4841,7 @@ Lsw_load:
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/* p does have a context: just switch to it */
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Lsw_havectx:
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! context is in %o0
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! pmap is in %o3
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#if (defined(SUN4) || defined(SUN4C)) && defined(SUN4M)
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sethi %hi(_cputyp), %o1 ! what cpu are we running on?
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ld [%o1 + %lo(_cputyp)], %o1
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@ -4865,6 +4866,15 @@ Lsw_havectx:
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jmpl %o2, %o7 ! this function must not clobber %o0 and %g7
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nop
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#if defined(MULTIPROCESSOR)
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/* Fixup CPUINFO_VA region table entry */
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sethi %hi(CPUINFO_VA+CPUINFO_SEGPTD), %o2
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ld [%o2 + %lo(CPUINFO_VA+CPUINFO_SEGPTD)], %o2
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ld [%o3 + PMAP_REGPTPS], %o3 ! load region table address
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add %o3, REGTAB_CPU_OFF, %o3 ! goto CPUINFO_VA segment entry
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st %o2, [%o3] ! switch to this CPU's segment
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#endif
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set SRMMU_CXR, %o1
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jmp %g7 + 8
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sta %o0, [%o1] ASI_SRMMU ! setcontext(vm->vm_pmap.pm_ctxnum);
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.132 1998/10/08 21:47:34 pk Exp $ */
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/* $NetBSD: pmap.c,v 1.133 1998/10/16 22:39:18 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -1921,15 +1921,27 @@ ctx_alloc(pm)
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/* Do any cache flush needed on context switch */
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(*cpuinfo.pure_vcache_flush)();
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#ifdef DEBUG
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#if 0
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ctxbusyvector[cnum] = 1; /* mark context as busy */
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#endif
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if (pm->pm_reg_ptps_pa == 0)
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panic("ctx_alloc: no region table in current pmap");
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#endif
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/*setcontext(0); * paranoia? can we modify curr. ctx? */
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#if defined(MULTIPROCESSOR)
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for (i = 0; i < ncpu; i++) {
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struct cpu_info *cpi = cpus[i];
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if (cpi == NULL)
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continue;
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setpgt4m(&cpi->ctx_tbl[cnum],
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(pm->pm_reg_ptps_pa >> SRMMU_PPNPASHIFT) |
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SRMMU_TEPTD);
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}
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/* Fixup CPUINFO_VA region table entry for current CPU */
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setpgt4m(&pm->pm_reg_ptps[VA_VREG(CPUINFO_VA)],
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cpuinfo.cpu_seg_ptd);
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#else
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setpgt4m(&cpuinfo.ctx_tbl[cnum],
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(pm->pm_reg_ptps_pa >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD);
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#endif
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setcontext4m(cnum);
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if (doflush)
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@ -3354,12 +3366,10 @@ pmap_bootstrap4m(void)
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setpgt4m(&cpuinfo.ctx_tbl[0],
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(pmap_kernel()->pm_reg_ptps_pa >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD);
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/* XXX:rethink - Store pointer to region table address */
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cpuinfo.L1_ptps = pmap_kernel()->pm_reg_ptps;
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for (reg = 0; reg < NKREG; reg++) {
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struct regmap *rp;
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caddr_t kphyssegtbl;
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u_int ptd;
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/*
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* Entering new region; install & build segtbl
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@ -3370,11 +3380,22 @@ pmap_bootstrap4m(void)
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kphyssegtbl = (caddr_t)
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&kernel_segtable_store[reg * SRMMU_L2SIZE];
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ptd = (VA2PA(kphyssegtbl) >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD;
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setpgt4m(&pmap_kernel()->pm_reg_ptps[reg + VA_VREG(KERNBASE)],
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(VA2PA(kphyssegtbl) >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD);
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ptd);
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rp->rg_seg_ptps = (int *)kphyssegtbl;
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if (reg + VA_VREG(KERNBASE) == VA_VREG(CPUINFO_VA)) {
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/*
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* Store the segment page table descriptor
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* corresponding to CPUINFO_VA, so we can install
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* this CPU-dependent translation into user pmaps
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* at context switch time.
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*/
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cpuinfo.cpu_seg_ptd = ptd;
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}
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if (rp->rg_segmap == NULL) {
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printf("rp->rg_segmap == NULL!\n");
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rp->rg_segmap = &kernel_segmap_store[reg * NSEGRG];
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@ -3627,6 +3648,21 @@ pmap_alloc_cpu(sc)
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segtable = regtable + SRMMU_L1SIZE;
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pagtable = segtable + SRMMU_L2SIZE;
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/*
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* Store the segment page table descriptor corresponding
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* to CPUINFO_VA, so we can install this CPU-dependent
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* translation into user pmaps at context switch time.
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* Note that the region table we allocate here (`regtable')
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* is only used in context 0 on this CPU. Non-zero context
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* numbers always have a user pmap associated with it.
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* That pmap's region table is fixed up at context switch
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* time so that the entry corresponding to CPUINFO_VA points
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* at the correct CPU's segment table (and hence the per-CPU
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* page table).
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*/
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sc->cpu_seg_ptd =
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(VA2PA((caddr_t)segtable) >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD;
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vr = VA_VREG(CPUINFO_VA);
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vs = VA_VSEG(CPUINFO_VA);
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vpg = VA_VPG(CPUINFO_VA);
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@ -3655,7 +3691,6 @@ pmap_alloc_cpu(sc)
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(SRMMU_TEPTE | PPROT_N_RWX | SRMMU_PG_C));
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sc->ctx_tbl = ctxtable;
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sc->L1_ptps = regtable;
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}
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#endif /* SUN4M */
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@ -3799,8 +3834,10 @@ pmap_pinit(pm)
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/* Copy kernel regions */
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for (i = 0; i < NKREG; i++) {
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setpgt4m(&pm->pm_reg_ptps[VA_VREG(KERNBASE) + i],
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cpuinfo.L1_ptps[VA_VREG(KERNBASE) + i]);
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int *kpt, *upt;
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kpt = &pmap_kernel()->pm_reg_ptps[VA_VREG(KERNBASE)];
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upt = &pm->pm_reg_ptps[VA_VREG(KERNBASE)];
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setpgt4m(&upt[i], kpt[i]);
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}
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}
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#endif
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