No functional change:
- Fix typo. - Remove trailing white spaces. - Capitalize comments. - Tabify. - KNF.
This commit is contained in:
parent
13b8fa7d71
commit
0be714dc99
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@ -1,4 +1,4 @@
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/* $NetBSD: bmtphy.c,v 1.30 2009/10/19 18:41:13 bouyer Exp $ */
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/* $NetBSD: bmtphy.c,v 1.31 2014/06/16 14:43:22 msaitoh Exp $ */
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/*-
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/*-
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* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
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* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
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@ -61,7 +61,7 @@
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*/
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*/
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#include <sys/cdefs.h>
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: bmtphy.c,v 1.30 2009/10/19 18:41:13 bouyer Exp $");
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__KERNEL_RCSID(0, "$NetBSD: bmtphy.c,v 1.31 2014/06/16 14:43:22 msaitoh Exp $");
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#include <sys/param.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/systm.h>
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@ -247,7 +247,7 @@ bmtphy_status(struct mii_softc *sc)
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if (bmcr & BMCR_AUTOEN) {
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if (bmcr & BMCR_AUTOEN) {
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/*
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/*
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* The media status bits are only valid of autonegotiation
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* The media status bits are only valid if autonegotiation
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* has completed (or it's disabled).
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* has completed (or it's disabled).
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*/
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*/
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if ((bmsr & BMSR_ACOMP) == 0) {
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if ((bmsr & BMSR_ACOMP) == 0) {
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@ -288,8 +288,7 @@ bmtphy_reset(struct mii_softc *sc)
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data = PHY_READ(sc, MII_BMTPHY_AUX2);
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data = PHY_READ(sc, MII_BMTPHY_AUX2);
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PHY_WRITE(sc, MII_BMTPHY_AUX2, data | 0x0020);
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PHY_WRITE(sc, MII_BMTPHY_AUX2, data | 0x0020);
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/* Enable clocks across APD for
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/* Enable clocks across APD for Auto-MDIX functionality */
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* Auto-MDIX functionality */
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data = PHY_READ(sc, MII_BMTPHY_INTR);
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data = PHY_READ(sc, MII_BMTPHY_INTR);
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PHY_WRITE(sc, MII_BMTPHY_INTR, data | 0x0004);
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PHY_WRITE(sc, MII_BMTPHY_INTR, data | 0x0004);
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@ -1,4 +1,4 @@
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/* $NetBSD: brgphyreg.h,v 1.7 2014/06/12 12:09:47 msaitoh Exp $ */
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/* $NetBSD: brgphyreg.h,v 1.8 2014/06/16 14:43:22 msaitoh Exp $ */
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/*
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/*
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* Copyright (c) 2000
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* Copyright (c) 2000
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@ -52,7 +52,7 @@
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#define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */
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#define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */
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#define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */
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#define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */
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#define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */
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#define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */
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#define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* Tx output disable d*/
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#define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* Tx output disabled */
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#define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */
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#define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */
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#define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */
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#define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */
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#define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */
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#define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */
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@ -85,7 +85,7 @@
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#define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */
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#define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */
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#define BRGPHY_MII_FCERRCNT 0x13 /* false carrier sense counter */
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#define BRGPHY_MII_FCERRCNT 0x13 /* False carrier sense counter */
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#define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */
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#define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */
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#define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */
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#define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */
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@ -140,14 +140,14 @@
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#define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */
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#define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */
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#define BRGPHY_MII_AUXSTS 0x19 /* AUX status */
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#define BRGPHY_MII_AUXSTS 0x19 /* AUX status */
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#define BRGPHY_AUXSTS_ACOMP 0x8000 /* autoneg complete */
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#define BRGPHY_AUXSTS_ACOMP 0x8000 /* Autoneg complete */
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#define BRGPHY_AUXSTS_AN_ACK 0x4000 /* autoneg complete ack */
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#define BRGPHY_AUXSTS_AN_ACK 0x4000 /* Autoneg complete ack */
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#define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* autoneg complete ack detect */
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#define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* Autoneg complete ack detect */
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#define BRGPHY_AUXSTS_AN_NPW 0x1000 /* autoneg next page wait */
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#define BRGPHY_AUXSTS_AN_NPW 0x1000 /* Autoneg next page wait */
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#define BRGPHY_AUXSTS_AN_RES 0x0700 /* AN HDC */
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#define BRGPHY_AUXSTS_AN_RES 0x0700 /* Autoneg HCD */
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#define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */
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#define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */
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#define BRGPHY_AUXSTS_RF 0x0040 /* remote fault */
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#define BRGPHY_AUXSTS_RF 0x0040 /* Remote fault */
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#define BRGPHY_AUXSTS_ANP_R 0x0020 /* AN page received */
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#define BRGPHY_AUXSTS_ANP_R 0x0020 /* Autoneg page received */
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#define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* LP AN ability */
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#define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* LP AN ability */
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#define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* LP Next page ability */
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#define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* LP Next page ability */
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#define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */
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#define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */
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@ -162,11 +162,11 @@
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#define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */
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#define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */
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#define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */
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#define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */
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#define BRGPHY_MII_ISR 0x1A /* interrupt status */
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#define BRGPHY_MII_ISR 0x1A /* Interrupt status */
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#define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */
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#define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */
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#define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */
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#define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */
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#define BRGPHY_ISR_HCT 0x1000 /* counter above 32K */
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#define BRGPHY_ISR_HCT 0x1000 /* Counter above 32K */
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#define BRGPHY_ISR_LCT 0x0800 /* all counter below 128 */
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#define BRGPHY_ISR_LCT 0x0800 /* All counter below 128 */
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#define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */
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#define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */
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#define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */
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#define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */
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#define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */
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#define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */
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#define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */
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#define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */
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#define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */
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#define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */
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#define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */
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#define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */
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#define BRGPHY_ISR_CRCERR 0x0001 /* CEC error */
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#define BRGPHY_ISR_CRCERR 0x0001 /* CRC error */
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#define BRGPHY_MII_IMR 0x1B /* interrupt mask */
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#define BRGPHY_MII_IMR 0x1B /* Interrupt mask */
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#define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */
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#define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */
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#define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */
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#define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */
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#define BRGPHY_IMR_HCT 0x1000 /* counter above 32K */
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#define BRGPHY_IMR_HCT 0x1000 /* Counter above 32K */
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#define BRGPHY_IMR_LCT 0x0800 /* all counter below 128 */
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#define BRGPHY_IMR_LCT 0x0800 /* All counter below 128 */
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#define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */
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#define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */
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#define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */
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#define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */
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#define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */
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#define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */
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#define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */
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#define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */
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#define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */
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#define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */
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#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */
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#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */
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#define BRGPHY_IMR_CRCERR 0x0001 /* CEC error */
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#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */
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/*******************************************************/
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/*******************************************************/
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/* Begin: PHY register values for the 5706 PHY */
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/* Begin: PHY register values for the 5706 PHY */
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/* $NetBSD: ciphyreg.h,v 1.4 2006/03/12 22:41:41 chs Exp $ */
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/* $NetBSD: ciphyreg.h,v 1.5 2014/06/16 14:43:22 msaitoh Exp $ */
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/*-
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/*-
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* Copyright (c) 2004
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* Copyright (c) 2004
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@ -172,7 +172,7 @@
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/* Vendor-specific PHY registers */
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/* Vendor-specific PHY registers */
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/* 100baseTX status extention register */
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/* 100baseTX status extension register */
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#define CIPHY_MII_100STS 0x10
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#define CIPHY_MII_100STS 0x10
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#define CIPHY_100STS_DESLCK 0x8000 /* descrambler locked */
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#define CIPHY_100STS_DESLCK 0x8000 /* descrambler locked */
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#define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */
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#define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */
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#define CIPHY_100STS_SSDERR 0x0200 /* false carrier error detected */
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#define CIPHY_100STS_SSDERR 0x0200 /* false carrier error detected */
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#define CIPHY_100STS_ESDERR 0x0100 /* premature end of stream error */
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#define CIPHY_100STS_ESDERR 0x0100 /* premature end of stream error */
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/* 1000BT status extention register #2 */
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/* 1000BT status extension register #2 */
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#define CIPHY_MII_1000STS2 0x11
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#define CIPHY_MII_1000STS2 0x11
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#define CIPHY_1000STS2_DESLCK 0x8000 /* descrambler locked */
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#define CIPHY_1000STS2_DESLCK 0x8000 /* descrambler locked */
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#define CIPHY_1000STS2_LKCERR 0x4000 /* lock error detected/lock lost */
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#define CIPHY_1000STS2_LKCERR 0x4000 /* lock error detected/lock lost */
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#define CIPHY_1000STS2_TXERR 0x0400 /* transmit error detected */
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#define CIPHY_1000STS2_TXERR 0x0400 /* transmit error detected */
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#define CIPHY_1000STS2_SSDERR 0x0200 /* false carrier error detected */
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#define CIPHY_1000STS2_SSDERR 0x0200 /* false carrier error detected */
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#define CIPHY_1000STS2_ESDERR 0x0100 /* premature end of stream error */
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#define CIPHY_1000STS2_ESDERR 0x0100 /* premature end of stream error */
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#define CIPHY_1000STS2_CARREXT 0x0080 /* carrier extention err detected */
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#define CIPHY_1000STS2_CARREXT 0x0080 /* carrier extension err detected */
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#define CIPHY_1000STS2_BCM5400 0x0040 /* non-complient BCM5400 detected */
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#define CIPHY_1000STS2_BCM5400 0x0040 /* non-complient BCM5400 detected */
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/* Bypass control register */
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/* Bypass control register */
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#define CIPHY_LED_LINKACTBLINK 0x0004 /* enable link/activity LED blink */
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#define CIPHY_LED_LINKACTBLINK 0x0004 /* enable link/activity LED blink */
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#define CIPHY_LED_BLINKRATE 0x0002 /* blink rate 0=10hz, 1=5hz */
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#define CIPHY_LED_BLINKRATE 0x0002 /* blink rate 0=10hz, 1=5hz */
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/* Auxilliary control and status register */
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/* Auxiliary control and status register */
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#define CIPHY_MII_AUXCSR 0x1C
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#define CIPHY_MII_AUXCSR 0x1C
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#define CIPHY_AUXCSR_ANEGDONE 0x8000 /* Autoneg complete */
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#define CIPHY_AUXCSR_ANEGDONE 0x8000 /* Autoneg complete */
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#define CIPHY_AUXCSR_ANEGOFF 0x4000 /* Autoneg disabled */
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#define CIPHY_AUXCSR_ANEGOFF 0x4000 /* Autoneg disabled */
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/* $NetBSD: gentbi.c,v 1.25 2014/06/11 22:34:26 msaitoh Exp $ */
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/* $NetBSD: gentbi.c,v 1.26 2014/06/16 14:43:22 msaitoh Exp $ */
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/*-
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/*-
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* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
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* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
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*/
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*/
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/*
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/*
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* Driver for generic ten-bit (1000BASE-SX) interfaces, built in to
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* Driver for generic ten-bit (1000BASE-SX) interfaces, built into
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* many Gigabit Ethernet chips.
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* many Gigabit Ethernet chips.
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*
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*
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* All we have to do here is correctly report speed and duplex.
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* All we have to do here is correctly report speed and duplex.
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*/
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*/
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#include <sys/cdefs.h>
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gentbi.c,v 1.25 2014/06/11 22:34:26 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: gentbi.c,v 1.26 2014/06/16 14:43:22 msaitoh Exp $");
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#include <sys/param.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/systm.h>
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if (bmcr & BMCR_AUTOEN) {
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if (bmcr & BMCR_AUTOEN) {
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/*
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/*
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* The media status bits are only valid of autonegotiation
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* The media status bits are only valid if autonegotiation
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* has completed (or it's disabled).
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* has completed (or it's disabled).
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*/
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*/
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if ((bmsr & BMSR_ACOMP) == 0) {
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if ((bmsr & BMSR_ACOMP) == 0) {
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/* $NetBSD: mii.h,v 1.17 2013/06/16 06:29:08 msaitoh Exp $ */
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/* $NetBSD: mii.h,v 1.18 2014/06/16 14:43:22 msaitoh Exp $ */
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/*
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/*
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* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
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* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
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/*
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/*
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* Note that the EXTSTAT bit indicates that there is extended status
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* Note that the EXTSTAT bit indicates that there is extended status
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* info available in register 15, but 802.3 section 22.2.4.3 also
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* info available in register 15, but 802.3 section 22.2.4.3 also
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* states that that all 1000 Mb/s capable PHYs will set this bit to 1.
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* states that all 1000 Mb/s capable PHYs will set this bit to 1.
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*/
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*/
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#define BMSR_MEDIAMASK (BMSR_100T4|BMSR_100TXFDX|BMSR_100TXHDX| \
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#define BMSR_MEDIAMASK (BMSR_100T4|BMSR_100TXFDX|BMSR_100TXHDX| \
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/* $NetBSD: nsphy.c,v 1.57 2009/10/19 18:41:14 bouyer Exp $ */
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/* $NetBSD: nsphy.c,v 1.58 2014/06/16 14:43:22 msaitoh Exp $ */
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/*-
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/*-
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* Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
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* Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
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@ -60,7 +60,7 @@
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*/
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*/
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#include <sys/cdefs.h>
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: nsphy.c,v 1.57 2009/10/19 18:41:14 bouyer Exp $");
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__KERNEL_RCSID(0, "$NetBSD: nsphy.c,v 1.58 2014/06/16 14:43:22 msaitoh Exp $");
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#include <sys/param.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/systm.h>
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@ -264,7 +264,7 @@ nsphy_status(struct mii_softc *sc)
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if (bmcr & BMCR_AUTOEN) {
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if (bmcr & BMCR_AUTOEN) {
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/*
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/*
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* The PAR status bits are only valid of autonegotiation
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* The PAR status bits are only valid if autonegotiation
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* has completed (or it's disabled).
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* has completed (or it's disabled).
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*/
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*/
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if ((bmsr & BMSR_ACOMP) == 0) {
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if ((bmsr & BMSR_ACOMP) == 0) {
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/* $NetBSD: rlphy.c,v 1.27 2011/01/20 14:26:11 pooka Exp $ */
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/* $NetBSD: rlphy.c,v 1.28 2014/06/16 14:43:22 msaitoh Exp $ */
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/* $OpenBSD: rlphy.c,v 1.20 2005/07/31 05:27:30 pvalchev Exp $ */
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/* $OpenBSD: rlphy.c,v 1.20 2005/07/31 05:27:30 pvalchev Exp $ */
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||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -38,7 +38,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <sys/cdefs.h>
|
#include <sys/cdefs.h>
|
||||||
__KERNEL_RCSID(0, "$NetBSD: rlphy.c,v 1.27 2011/01/20 14:26:11 pooka Exp $");
|
__KERNEL_RCSID(0, "$NetBSD: rlphy.c,v 1.28 2014/06/16 14:43:22 msaitoh Exp $");
|
||||||
|
|
||||||
#include <sys/param.h>
|
#include <sys/param.h>
|
||||||
#include <sys/systm.h>
|
#include <sys/systm.h>
|
||||||
|
|
|
@ -1,4 +1,4 @@
|
||||||
/* $NetBSD: ukphy_subr.c,v 1.11 2009/02/16 08:00:42 cegger Exp $ */
|
/* $NetBSD: ukphy_subr.c,v 1.12 2014/06/16 14:43:22 msaitoh Exp $ */
|
||||||
|
|
||||||
/*-
|
/*-
|
||||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||||
|
@ -35,7 +35,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <sys/cdefs.h>
|
#include <sys/cdefs.h>
|
||||||
__KERNEL_RCSID(0, "$NetBSD: ukphy_subr.c,v 1.11 2009/02/16 08:00:42 cegger Exp $");
|
__KERNEL_RCSID(0, "$NetBSD: ukphy_subr.c,v 1.12 2014/06/16 14:43:22 msaitoh Exp $");
|
||||||
|
|
||||||
#include <sys/param.h>
|
#include <sys/param.h>
|
||||||
#include <sys/systm.h>
|
#include <sys/systm.h>
|
||||||
|
@ -92,7 +92,7 @@ ukphy_status(struct mii_softc *phy)
|
||||||
anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);
|
anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);
|
||||||
if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &&
|
if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &&
|
||||||
(phy->mii_extcapabilities &
|
(phy->mii_extcapabilities &
|
||||||
(EXTSR_1000THDX|EXTSR_1000TFDX)) != 0) {
|
(EXTSR_1000THDX | EXTSR_1000TFDX)) != 0) {
|
||||||
gtcr = PHY_READ(phy, MII_100T2CR);
|
gtcr = PHY_READ(phy, MII_100T2CR);
|
||||||
gtsr = PHY_READ(phy, MII_100T2SR);
|
gtsr = PHY_READ(phy, MII_100T2SR);
|
||||||
} else
|
} else
|
||||||
|
|
Loading…
Reference in New Issue