Rewrite jazzio asc SCSI driver to use MI ncr53c9x and bus_dma(9) with
BUS_DMA_ALLOCNOW flag for jazzio bus DMAC. Tested on Soda's NEC Image RISCstation (which is an OEM of Acer PICA), and should fix port-arc/13388.
This commit is contained in:
tsutsui
parent
5e5ffccb2b
commit
0bcf529e7f
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@ -1,4 +1,4 @@
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/* $NetBSD: p_acer_pica_61.c,v 1.3 2002/12/28 16:44:44 tsutsui Exp $ */
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/* $NetBSD: p_acer_pica_61.c,v 1.4 2003/05/04 10:01:19 tsutsui Exp $ */
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/* $OpenBSD: picabus.c,v 1.11 1999/01/11 05:11:10 millert Exp $ */
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/*
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@ -38,16 +38,6 @@
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#include <arc/jazz/pica.h>
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#include <arc/jazz/jazziovar.h>
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#include "asc.h"
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#if NASC > 0
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#include <arc/jazz/ascvar.h>
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struct asc_config asc_acer_pica_61_conf = {
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&asc_timing_25mhz,
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0,
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};
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#endif
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/* ALI PICA 61 and some MAGNUM? */
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void p_acer_pica_61_init __P((void));
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@ -106,8 +96,4 @@ p_acer_pica_61_init()
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/* chipset-dependent jazzio bus configuration */
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jazzio_devconfig = acer_pica_61_cpu;
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#if NASC > 0
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asc_conf = &asc_acer_pica_61_conf;
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#endif
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: p_ms_jazz.c,v 1.3 2002/12/28 16:44:44 tsutsui Exp $ */
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/* $NetBSD: p_ms_jazz.c,v 1.4 2003/05/04 10:01:19 tsutsui Exp $ */
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/* $OpenBSD: picabus.c,v 1.11 1999/01/11 05:11:10 millert Exp $ */
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/*
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@ -39,12 +39,6 @@
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#include "com.h"
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#include "asc.h"
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#if NASC > 0
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#include <arc/jazz/ascreg.h>
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#include <arc/jazz/ascvar.h>
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#endif
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/* MAGNUM. NEC goes here too. */
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#ifndef COM_FREQ_MAGNUM
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@ -55,15 +49,6 @@
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#endif
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#endif /* COM_FREQ_MAGNUM */
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#if NASC > 0
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struct asc_config asc_ms_jazz_conf = {
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&asc_timing_40mhz,
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/* only if EPL is FE (Feature Enable bit for 53CF94) */
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ASC_CNFG3_FCLK, /* clock 40MHz */
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};
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#endif
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void p_ms_jazz_init __P((void));
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struct platform platform_microsoft_jazz = {
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@ -112,10 +97,6 @@ p_ms_jazz_init()
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/* jazzio bus configuration */
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jazzio_devconfig = mips_magnum_r4000_cpu;
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#if NASC > 0
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asc_conf = &asc_ms_jazz_conf;
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#endif
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#if NCOM > 0
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com_freq = COM_FREQ_MAGNUM;
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#endif
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@ -1,4 +1,4 @@
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# $NetBSD: GENERIC,v 1.84 2003/04/26 14:10:14 ragge Exp $
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# $NetBSD: GENERIC,v 1.85 2003/05/04 10:01:20 tsutsui Exp $
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#
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# GENERIC machine description file
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#
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@ -22,7 +22,7 @@ include "arch/arc/conf/std.arc"
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options INCLUDE_CONFIG_FILE # embed config file in kernel binary
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#ident "GENERIC-$Revision: 1.84 $"
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#ident "GENERIC-$Revision: 1.85 $"
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maxusers 32 # estimated number of users
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@ -190,7 +190,7 @@ sn0 at jazzio?
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fdc0 at jazzio?
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fd* at fdc? drive ?
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asc0 at jazzio? # NCR53C9x SCSI
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asc0 at jazzio? flags 0x000000 # NCR53C9x SCSI
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scsibus* at asc?
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osiop* at jazzio? flags 0x00000 # NCR53C710 SCSI
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@ -1,4 +1,4 @@
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# $NetBSD: RAMDISK,v 1.34 2003/04/06 10:00:00 tsutsui Exp $
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# $NetBSD: RAMDISK,v 1.35 2003/05/04 10:01:20 tsutsui Exp $
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#
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# memory disk based configuration file for MIPS R4x00 ARC Systems
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#
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@ -7,7 +7,7 @@ include "arch/arc/conf/std.arc"
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#options INCLUDE_CONFIG_FILE # embed config file in kernel binary
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#ident "GENERIC-$Revision: 1.34 $"
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#ident "GENERIC-$Revision: 1.35 $"
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maxusers 32 # estimated number of users
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@ -183,7 +183,7 @@ sn0 at jazzio?
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fdc0 at jazzio?
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fd* at fdc? drive ?
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asc0 at jazzio? # NCR53C9x SCSI
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asc0 at jazzio? flags 0x000000 # NCR53C9x SCSI
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scsibus* at asc?
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osiop* at jazzio? flags 0x00000 # NCR53C710 SCSI
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@ -1,4 +1,4 @@
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# $NetBSD: files.arc,v 1.42 2003/04/06 09:55:50 tsutsui Exp $
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# $NetBSD: files.arc,v 1.43 2003/05/04 10:01:20 tsutsui Exp $
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# $OpenBSD: files.arc,v 1.21 1999/09/11 10:20:20 niklas Exp $
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#
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# maxpartitions must be first item in files.${ARCH}
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@ -160,7 +160,7 @@ include "dev/i2o/files.i2o"
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include "dev/scsipi/files.scsipi"
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# Symbios 53C94 SCSI interface driver on Jazz-Internal bus
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device asc: scsi
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device asc: scsi, ncr53c9x
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attach asc at jazzio
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file arch/arc/jazz/asc.c asc needs-flag
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File diff suppressed because it is too large
Load Diff
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@ -1,338 +0,0 @@
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/* $NetBSD: ascreg.h,v 1.2 2003/05/03 18:10:45 wiz Exp $ */
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/* $OpenBSD: ascreg.h,v 1.1.1.1 1996/06/24 09:07:19 pefo Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)ascreg.h 8.1 (Berkeley) 6/10/93
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*/
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/*
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* Mach Operating System
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* Copyright (c) 1991,1990,1989 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* HISTORY
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* Log: scsi_53C94.h,v
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* Revision 2.4 91/02/05 17:44:59 mrt
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* Added author notices
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* [91/02/04 11:18:32 mrt]
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*
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* Changed to use new Mach copyright
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* [91/02/02 12:17:11 mrt]
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*
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* Revision 2.3 90/12/05 23:34:46 af
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* Documented max DMA xfer size.
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* [90/12/03 23:39:36 af]
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*
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* Revision 2.1.1.1 90/11/01 03:38:54 af
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* Created, from the DEC specs:
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* "PMAZ-AA TURBOchannel SCSI Module Functional Specification"
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* Workstation Systems Engineering, Palo Alto, CA. Aug 27, 1990.
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* And from the NCR data sheets
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* "NCR 53C94, 53C95, 53C96 Advanced SCSI Controller"
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* [90/09/03 af]
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*/
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/*
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* File: scsi_53C94.h
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* Author: Alessandro Forin, Carnegie Mellon University
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* Date: 9/90
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*
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* Defines for the NCR 53C94 ASC (SCSI interface)
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* Some gotcha came from the "86C01/53C94 DMA lab work" written
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* by Ken Stewart (NCR MED Logic Products Applications Engineer)
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* courtesy of NCR. Thanks Ken !
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*/
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#define ASC_OFFSET_53C94 0x0 /* from module base */
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#define ASC_NCMD 7 /* Number of simultaneous cmds */
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/*
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* Synch xfer parameters, and timing conversions
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*/
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#define SCSI_MIN_PERIOD 50 /* in 4 nsecs units */
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#define ASC_MIN_PERIOD40 8 /* in CLKS/BYTE, 1 CLK = 25nsecs */
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#define ASC_MIN_PERIOD25 5 /* in CLKS/BYTE, 1 CLK = 40nsecs */
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#define ASC_MIN_PERIOD12 3 /* in CLKS/BYTE, 1 CLK = 80nsecs */
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#define ASC_MAX_PERIOD40 56 /* in CLKS/BYTE, 1 CLK = 25nsecs */
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#define ASC_MAX_PERIOD25 35 /* in CLKS/BYTE, 1 CLK = 40nsecs */
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#define ASC_MAX_PERIOD12 18 /* in CLKS/BYTE, 1 CLK = 80nsecs */
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#define ASC_MAX_OFFSET 15 /* pure number */
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/*
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* Register map, padded as needed
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*/
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typedef volatile struct {
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u_char asc_tc_lsb; /* rw: Transfer Counter LSB */
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u_char asc_tc_msb; /* rw: Transfer Counter MSB */
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u_char asc_fifo; /* rw: FIFO top */
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u_char asc_cmd; /* rw: Command */
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u_char asc_status; /* r: Status */
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#define asc_dbus_id asc_status /* w: Destination Bus ID */
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u_char asc_intr; /* r: Interrupt */
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#define asc_sel_timo asc_intr /* w: (re)select timeout */
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u_char asc_ss; /* r: Sequence Step */
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#define asc_syn_p asc_ss /* w: synchronous period */
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u_char asc_flags; /* r: FIFO flags + seq step */
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#define asc_syn_o asc_flags /* w: synchronous offset */
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u_char asc_cnfg1; /* rw: Configuration 1 */
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u_char asc_ccf; /* w: Clock Conv. Factor */
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u_char asc_test; /* w: Test Mode */
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u_char asc_cnfg2; /* rw: Configuration 2 */
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u_char asc_cnfg3; /* rw: Configuration 3 */
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u_char asc_res_fifo; /* w: Reserve FIFO byte */
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#define asc_cnfg4 asc_res_fifo /* rw: Configuration 4 (53CF94) */
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u_char asc_tc_high; /* w: Transfer Counter High: 24bit (53CF94) */
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#define asc_id asc_tc_high /* r: ID Register */
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} asc_regmap_t;
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/*
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* Transfer Count: access macros
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* That a NOP is required after loading the DMA counter
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* I learned on the NCR test code. Sic.
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*/
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#define ASC_TC_MAX 0x10000
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#define ASC_TC_GET(ptr, val) \
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val = (ptr)->asc_tc_lsb | ((ptr)->asc_tc_msb << 8)
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#define ASC_TC_PUT(ptr, val, is24bit) \
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(ptr)->asc_tc_lsb = (val); \
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(ptr)->asc_tc_msb = (val) >> 8; \
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if (is24bit) (ptr)->asc_tc_high = 0; \
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(ptr)->asc_cmd = ASC_CMD_NOP | ASC_CMD_DMA;
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/*
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* Command register (command codes)
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*/
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#define ASC_CMD_DMA 0x80
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/* Miscellaneous */
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#define ASC_CMD_NOP 0x00
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#define ASC_CMD_FLUSH 0x01
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#define ASC_CMD_RESET 0x02
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#define ASC_CMD_BUS_RESET 0x03
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/* Initiator state */
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#define ASC_CMD_XFER_INFO 0x10
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#define ASC_CMD_I_COMPLETE 0x11
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#define ASC_CMD_MSG_ACPT 0x12
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#define ASC_CMD_XFER_PAD 0x18
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#define ASC_CMD_SET_ATN 0x1a
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#define ASC_CMD_CLR_ATN 0x1b
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/* Target state */
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#define ASC_CMD_SND_MSG 0x20
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#define ASC_CMD_SND_STATUS 0x21
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#define ASC_CMD_SND_DATA 0x22
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#define ASC_CMD_DISC_SEQ 0x23
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#define ASC_CMD_TERM 0x24
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#define ASC_CMD_T_COMPLETE 0x25
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#define ASC_CMD_DISC 0x27
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#define ASC_CMD_RCV_MSG 0x28
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#define ASC_CMD_RCV_CDB 0x29
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#define ASC_CMD_RCV_DATA 0x2a
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#define ASC_CMD_RCV_CMD 0x2b
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#define ASC_CMD_ABRT_DMA 0x04
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/* Disconnected state */
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#define ASC_CMD_RESELECT 0x40
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#define ASC_CMD_SEL 0x41
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#define ASC_CMD_SEL_ATN 0x42
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#define ASC_CMD_SEL_ATN_STOP 0x43
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#define ASC_CMD_ENABLE_SEL 0x44
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#define ASC_CMD_DISABLE_SEL 0x45
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#define ASC_CMD_SEL_ATN3 0x46
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/*
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* Status register, and phase encoding
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*/
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#define ASC_CSR_INT 0x80
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#define ASC_CSR_GE 0x40
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#define ASC_CSR_PE 0x20
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#define ASC_CSR_TC 0x10
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#define ASC_CSR_VGC 0x08
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#define ASC_CSR_MSG 0x04
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#define ASC_CSR_CD 0x02
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#define ASC_CSR_IO 0x01
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#define ASC_PHASE(csr) ((csr) & 0x7)
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#define ASC_PHASE_DATAO 0x0
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#define ASC_PHASE_DATAI 0x1
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#define ASC_PHASE_COMMAND 0x2
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#define ASC_PHASE_STATUS 0x3
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/* 4..5 ANSI reserved */
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#define ASC_PHASE_MSG_OUT 0x6
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#define ASC_PHASE_MSG_IN 0x7
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/*
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* Destination Bus ID
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*/
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#define ASC_DEST_ID_MASK 0x07
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/*
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* Interrupt register
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*/
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#define ASC_INT_RESET 0x80
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#define ASC_INT_ILL 0x40
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#define ASC_INT_DISC 0x20
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#define ASC_INT_BS 0x10
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#define ASC_INT_FC 0x08
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#define ASC_INT_RESEL 0x04
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#define ASC_INT_SEL_ATN 0x02
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#define ASC_INT_SEL 0x01
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/*
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* Timeout register:
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*
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* val = (timeout * CLK_freq) / (8192 * CCF);
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*/
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#define ASC_TIMEOUT_250(clk, ccf) (((clk) * 31) / (ccf))
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/*
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* Sequence Step register
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*/
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#define ASC_SS_RESERVED 0xf0
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#define ASC_SS_SOM 0x08
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#define ASC_SS_MASK 0x07
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#define ASC_SS(ss) ((ss) & ASC_SS_MASK)
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/*
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* Synchronous Transfer Period
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*/
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#define ASC_STP_MASK 0x1f
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#define ASC_STP_MIN 0x05 /* 5 clk per byte */
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#define ASC_STP_MAX 0x04 /* after ovfl, 35 clk/byte */
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/*
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* FIFO flags
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*/
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#define ASC_FLAGS_SEQ_STEP 0xe0
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#define ASC_FLAGS_FIFO_CNT 0x1f
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/*
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* Synchronous offset
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*/
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#define ASC_SYNO_MASK 0x0f /* 0 -> asyn */
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/*
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* Configuration 1
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*/
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#define ASC_CNFG1_SLOW 0x80
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#define ASC_CNFG1_SRD 0x40
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#define ASC_CNFG1_P_TEST 0x20
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#define ASC_CNFG1_P_CHECK 0x10
|
||||
#define ASC_CNFG1_TEST 0x08
|
||||
#define ASC_CNFG1_MY_BUS_ID 0x07
|
||||
|
||||
/*
|
||||
* CCF register
|
||||
*/
|
||||
|
||||
#define ASC_CCF(clk) (((((clk) - 1) / 5) + 1) & 0x7)
|
||||
|
||||
/*
|
||||
* Test register
|
||||
*/
|
||||
|
||||
#define ASC_TEST_XXXX 0xf8
|
||||
#define ASC_TEST_HI_Z 0x04
|
||||
#define ASC_TEST_I 0x02
|
||||
#define ASC_TEST_T 0x01
|
||||
|
||||
/*
|
||||
* Configuration 2
|
||||
*/
|
||||
|
||||
#define ASC_CNFG2_RFB 0x80
|
||||
#define ASC_CNFG2_EPL 0x40
|
||||
#define ASC_CNFG2_FE 0x40 /* 53CF94: Features Enable */
|
||||
#define ASC_CNFG2_EBC 0x20
|
||||
#define ASC_CNFG2_DREQ_HIZ 0x10
|
||||
#define ASC_CNFG2_SCSI2 0x08
|
||||
#define ASC_CNFG2_BPA 0x04
|
||||
#define ASC_CNFG2_RPE 0x02
|
||||
#define ASC_CNFG2_DPE 0x01
|
||||
|
||||
/*
|
||||
* Configuration 3
|
||||
*/
|
||||
|
||||
#define ASC_CNFG3_RESERVED 0xf8 /* 53C94 */
|
||||
#define ASC_CNFG3_IMRC 0x40 /* 53CF94: ID Message Reserved Check */
|
||||
#define ASC_CNFG3_QTE 0x40 /* 53CF94: Queue Tag Enable */
|
||||
#define ASC_CNFG3_CDB10 0x20 /* 53CF94: 10byte Group2 CDB */
|
||||
#define ASC_CNFG3_FSCSI 0x10 /* 53CF94: Fast SCSI */
|
||||
#define ASC_CNFG3_FCLK 0x08 /* 53CF94: Fast CLK (clock > 25MHz) */
|
||||
#define ASC_CNFG3_SRB 0x04
|
||||
#define ASC_CNFG3_ALT_DMA 0x02
|
||||
#define ASC_CNFG3_T8 0x01
|
||||
|
||||
/*
|
||||
* chip identifier
|
||||
*/
|
||||
#define ASC_ID_53CF94 0xa2 /* 53CF94-2 or 53CF96-2 */
|
||||
|
||||
#define ST_MASK 0x3e
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
struct asc_config {
|
||||
struct asc_timing *ac_timing;
|
||||
int ac_cnfg3;
|
||||
};
|
||||
|
||||
extern struct asc_config *asc_conf;
|
||||
|
||||
extern struct asc_timing asc_timing_40mhz, asc_timing_25mhz, asc_timing_12mhz;
|
||||
Loading…
Reference in New Issue